Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T212	7		T213	7		T214	7
all_values[1]	278	1		T212	7		T213	7		T214	7
all_values[2]	278	1		T212	7		T213	7		T214	7
all_values[3]	278	1		T212	7		T213	7		T214	7
all_values[4]	278	1		T212	7		T213	7		T214	7
all_values[5]	278	1		T212	7		T213	7		T214	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	870	1		T212	23		T213	25		T214	21
auto[1]	798	1		T212	19		T213	17		T214	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	555	1		T212	13		T213	11		T214	14
auto[1]	1113	1		T212	29		T213	31		T214	28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	980	1		T212	25		T213	20		T214	23
auto[1]	688	1		T212	17		T213	22		T214	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	80	1		T213	1		T214	4		T318	1
all_values[0]	auto[0]	auto[1]	auto[1]	90	1		T212	3		T213	1		T319	1
all_values[0]	auto[1]	auto[0]	auto[1]	45	1		T213	4		T214	1		T318	3
all_values[0]	auto[1]	auto[1]	auto[1]	63	1		T212	4		T213	1		T214	2
all_values[1]	auto[0]	auto[0]	auto[1]	79	1		T212	3		T213	2		T214	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1		T212	2		T213	1		T214	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T212	1		T213	2		T318	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1		T212	1		T213	2		T214	3
all_values[2]	auto[0]	auto[0]	auto[0]	99	1		T212	5		T213	3		T214	3
all_values[2]	auto[0]	auto[1]	auto[0]	72	1		T212	1		T213	1		T214	1
all_values[2]	auto[1]	auto[0]	auto[1]	58	1		T214	1		T320	1		T321	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T212	1		T213	3		T214	2
all_values[3]	auto[0]	auto[0]	auto[0]	99	1		T212	4		T213	1		T214	2
all_values[3]	auto[0]	auto[1]	auto[0]	82	1		T212	1		T213	3		T214	2
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T212	2		T213	3		T214	2
all_values[3]	auto[1]	auto[1]	auto[1]	42	1		T214	1		T321	1		T322	3
all_values[4]	auto[0]	auto[0]	auto[0]	48	1		T213	1		T214	1		T319	2
all_values[4]	auto[0]	auto[0]	auto[1]	23	1		T212	2		T323	2		T324	1
all_values[4]	auto[0]	auto[1]	auto[0]	49	1		T212	2		T213	2		T318	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T214	1		T318	1		T319	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1		T212	2		T213	3		T214	2
all_values[4]	auto[1]	auto[1]	auto[1]	60	1		T212	1		T213	1		T214	3
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T214	1		T318	1		T320	1
all_values[5]	auto[0]	auto[0]	auto[1]	30	1		T212	1		T213	3		T318	1
all_values[5]	auto[0]	auto[1]	auto[0]	52	1		T214	4		T318	1		T319	1
all_values[5]	auto[0]	auto[1]	auto[1]	21	1		T212	1		T213	1		T319	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T212	3		T213	2		T214	2
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T212	2		T213	1		T319	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal