Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343370	1		T1	1		T2	2		T3	1
all_values[1]	343370	1		T1	1		T2	2		T3	1
all_values[2]	343370	1		T1	1		T2	2		T3	1
all_values[3]	343370	1		T1	1		T2	2		T3	1
all_values[4]	343370	1		T1	1		T2	2		T3	1
all_values[5]	343370	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	692760	1		T1	6		T2	12		T3	6
auto[1]	1367460	1		T7	1300		T33	21108		T34	13272

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1003224	1		T1	4		T2	7		T3	4
auto[1]	1056996	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	343196	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	174	1		T271	4		T322	2		T323	4
all_values[1]	auto[0]	auto[1]	343224	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	146	1		T271	4		T323	2		T325	3
all_values[2]	auto[0]	auto[0]	1531	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	61	1		T322	2		T323	1		T325	1
all_values[2]	auto[1]	auto[0]	341740	1		T7	325		T33	5277		T34	3318
all_values[2]	auto[1]	auto[1]	38	1		T271	1		T323	1		T326	1
all_values[3]	auto[0]	auto[0]	1528	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	57	1		T323	1		T325	1		T326	1
all_values[3]	auto[1]	auto[0]	83623	1		T7	79		T33	1759		T34	1659
all_values[3]	auto[1]	auto[1]	258162	1		T7	246		T33	3518		T34	1659
all_values[4]	auto[0]	auto[0]	1083	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	491	1		T2	1		T4	1		T11	1
all_values[4]	auto[1]	auto[0]	230560	1		T7	242		T33	3518		T34	1659
all_values[4]	auto[1]	auto[1]	111236	1		T7	83		T33	1759		T34	1659
all_values[5]	auto[0]	auto[0]	1452	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	137	1		T4	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	341707	1		T7	325		T33	5277		T34	3318
all_values[5]	auto[1]	auto[1]	74	1		T271	4		T322	3		T326	3