Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240280	1		T1	5		T2	33		T4	362
auto[FlashEraseBank]	269739	1		T1	8		T2	39		T4	474

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	261697	1		T1	11		T4	241		T11	1
auto[FlashOpProgram]	229070	1		T1	2		T2	72		T4	595
auto[FlashOpErase]	15252	1		T12	9		T40	7		T19	14
auto[FlashOpInvalid]	4000	1		T76	200		T225	200		T226	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	261697	1		T1	11		T4	241		T11	1
op[FlashOpProgram]	229070	1		T1	2		T2	72		T4	595
op[FlashOpErase]	15252	1		T12	9		T40	7		T19	14
read_erase_read	667	1		T12	3		T40	3		T19	2
read_prog_read	805	1		T12	7		T6	9		T18	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	375215	1		T1	4		T2	72		T4	715
auto[FlashPartInfo]	131448	1		T1	9		T4	115		T11	1
auto[FlashPartInfo1]	863	1		T4	1		T7	28		T6	1
auto[FlashPartInfo2]	2493	1		T4	5		T7	55		T6	12

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	193270	1		T1	3		T4	162		T11	1
auto[FlashPartData]	auto[FlashOpProgram]	174342	1		T1	1		T2	72		T4	553
auto[FlashPartData]	auto[FlashOpErase]	3687	1		T12	9		T40	7		T70	29
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T76	194		T225	198		T226	198
auto[FlashPartInfo]	auto[FlashOpRead]	66176	1		T1	8		T4	75		T6	256
auto[FlashPartInfo]	auto[FlashOpProgram]	53715	1		T1	1		T4	40		T11	1
auto[FlashPartInfo]	auto[FlashOpErase]	11483	1		T19	14		T44	269		T27	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T76	6		T225	2		T226	2
auto[FlashPartInfo1]	auto[FlashOpRead]	696	1		T4	1		T7	28		T6	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T115	32		T85	32		T89	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T92	2		T409	1		T410	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T409	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1555	1		T4	3		T7	55		T6	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	852	1		T4	2		T6	1		T35	1
auto[FlashPartInfo2]	auto[FlashOpErase]	78	1		T108	1		T119	1		T116	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T411	2		T409	2		T412	2