Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29542	1		T40	4		T44	580		T177	740
auto[1]	13	1		T18	1		T342	4		T343	1
auto[2]	43	1		T1	1		T84	4		T344	2
auto[3]	85	1		T1	1		T75	4		T79	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7418	1		T40	1		T44	145		T75	1
evic_idx[1]	7412	1		T40	1		T44	145		T75	1
evic_idx[2]	7422	1		T1	1		T40	1		T44	145
evic_idx[3]	7431	1		T1	1		T18	1		T40	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28827	1		T44	580		T177	740		T181	144
evic_op[2]	288	1		T1	2		T18	1		T75	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7196	1		T44	145		T177	185		T181	36
evic_idx[0]	evic_op[1]	auto[1]	1	1		T342	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	2	1		T344	1		T345	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	10	1		T346	2		T347	4		T348	1
evic_idx[0]	evic_op[2]	auto[0]	53	1		T77	4		T227	9		T114	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T349	1		T350	1		T351	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T75	1		T37	1		T352	1
evic_idx[1]	evic_op[1]	auto[0]	7195	1		T44	145		T177	185		T181	36
evic_idx[1]	evic_op[1]	auto[1]	1	1		T342	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	1	1		T345	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	8	1		T346	2		T347	3		T348	1
evic_idx[1]	evic_op[2]	auto[0]	56	1		T77	4		T227	9		T114	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T353	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T75	1		T79	1		T354	1
evic_idx[2]	evic_op[1]	auto[0]	7196	1		T44	145		T177	185		T181	36
evic_idx[2]	evic_op[1]	auto[1]	1	1		T342	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T345	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	9	1		T346	1		T344	2		T355	1
evic_idx[2]	evic_op[2]	auto[0]	57	1		T77	4		T197	1		T227	9
evic_idx[2]	evic_op[2]	auto[1]	2	1		T343	1		T353	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T356	1		T351	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T1	1		T75	1		T354	1
evic_idx[3]	evic_op[1]	auto[0]	7195	1		T44	145		T177	185		T181	36
evic_idx[3]	evic_op[1]	auto[1]	1	1		T342	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	2	1		T344	1		T345	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	8	1		T346	1		T344	1		T355	1
evic_idx[3]	evic_op[2]	auto[0]	58	1		T77	4		T227	9		T114	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T18	1		T357	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T1	1		T356	1		T351	1
evic_idx[3]	evic_op[2]	auto[3]	20	1		T75	1		T352	1		T358	1