Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	26061	1		T289	2420		T331	7872		T332	1239
rd_lvl[2]	52042	1		T333	1232		T284	1509		T289	923
rd_lvl[3]	12206	1		T291	1386		T333	1988		T284	759
rd_lvl[4]	24635	1		T291	5717		T333	329		T334	5918
rd_lvl[5]	13691	1		T7	184		T291	948		T333	1557
rd_lvl[6]	17037	1		T7	56		T333	645		T335	2503
rd_lvl[7]	15864	1		T33	1997		T333	1120		T173	819
rd_lvl[8]	25699	1		T7	3		T33	1521		T333	1117
rd_lvl[9]	8353	1		T34	646		T333	1117		T336	295
rd_lvl[10]	5205	1		T34	1013		T29	174		T284	1
rd_lvl[11]	4379	1		T7	3		T29	1		T289	137
rd_lvl[12]	10279	1		T29	49		T284	5		T289	1
rd_lvl[13]	5159	1		T337	602		T30	196		T284	5
rd_lvl[14]	5445	1		T337	908		T30	207		T289	137
rd_lvl[15]	1832	1		T31	431		T338	144		T339	213