Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343370	1		T1	1		T2	2		T3	1
all_pins[1]	343370	1		T1	1		T2	2		T3	1
all_pins[2]	343370	1		T1	1		T2	2		T3	1
all_pins[3]	343370	1		T1	1		T2	2		T3	1
all_pins[4]	343370	1		T1	1		T2	2		T3	1
all_pins[5]	343370	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1713186	1		T1	6		T2	12		T3	6
values[0x1]	347034	1		T7	351		T33	5277		T34	3318
transitions[0x0=>0x1]	313935	1		T7	325		T33	5277		T34	3318
transitions[0x1=>0x0]	313914	1		T7	325		T33	5277		T34	3318

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	343196	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	174	1		T271	4		T322	2		T323	4
all_pins[0]	transitions[0x0=>0x1]	92	1		T271	1		T322	2		T323	3
all_pins[0]	transitions[0x1=>0x0]	64	1		T271	1		T323	1		T324	4
all_pins[1]	values[0x0]	343224	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	146	1		T271	4		T323	2		T325	3
all_pins[1]	transitions[0x0=>0x1]	128	1		T271	3		T323	1		T325	3
all_pins[1]	transitions[0x1=>0x0]	1221	1		T339	70		T359	24		T360	1107
all_pins[2]	values[0x0]	342131	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1239	1		T339	70		T359	24		T360	1107
all_pins[2]	transitions[0x0=>0x1]	32	1		T323	1		T326	1		T328	1
all_pins[2]	transitions[0x1=>0x0]	228315	1		T7	246		T33	3518		T34	1659
all_pins[3]	values[0x0]	113848	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	229522	1		T7	246		T33	3518		T34	1659
all_pins[3]	transitions[0x0=>0x1]	197795	1		T7	220		T33	3518		T34	1659
all_pins[3]	transitions[0x1=>0x0]	84152	1		T7	79		T33	1759		T34	1659
all_pins[4]	values[0x0]	227491	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	115879	1		T7	105		T33	1759		T34	1659
all_pins[4]	transitions[0x0=>0x1]	115865	1		T7	105		T33	1759		T34	1659
all_pins[4]	transitions[0x1=>0x0]	60	1		T271	4		T322	3		T326	3
all_pins[5]	values[0x0]	343296	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	74	1		T271	4		T322	3		T326	3
all_pins[5]	transitions[0x0=>0x1]	23	1		T271	1		T322	1		T361	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T271	1		T323	3		T325	3