Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	248125	1		T3	3		T4	2		T5	7
auto[FlashEraseBank]	272658	1		T3	1		T4	2		T5	7

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	260913	1		T3	4		T4	1		T5	12
auto[FlashOpProgram]	241297	1		T4	3		T5	2		T6	1
auto[FlashOpErase]	14573	1		T14	1		T7	56		T8	4
auto[FlashOpInvalid]	4000	1		T80	200		T81	200		T99	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	260913	1		T3	4		T4	1		T5	12
op[FlashOpProgram]	241297	1		T4	3		T5	2		T6	1
op[FlashOpErase]	14573	1		T14	1		T7	56		T8	4
read_erase_read	709	1		T7	6		T29	2		T70	8
read_prog_read	791	1		T6	1		T7	3		T25	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	389903	1		T3	4		T4	4		T5	5
auto[FlashPartInfo]	127364	1		T5	7		T6	9		T14	1
auto[FlashPartInfo1]	906	1		T10	1		T95	5		T38	1
auto[FlashPartInfo2]	2610	1		T5	2		T9	1		T10	12

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	197237	1		T3	4		T4	1		T5	5
auto[FlashPartData]	auto[FlashOpProgram]	184987	1		T4	3		T21	1		T7	30
auto[FlashPartData]	auto[FlashOpErase]	3767	1		T7	35		T8	4		T41	41
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T80	194		T81	198		T99	198
auto[FlashPartInfo]	auto[FlashOpRead]	61266	1		T5	5		T6	8		T7	545
auto[FlashPartInfo]	auto[FlashOpProgram]	55244	1		T5	2		T6	1		T21	2
auto[FlashPartInfo]	auto[FlashOpErase]	10778	1		T14	1		T7	21		T29	7
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T80	6		T81	2		T99	2
auto[FlashPartInfo1]	auto[FlashOpRead]	739	1		T10	1		T95	5		T38	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T101	1		T64	32		T86	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T87	1		T107	1		T403	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T403	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1671	1		T5	2		T9	1		T10	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	904	1		T10	5		T70	1		T36	2
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T85	1		T109	1		T404	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T109	2		T404	2		T405	2