Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27968	1		T7	8		T8	4		T41	1
auto[1]	21	1		T25	1		T36	3		T204	1
auto[2]	35	1		T221	1		T337	4		T155	4
auto[3]	60	1		T5	1		T6	1		T170	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7024	1		T6	1		T7	2		T8	1
evic_idx[1]	7023	1		T7	2		T8	1		T29	1
evic_idx[2]	7016	1		T5	1		T7	2		T8	1
evic_idx[3]	7021	1		T7	2		T8	1		T29	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27212	1		T41	1		T62	440		T93	652
evic_op[2]	356	1		T5	1		T6	1		T25	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[2]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[1]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6797	1		T62	110		T93	163		T80	100
evic_idx[0]	evic_op[1]	auto[2]	2	1		T337	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	5	1		T338	1		T339	1		T340	3
evic_idx[0]	evic_op[2]	auto[0]	72	1		T29	1		T341	4		T342	1
evic_idx[0]	evic_op[2]	auto[1]	7	1		T25	1		T36	1		T343	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T344	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T6	1		T345	1		T346	1
evic_idx[1]	evic_op[1]	auto[0]	6797	1		T62	110		T93	163		T80	100
evic_idx[1]	evic_op[1]	auto[1]	1	1		T347	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	2	1		T221	1		T337	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	5	1		T338	1		T339	1		T340	3
evic_idx[1]	evic_op[2]	auto[0]	75	1		T29	1		T98	1		T71	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T348	1		T349	1		T350	1
evic_idx[1]	evic_op[2]	auto[3]	10	1		T351	1		T352	1		T353	1
evic_idx[2]	evic_op[1]	auto[0]	6798	1		T41	1		T62	110		T93	163
evic_idx[2]	evic_op[1]	auto[3]	3	1		T340	3		-	-		-	-
evic_idx[2]	evic_op[2]	auto[0]	72	1		T29	1		T341	4		T342	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T36	1		T204	1		T348	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T5	1		T170	1		T351	1
evic_idx[3]	evic_op[1]	auto[0]	6797	1		T62	110		T93	163		T80	100
evic_idx[3]	evic_op[1]	auto[2]	1	1		T337	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	4	1		T338	1		T340	3		-	-
evic_idx[3]	evic_op[2]	auto[0]	72	1		T29	1		T341	4		T342	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T36	1		T354	1		T355	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T356	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	13	1		T276	1		T346	1		T357	1