Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	2225	1		T327	1017		T328	1208		-	-
rd_lvl[2]	27307	1		T327	279		T329	12708		T330	12336
rd_lvl[3]	12553	1		T327	2		T331	933		T332	684
rd_lvl[4]	52456	1		T273	5378		T333	5759		T327	1
rd_lvl[5]	15162	1		T33	1995		T272	2701		T273	1294
rd_lvl[6]	11343	1		T33	1079		T272	1114		T209	2753
rd_lvl[7]	11451	1		T209	349		T280	176		T334	1768
rd_lvl[8]	11372	1		T319	2783		T327	1		T32	744
rd_lvl[9]	4816	1		T319	375		T327	2		T32	230
rd_lvl[10]	7800	1		T327	1		T31	201		T280	89
rd_lvl[11]	7557	1		T34	541		T327	2		T31	51
rd_lvl[12]	6003	1		T34	1123		T187	1099		T335	148
rd_lvl[13]	2533	1		T23	668		T305	65		T327	1
rd_lvl[14]	7718	1		T23	1123		T305	10		T30	410
rd_lvl[15]	3428	1		T30	1337		T336	107		T188	221