Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	283490	1		T1	1		T2	1		T3	2
all_pins[1]	283490	1		T1	1		T2	1		T3	2
all_pins[2]	283490	1		T1	1		T2	1		T3	2
all_pins[3]	283490	1		T1	1		T2	1		T3	2
all_pins[4]	283490	1		T1	1		T2	1		T3	2
all_pins[5]	283490	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1397110	1		T1	6		T2	6		T3	12
values[0x1]	303830	1		T23	3582		T33	4565		T26	1456
transitions[0x0=>0x1]	275622	1		T23	3582		T33	4490		T26	1456
transitions[0x1=>0x0]	275604	1		T23	3582		T33	4490		T26	1456

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283333	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	157	1		T257	2		T258	4		T259	1
all_pins[0]	transitions[0x0=>0x1]	85	1		T258	4		T259	1		T321	6
all_pins[0]	transitions[0x1=>0x0]	75	1		T258	1		T259	2		T322	3
all_pins[1]	values[0x0]	283343	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	147	1		T257	2		T258	1		T259	2
all_pins[1]	transitions[0x0=>0x1]	121	1		T257	1		T258	1		T259	2
all_pins[1]	transitions[0x1=>0x0]	2570	1		T336	197		T188	1093		T360	1124
all_pins[2]	values[0x0]	280894	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	2596	1		T336	197		T188	1093		T360	1124
all_pins[2]	transitions[0x0=>0x1]	50	1		T257	3		T259	1		T321	2
all_pins[2]	transitions[0x1=>0x0]	184075	1		T23	1791		T33	3074		T34	1664
all_pins[3]	values[0x0]	96869	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	186621	1		T23	1791		T33	3074		T34	1664
all_pins[3]	transitions[0x0=>0x1]	161094	1		T23	1791		T33	2999		T34	1664
all_pins[3]	transitions[0x1=>0x0]	88741	1		T23	1791		T33	1416		T26	1456
all_pins[4]	values[0x0]	169222	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	114268	1		T23	1791		T33	1491		T26	1456
all_pins[4]	transitions[0x0=>0x1]	114258	1		T23	1791		T33	1491		T26	1456
all_pins[4]	transitions[0x1=>0x0]	31	1		T257	1		T258	1		T323	1
all_pins[5]	values[0x0]	283449	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	41	1		T257	1		T258	1		T323	1
all_pins[5]	transitions[0x0=>0x1]	14	1		T257	1		T258	1		T324	1
all_pins[5]	transitions[0x1=>0x0]	112	1		T257	2		T258	3		T259	1