Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	297732	1		T1	2		T2	2		T3	1
all_values[1]	297732	1		T1	2		T2	2		T3	1
all_values[2]	297732	1		T1	2		T2	2		T3	1
all_values[3]	297732	1		T1	2		T2	2		T3	1
all_values[4]	297732	1		T1	2		T2	2		T3	1
all_values[5]	297732	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	601671	1		T1	12		T2	12		T3	6
auto[1]	1184721	1		T7	496		T31	27936		T29	4296

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	863754	1		T1	7		T2	7		T3	4
auto[1]	922638	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	297581	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	151	1		T255	1		T256	3		T257	4
all_values[1]	auto[0]	auto[1]	297574	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	158	1		T256	3		T257	5		T315	4
all_values[2]	auto[0]	auto[0]	1572	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	58	1		T256	2		T257	2		T315	1
all_values[2]	auto[1]	auto[0]	296042	1		T7	124		T31	6984		T29	1074
all_values[2]	auto[1]	auto[1]	60	1		T255	1		T256	1		T315	3
all_values[3]	auto[0]	auto[0]	1572	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	54	1		T256	1		T257	1		T315	1
all_values[3]	auto[1]	auto[0]	75828	1		T7	62		T29	537		T226	1669
all_values[3]	auto[1]	auto[1]	220278	1		T7	62		T31	6984		T29	537
all_values[4]	auto[0]	auto[0]	1130	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	521	1		T1	1		T2	1		T9	1
all_values[4]	auto[1]	auto[0]	190079	1		T7	62		T31	5238		T29	537
all_values[4]	auto[1]	auto[1]	106002	1		T7	62		T31	1746		T29	537
all_values[5]	auto[0]	auto[0]	1479	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	130	1		T33	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	296052	1		T7	124		T31	6984		T29	1074
all_values[5]	auto[1]	auto[1]	71	1		T255	2		T256	2		T318	3