Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	2	14	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	2	14	87.50	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	247650	1		T1	600		T2	600		T3	3
auto[FlashEraseBank]	275269	1		T3	9		T9	1		T18	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	262826	1		T1	200		T2	200		T3	11
auto[FlashOpProgram]	239059	1		T1	100		T2	100		T3	1
auto[FlashOpErase]	17034	1		T1	100		T2	100		T9	3
auto[FlashOpInvalid]	4000	1		T1	200		T2	200		T19	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	262826	1		T1	200		T2	200		T3	11
op[FlashOpProgram]	239059	1		T1	100		T2	100		T3	1
op[FlashOpErase]	17034	1		T1	100		T2	100		T9	3
read_erase_read	626	1		T26	1		T32	2		T68	6
read_prog_read	782	1		T3	1		T18	1		T22	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	381260	1		T1	582		T2	594		T3	3
auto[FlashPartInfo]	138249	1		T1	18		T2	6		T3	8
auto[FlashPartInfo1]	757	1		T8	1		T38	3		T55	1
auto[FlashPartInfo2]	2653	1		T3	1		T19	6		T59	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase] , auto[FlashOpInvalid]]	--	--	2

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190724	1		T1	194		T2	198		T3	3
auto[FlashPartData]	auto[FlashOpProgram]	182815	1		T1	97		T2	99		T9	3
auto[FlashPartData]	auto[FlashOpErase]	3829	1		T1	97		T2	99		T9	3
auto[FlashPartData]	auto[FlashOpInvalid]	3892	1		T1	194		T2	198		T19	188
auto[FlashPartInfo]	auto[FlashOpRead]	69840	1		T1	6		T2	2		T3	7
auto[FlashPartInfo]	auto[FlashOpProgram]	55130	1		T1	3		T2	1		T3	1
auto[FlashPartInfo]	auto[FlashOpErase]	13181	1		T1	3		T2	1		T19	5
auto[FlashPartInfo]	auto[FlashOpInvalid]	98	1		T1	6		T2	2		T19	10
auto[FlashPartInfo1]	auto[FlashOpRead]	595	1		T8	1		T38	3		T55	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T60	32		T101	1		T28	32
auto[FlashPartInfo2]	auto[FlashOpRead]	1667	1		T3	1		T19	2		T7	62
auto[FlashPartInfo2]	auto[FlashOpProgram]	952	1		T19	1		T59	4		T36	2
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T19	1		T99	1		T103	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T19	2		T99	2		T336	2