Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	9	23	71.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	9	23	71.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32583	1		T1	400		T2	400		T19	400
auto[1]	12	1		T302	1		T303	1		T201	4
auto[2]	32	1		T133	8		T138	4		T304	16
auto[3]	54	1		T22	1		T64	2		T177	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8175	1		T1	100		T2	100		T19	100
evic_idx[1]	8165	1		T1	100		T2	100		T19	100
evic_idx[2]	8172	1		T1	100		T2	100		T19	100
evic_idx[3]	8169	1		T1	100		T2	100		T19	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31769	1		T1	400		T2	400		T19	400
evic_op[2]	288	1		T22	1		T64	2		T177	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	9	23	71.88	9

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	*	[auto[2]]	--	--	2
[evic_idx[2] , evic_idx[3]]	*	[auto[2]]	--	--	4

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7937	1		T1	100		T2	100		T19	100
evic_idx[0]	evic_op[1]	auto[1]	1	1		T305	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	5	1		T306	2		T307	2		T308	1
evic_idx[0]	evic_op[2]	auto[0]	64	1		T219	1		T101	2		T264	4
evic_idx[0]	evic_op[2]	auto[1]	1	1		T201	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T64	1		T177	1		T188	1
evic_idx[1]	evic_op[1]	auto[0]	7938	1		T1	100		T2	100		T19	100
evic_idx[1]	evic_op[1]	auto[3]	5	1		T306	2		T309	1		T307	2
evic_idx[1]	evic_op[2]	auto[0]	59	1		T101	2		T264	4		T82	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T303	1		T201	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	5	1		T91	1		T310	1		T190	1
evic_idx[2]	evic_op[1]	auto[0]	7937	1		T1	100		T2	100		T19	100
evic_idx[2]	evic_op[1]	auto[1]	1	1		T305	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	3	1		T306	1		T309	1		T307	1
evic_idx[2]	evic_op[2]	auto[0]	60	1		T101	2		T264	4		T82	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T201	1		T311	1		T312	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T22	1		T178	1		T313	1
evic_idx[3]	evic_op[1]	auto[0]	7937	1		T1	100		T2	100		T19	100
evic_idx[3]	evic_op[1]	auto[1]	1	1		T305	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	4	1		T306	2		T309	1		T314	1
evic_idx[3]	evic_op[2]	auto[0]	59	1		T112	1		T101	2		T264	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T302	1		T201	1		T312	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T64	1		T178	1		T313	1