Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	21464	1		T321	2613		T322	2216		T323	14554
rd_lvl[2]	27296	1		T321	1781		T322	2119		T323	10342
rd_lvl[3]	8222	1		T324	1362		T321	871		T322	1203
rd_lvl[4]	43122	1		T31	6023		T324	5793		T325	5509
rd_lvl[5]	10116	1		T31	961		T324	988		T325	1371
rd_lvl[6]	10410	1		T326	198		T327	2750		T321	9
rd_lvl[7]	11016	1		T327	692		T321	674		T322	1002
rd_lvl[8]	27327	1		T328	2763		T329	2830		T187	821
rd_lvl[9]	7520	1		T265	459		T328	355		T329	300
rd_lvl[10]	5504	1		T265	1082		T330	72		T321	430
rd_lvl[11]	4233	1		T7	39		T187	47		T331	321
rd_lvl[12]	4183	1		T7	21		T226	1400		T331	223
rd_lvl[13]	3330	1		T226	269		T332	436		T266	162
rd_lvl[14]	8130	1		T7	2		T29	250		T30	1157
rd_lvl[15]	4241	1		T29	276		T30	493		T333	378