Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	297732	1		T1	2		T2	2		T3	1
all_pins[1]	297732	1		T1	2		T2	2		T3	1
all_pins[2]	297732	1		T1	2		T2	2		T3	1
all_pins[3]	297732	1		T1	2		T2	2		T3	1
all_pins[4]	297732	1		T1	2		T2	2		T3	1
all_pins[5]	297732	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1466559	1		T1	12		T2	12		T3	6
values[0x1]	319833	1		T7	124		T31	8730		T29	1096
transitions[0x0=>0x1]	277865	1		T7	124		T31	6984		T29	1074
transitions[0x1=>0x0]	277848	1		T7	124		T31	6984		T29	1074

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	297581	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	151	1		T255	1		T256	3		T257	4
all_pins[0]	transitions[0x0=>0x1]	65	1		T255	1		T256	2		T257	1
all_pins[0]	transitions[0x1=>0x0]	72	1		T256	2		T257	2		T315	4
all_pins[1]	values[0x0]	297574	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	158	1		T256	3		T257	5		T315	4
all_pins[1]	transitions[0x0=>0x1]	128	1		T256	2		T257	5		T315	1
all_pins[1]	transitions[0x1=>0x0]	5178	1		T29	11		T30	1		T333	196
all_pins[2]	values[0x0]	292524	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	5208	1		T29	11		T30	1		T333	196
all_pins[2]	transitions[0x0=>0x1]	46	1		T255	1		T256	1		T315	3
all_pins[2]	transitions[0x1=>0x0]	196550	1		T7	62		T31	6984		T29	526
all_pins[3]	values[0x0]	96020	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	201712	1		T7	62		T31	6984		T29	537
all_pins[3]	transitions[0x0=>0x1]	165078	1		T7	62		T31	5238		T29	526
all_pins[3]	transitions[0x1=>0x0]	75899	1		T7	62		T29	537		T226	1669
all_pins[4]	values[0x0]	185199	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	112533	1		T7	62		T31	1746		T29	548
all_pins[4]	transitions[0x0=>0x1]	112517	1		T7	62		T31	1746		T29	548
all_pins[4]	transitions[0x1=>0x0]	55	1		T255	2		T256	2		T318	3
all_pins[5]	values[0x0]	297661	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	71	1		T255	2		T256	2		T318	3
all_pins[5]	transitions[0x0=>0x1]	31	1		T255	1		T318	1		T317	2
all_pins[5]	transitions[0x1=>0x0]	94	1		T256	1		T257	3		T315	2