Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T255	4		T256	7		T257	7
all_values[1]	272	1		T255	4		T256	7		T257	7
all_values[2]	272	1		T255	4		T256	7		T257	7
all_values[3]	272	1		T255	4		T256	7		T257	7
all_values[4]	272	1		T255	4		T256	7		T257	7
all_values[5]	272	1		T255	4		T256	7		T257	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	851	1		T255	14		T256	27		T257	22
auto[1]	781	1		T255	10		T256	15		T257	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	519	1		T255	12		T256	16		T257	16
auto[1]	1113	1		T255	12		T256	26		T257	26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	970	1		T255	19		T256	27		T257	25
auto[1]	662	1		T255	5		T256	15		T257	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	87	1		T255	3		T256	4		T257	3
all_values[0]	auto[0]	auto[1]	auto[1]	86	1		T256	2		T257	4		T315	1
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T255	1		T256	1		T315	4
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T315	1		T316	1		T317	2
all_values[1]	auto[0]	auto[0]	auto[1]	80	1		T255	3		T256	2		T315	3
all_values[1]	auto[0]	auto[1]	auto[1]	72	1		T256	1		T257	1		T315	3
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T255	1		T256	3		T257	2
all_values[1]	auto[1]	auto[1]	auto[1]	61	1		T256	1		T257	4		T318	4
all_values[2]	auto[0]	auto[0]	auto[0]	95	1		T255	2		T256	3		T257	3
all_values[2]	auto[0]	auto[1]	auto[0]	59	1		T255	1		T256	1		T257	2
all_values[2]	auto[1]	auto[0]	auto[1]	55	1		T256	2		T257	2		T315	2
all_values[2]	auto[1]	auto[1]	auto[1]	63	1		T255	1		T256	1		T315	2
all_values[3]	auto[0]	auto[0]	auto[0]	80	1		T255	2		T256	4		T257	2
all_values[3]	auto[0]	auto[1]	auto[0]	76	1		T255	1		T257	2		T315	3
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T256	1		T257	1		T315	1
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T255	1		T256	2		T257	2
all_values[4]	auto[0]	auto[0]	auto[0]	69	1		T255	2		T256	4		T257	1
all_values[4]	auto[0]	auto[0]	auto[1]	36	1		T256	1		T257	1		T315	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1		T255	2		T256	1		T257	1
all_values[4]	auto[0]	auto[1]	auto[1]	22	1		T318	1		T319	1		T320	1
all_values[4]	auto[1]	auto[0]	auto[1]	54	1		T256	1		T257	2		T315	2
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T257	2		T315	2		T318	1
all_values[5]	auto[0]	auto[0]	auto[0]	45	1		T256	1		T257	4		T315	4
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T315	2		T318	1		T319	1
all_values[5]	auto[0]	auto[1]	auto[0]	57	1		T255	2		T256	2		T257	1
all_values[5]	auto[0]	auto[1]	auto[1]	39	1		T255	1		T256	1		T318	2
all_values[5]	auto[1]	auto[0]	auto[1]	46	1		T257	1		T315	1		T318	4
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T255	1		T256	3		T257	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal