Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353746	1		T1	1		T2	2		T3	1
all_values[1]	353746	1		T1	1		T2	2		T3	1
all_values[2]	353746	1		T1	1		T2	2		T3	1
all_values[3]	353746	1		T1	1		T2	2		T3	1
all_values[4]	353746	1		T1	1		T2	2		T3	1
all_values[5]	353746	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	713760	1		T1	6		T2	12		T3	6
auto[1]	1408716	1		T5	24208		T20	14944		T21	4008

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1039521	1		T1	4		T2	7		T3	4
auto[1]	1082955	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	353574	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	172	1		T260	2		T261	4		T262	3
all_values[1]	auto[0]	auto[1]	353584	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	162	1		T260	7		T261	1		T262	4
all_values[2]	auto[0]	auto[0]	1584	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	67	1		T260	1		T262	1		T315	3
all_values[2]	auto[1]	auto[0]	352038	1		T5	6052		T20	3736		T21	1002
all_values[2]	auto[1]	auto[1]	57	1		T261	1		T311	2		T310	1
all_values[3]	auto[0]	auto[0]	1592	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	54	1		T260	2		T261	1		T310	1
all_values[3]	auto[1]	auto[0]	87343	1		T5	20		T20	934		T21	456
all_values[3]	auto[1]	auto[1]	264757	1		T5	6032		T20	2802		T21	546
all_values[4]	auto[0]	auto[0]	1138	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	510	1		T2	1		T17	1		T4	1
all_values[4]	auto[1]	auto[0]	242264	1		T5	5474		T20	2802		T21	456
all_values[4]	auto[1]	auto[1]	109834	1		T5	578		T20	934		T21	546
all_values[5]	auto[0]	auto[0]	1521	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	136	1		T35	1		T36	3		T37	1
all_values[5]	auto[1]	auto[0]	352041	1		T5	6052		T20	3736		T21	1002
all_values[5]	auto[1]	auto[1]	48	1		T315	1		T314	2		T316	3