Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240925	1		T1	281		T2	600		T5	312
auto[FlashEraseBank]	277341	1		T5	266		T17	24		T18	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263321	1		T1	141		T2	200		T5	578
auto[FlashOpProgram]	235992	1		T1	70		T2	100		T17	25
auto[FlashOpErase]	14953	1		T1	70		T2	100		T17	7
auto[FlashOpInvalid]	4000	1		T2	200		T4	200		T19	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263321	1		T1	141		T2	200		T5	578
op[FlashOpProgram]	235992	1		T1	70		T2	100		T17	25
op[FlashOpErase]	14953	1		T1	70		T2	100		T17	7
read_erase_read	675	1		T17	3		T30	3		T74	1
read_prog_read	845	1		T17	7		T6	7		T35	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	381388	1		T2	588		T17	37		T4	600
auto[FlashPartInfo]	133535	1		T1	281		T2	12		T5	578
auto[FlashPartInfo1]	803	1		T17	13		T20	18		T74	14
auto[FlashPartInfo2]	2540	1		T17	10		T19	6		T35	3

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	195253	1		T2	196		T17	22		T4	200
auto[FlashPartData]	auto[FlashOpProgram]	178363	1		T2	98		T17	10		T4	100
auto[FlashPartData]	auto[FlashOpErase]	3854	1		T2	98		T17	5		T4	100
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T2	196		T4	200		T19	190
auto[FlashPartInfo]	auto[FlashOpRead]	65871	1		T1	141		T2	4		T5	578
auto[FlashPartInfo]	auto[FlashOpProgram]	56520	1		T1	70		T2	2		T17	7
auto[FlashPartInfo]	auto[FlashOpErase]	11074	1		T1	70		T2	2		T17	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T2	4		T19	8		T96	2
auto[FlashPartInfo1]	auto[FlashOpRead]	640	1		T17	13		T20	18		T74	14
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T59	32		T76	32		T103	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T99	1		T81	1		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1557	1		T17	1		T19	2		T20	14
auto[FlashPartInfo2]	auto[FlashOpProgram]	948	1		T17	8		T19	1		T35	3
auto[FlashPartInfo2]	auto[FlashOpErase]	23	1		T17	1		T19	1		T74	3
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T19	2		T336	2		T337	2