Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28926	1		T1	132		T2	400		T17	4
auto[1]	15	1		T94	4		T181	4		T324	1
auto[2]	36	1		T213	4		T325	8		T120	16
auto[3]	82	1		T26	1		T212	16		T202	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7268	1		T1	33		T2	100		T17	1
evic_idx[1]	7262	1		T1	33		T2	100		T17	1
evic_idx[2]	7266	1		T1	33		T2	100		T17	1
evic_idx[3]	7263	1		T1	33		T2	100		T17	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28176	1		T1	132		T2	400		T4	400
evic_op[2]	324	1		T6	32		T65	1		T211	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7034	1		T1	33		T2	100		T4	100
evic_idx[0]	evic_op[1]	auto[2]	2	1		T325	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	8	1		T212	4		T326	1		T227	2
evic_idx[0]	evic_op[2]	auto[0]	64	1		T6	8		T211	4		T32	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T94	1		T181	1		T327	1
evic_idx[0]	evic_op[2]	auto[2]	2	1		T213	1		T328	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	14	1		T202	1		T209	1		T218	1
evic_idx[1]	evic_op[1]	auto[0]	7033	1		T1	33		T2	100		T4	100
evic_idx[1]	evic_op[1]	auto[2]	2	1		T325	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	8	1		T212	4		T326	1		T227	2
evic_idx[1]	evic_op[2]	auto[0]	63	1		T6	8		T211	4		T32	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T94	1		T181	1		T329	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T213	1		T328	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T202	1		T93	1		T330	1
evic_idx[2]	evic_op[1]	auto[0]	7034	1		T1	33		T2	100		T4	100
evic_idx[2]	evic_op[1]	auto[2]	2	1		T325	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	9	1		T212	4		T326	1		T227	2
evic_idx[2]	evic_op[2]	auto[0]	63	1		T6	8		T65	1		T211	4
evic_idx[2]	evic_op[2]	auto[1]	4	1		T94	1		T181	1		T331	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T213	1		T328	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	13	1		T26	1		T332	1		T333	1
evic_idx[3]	evic_op[1]	auto[0]	7034	1		T1	33		T2	100		T4	100
evic_idx[3]	evic_op[1]	auto[2]	2	1		T325	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	8	1		T212	4		T326	1		T227	2
evic_idx[3]	evic_op[2]	auto[0]	62	1		T6	8		T211	4		T32	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T94	1		T181	1		T324	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T213	1		T328	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	12	1		T209	1		T334	1		T204	1