Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
instr_type_cp	3	0	3	100.00	100	1	1	0
key_cp	2	0	2	100.00	100	1	1	2

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_instr_cross	6	0	6	100.00	100	1	1	0

Summary for Variable instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for instr_type_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	4842	1		T44	119		T45	133		T46	98
instr_types[0]	5910	1		T44	289		T45	126		T46	215
instr_types[1]	4212952	1		T3	16524		T5	16037		T18	140

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Summary for Variable key_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4221860	1		T3	16524		T5	16037		T18	140
auto[1]	1844	1		T44	193		T45	149		T46	194

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Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for key_instr_cross

Bins

key_cp	instr_type_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	others	4560	1		T44	76		T45	87		T46	84
auto[0]	instr_types[0]	5087	1		T44	193		T45	61		T46	133
auto[0]	instr_types[1]	4212213	1		T3	16524		T5	16037		T18	140
auto[1]	others	282	1		T44	43		T45	46		T46	14
auto[1]	instr_types[0]	823	1		T44	96		T45	65		T46	82
auto[1]	instr_types[1]	739	1		T44	54		T45	38		T46	98