Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	37673	1		T5	2010		T110	2433		T318	15325
rd_lvl[2]	53165	1		T5	953		T110	1104		T318	11123
rd_lvl[3]	5800	1		T5	379		T110	467		T282	1129
rd_lvl[4]	21173	1		T5	473		T110	376		T319	5496
rd_lvl[5]	19850	1		T5	219		T20	1462		T61	619
rd_lvl[6]	28086	1		T5	33		T20	1340		T61	210
rd_lvl[7]	8596	1		T5	170		T236	499		T110	205
rd_lvl[8]	15208	1		T5	163		T61	237		T33	843
rd_lvl[9]	4481	1		T5	240		T33	113		T174	275
rd_lvl[10]	6926	1		T5	84		T61	1		T110	88
rd_lvl[11]	3644	1		T5	187		T61	237		T33	100
rd_lvl[12]	3482	1		T5	2		T320	1491		T321	162
rd_lvl[13]	3407	1		T235	588		T320	282		T184	212
rd_lvl[14]	8373	1		T5	187		T235	1098		T110	25
rd_lvl[15]	4158	1		T21	281		T322	362		T323	261