Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353746	1		T1	1		T2	2		T3	1
all_pins[1]	353746	1		T1	1		T2	2		T3	1
all_pins[2]	353746	1		T1	1		T2	2		T3	1
all_pins[3]	353746	1		T1	1		T2	2		T3	1
all_pins[4]	353746	1		T1	1		T2	2		T3	1
all_pins[5]	353746	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1760182	1		T1	6		T2	12		T3	6
values[0x1]	362294	1		T5	5714		T20	4351		T21	1464
transitions[0x0=>0x1]	318524	1		T5	5120		T20	3736		T21	1002
transitions[0x1=>0x0]	318502	1		T5	5120		T20	3736		T21	1002

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	353574	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	172	1		T260	2		T261	4		T262	3
all_pins[0]	transitions[0x0=>0x1]	85	1		T260	1		T261	3		T311	2
all_pins[0]	transitions[0x1=>0x0]	75	1		T260	6		T262	1		T313	4
all_pins[1]	values[0x0]	353584	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	162	1		T260	7		T261	1		T262	4
all_pins[1]	transitions[0x0=>0x1]	132	1		T260	7		T262	4		T310	4
all_pins[1]	transitions[0x1=>0x0]	6108	1		T21	231		T323	1013		T338	1185
all_pins[2]	values[0x0]	347608	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	6138	1		T21	231		T323	1013		T338	1185
all_pins[2]	transitions[0x0=>0x1]	40	1		T261	1		T311	1		T310	1
all_pins[2]	transitions[0x1=>0x0]	224727	1		T5	5100		T20	2802		T21	315
all_pins[3]	values[0x0]	122921	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	230825	1		T5	5100		T20	2802		T21	546
all_pins[3]	transitions[0x0=>0x1]	193323	1		T5	4506		T20	2187		T21	315
all_pins[3]	transitions[0x1=>0x0]	87447	1		T5	20		T20	934		T21	456
all_pins[4]	values[0x0]	228797	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	124949	1		T5	614		T20	1549		T21	687
all_pins[4]	transitions[0x0=>0x1]	124926	1		T5	614		T20	1549		T21	687
all_pins[4]	transitions[0x1=>0x0]	25	1		T314	1		T316	1		T339	1
all_pins[5]	values[0x0]	353698	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	48	1		T315	1		T314	2		T316	3
all_pins[5]	transitions[0x0=>0x1]	18	1		T316	1		T340	1		T341	1
all_pins[5]	transitions[0x1=>0x0]	120	1		T260	2		T261	3		T262	2