Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T260	7		T261	4		T262	4
all_values[1]	281	1		T260	7		T261	4		T262	4
all_values[2]	281	1		T260	7		T261	4		T262	4
all_values[3]	281	1		T260	7		T261	4		T262	4
all_values[4]	281	1		T260	7		T261	4		T262	4
all_values[5]	281	1		T260	7		T261	4		T262	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	881	1		T260	19		T261	11		T262	17
auto[1]	805	1		T260	23		T261	13		T262	7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	532	1		T260	17		T261	8		T262	10
auto[1]	1154	1		T260	25		T261	16		T262	14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	973	1		T260	30		T261	14		T262	14
auto[1]	713	1		T260	12		T261	10		T262	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	75	1		T260	3		T261	1		T262	1
all_values[0]	auto[0]	auto[1]	auto[1]	86	1		T260	2		T261	2		T262	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T260	1		T262	2		T310	1
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T260	1		T261	1		T311	2
all_values[1]	auto[0]	auto[0]	auto[1]	85	1		T260	2		T261	2		T311	2
all_values[1]	auto[0]	auto[1]	auto[1]	84	1		T260	4		T262	1		T310	3
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T262	3		T311	2		T310	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T260	1		T261	2		T310	1
all_values[2]	auto[0]	auto[0]	auto[0]	83	1		T260	5		T261	2		T262	2
all_values[2]	auto[0]	auto[1]	auto[0]	74	1		T260	1		T261	1		T262	1
all_values[2]	auto[1]	auto[0]	auto[1]	72	1		T260	1		T312	1		T313	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1		T261	1		T262	1		T311	2
all_values[3]	auto[0]	auto[0]	auto[0]	82	1		T260	1		T261	2		T262	1
all_values[3]	auto[0]	auto[1]	auto[0]	80	1		T260	2		T261	1		T262	1
all_values[3]	auto[1]	auto[0]	auto[1]	56	1		T260	1		T261	1		T310	2
all_values[3]	auto[1]	auto[1]	auto[1]	63	1		T260	3		T262	2		T311	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T262	1		T311	4		T310	3
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T260	1		T261	1		T262	1
all_values[4]	auto[0]	auto[1]	auto[0]	32	1		T260	1		T310	1		T312	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T260	1		T313	1		T314	1
all_values[4]	auto[1]	auto[0]	auto[1]	68	1		T260	2		T261	1		T262	2
all_values[4]	auto[1]	auto[1]	auto[1]	60	1		T260	2		T261	2		T310	1
all_values[5]	auto[0]	auto[0]	auto[0]	61	1		T260	2		T261	1		T262	4
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T310	1		T315	2		T314	2
all_values[5]	auto[0]	auto[1]	auto[0]	58	1		T260	5		T261	1		T311	3
all_values[5]	auto[0]	auto[1]	auto[1]	20	1		T314	1		T316	2		T317	1
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T310	3		T313	1		T315	3
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T261	2		T313	1		T314	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal