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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.41 95.79 94.12 98.85 91.84 98.09 98.10 98.06


Total test records in report: 1246
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T1079 /workspace/coverage/default/8.flash_ctrl_error_prog_win.2037586467 May 21 03:19:20 PM PDT 24 May 21 03:33:22 PM PDT 24 848095900 ps
T1080 /workspace/coverage/default/12.flash_ctrl_re_evict.61483065 May 21 03:21:09 PM PDT 24 May 21 03:21:43 PM PDT 24 371871400 ps
T1081 /workspace/coverage/default/22.flash_ctrl_alert_test.884337200 May 21 03:23:48 PM PDT 24 May 21 03:24:06 PM PDT 24 139250100 ps
T1082 /workspace/coverage/default/1.flash_ctrl_serr_counter.77860503 May 21 03:13:46 PM PDT 24 May 21 03:15:18 PM PDT 24 2989463000 ps
T1083 /workspace/coverage/default/17.flash_ctrl_rand_ops.3141729357 May 21 03:22:34 PM PDT 24 May 21 03:34:23 PM PDT 24 744034300 ps
T1084 /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3662822778 May 21 03:20:52 PM PDT 24 May 21 03:21:06 PM PDT 24 15555200 ps
T1085 /workspace/coverage/default/35.flash_ctrl_intr_rd.977842581 May 21 03:25:18 PM PDT 24 May 21 03:28:21 PM PDT 24 1221894800 ps
T1086 /workspace/coverage/default/13.flash_ctrl_disable.2618721548 May 21 03:21:26 PM PDT 24 May 21 03:21:49 PM PDT 24 47395000 ps
T1087 /workspace/coverage/default/14.flash_ctrl_rw_evict.2657632559 May 21 03:21:50 PM PDT 24 May 21 03:22:23 PM PDT 24 64485100 ps
T327 /workspace/coverage/default/4.flash_ctrl_fs_sup.3793354998 May 21 03:17:25 PM PDT 24 May 21 03:18:07 PM PDT 24 1395262700 ps
T1088 /workspace/coverage/default/8.flash_ctrl_prog_reset.2931288626 May 21 03:19:30 PM PDT 24 May 21 03:19:44 PM PDT 24 56357500 ps
T179 /workspace/coverage/default/2.flash_ctrl_otp_reset.366689067 May 21 03:14:30 PM PDT 24 May 21 03:16:39 PM PDT 24 77094300 ps
T1089 /workspace/coverage/default/17.flash_ctrl_invalid_op.2504165581 May 21 03:22:37 PM PDT 24 May 21 03:23:50 PM PDT 24 1706582600 ps
T305 /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1528589976 May 21 03:25:40 PM PDT 24 May 21 03:27:26 PM PDT 24 4662238300 ps
T1090 /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3534930774 May 21 03:15:48 PM PDT 24 May 21 03:16:26 PM PDT 24 44348300 ps
T1091 /workspace/coverage/default/11.flash_ctrl_connect.4137989603 May 21 03:20:52 PM PDT 24 May 21 03:21:06 PM PDT 24 16028400 ps
T1092 /workspace/coverage/default/0.flash_ctrl_phy_arb.2598413343 May 21 03:12:00 PM PDT 24 May 21 03:23:51 PM PDT 24 53769962700 ps
T1093 /workspace/coverage/default/30.flash_ctrl_otp_reset.3504614489 May 21 03:24:47 PM PDT 24 May 21 03:26:40 PM PDT 24 134737200 ps
T1094 /workspace/coverage/default/11.flash_ctrl_smoke.419227709 May 21 03:20:37 PM PDT 24 May 21 03:22:15 PM PDT 24 31881300 ps
T1095 /workspace/coverage/default/0.flash_ctrl_rd_intg.189348107 May 21 03:12:49 PM PDT 24 May 21 03:13:22 PM PDT 24 235049100 ps
T1096 /workspace/coverage/default/15.flash_ctrl_otp_reset.1935238278 May 21 03:21:54 PM PDT 24 May 21 03:24:07 PM PDT 24 44571100 ps
T1097 /workspace/coverage/default/45.flash_ctrl_alert_test.147573114 May 21 03:26:13 PM PDT 24 May 21 03:26:29 PM PDT 24 45806000 ps
T1098 /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.157575523 May 21 03:23:52 PM PDT 24 May 21 03:24:47 PM PDT 24 2322274100 ps
T1099 /workspace/coverage/default/15.flash_ctrl_wo.1445863012 May 21 03:22:01 PM PDT 24 May 21 03:25:12 PM PDT 24 2424153900 ps
T1100 /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1575704493 May 21 03:20:55 PM PDT 24 May 21 03:21:10 PM PDT 24 15301200 ps
T1101 /workspace/coverage/default/8.flash_ctrl_rw.3714228026 May 21 03:19:26 PM PDT 24 May 21 03:28:21 PM PDT 24 5235324500 ps
T1102 /workspace/coverage/default/9.flash_ctrl_error_prog_win.3658753428 May 21 03:19:48 PM PDT 24 May 21 03:34:53 PM PDT 24 7174093700 ps
T1103 /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2921040218 May 21 03:23:00 PM PDT 24 May 21 03:24:14 PM PDT 24 10020223900 ps
T1104 /workspace/coverage/default/0.flash_ctrl_stress_all.4167464588 May 21 03:12:43 PM PDT 24 May 21 03:33:14 PM PDT 24 263074700 ps
T1105 /workspace/coverage/default/20.flash_ctrl_connect.2011343023 May 21 03:23:33 PM PDT 24 May 21 03:23:50 PM PDT 24 16849700 ps
T1106 /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.655146261 May 21 03:25:07 PM PDT 24 May 21 03:27:19 PM PDT 24 7630293500 ps
T62 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3827810539 May 21 02:38:58 PM PDT 24 May 21 02:40:22 PM PDT 24 1203101500 ps
T260 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.230390360 May 21 02:38:42 PM PDT 24 May 21 02:39:33 PM PDT 24 32657600 ps
T261 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1508703677 May 21 02:39:02 PM PDT 24 May 21 02:39:52 PM PDT 24 15823700 ps
T262 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.193646057 May 21 02:39:36 PM PDT 24 May 21 02:40:11 PM PDT 24 16937400 ps
T1107 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1503702875 May 21 02:39:30 PM PDT 24 May 21 02:40:08 PM PDT 24 11328100 ps
T194 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2004313594 May 21 02:39:08 PM PDT 24 May 21 02:39:58 PM PDT 24 74848600 ps
T195 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1563557490 May 21 02:39:16 PM PDT 24 May 21 02:40:02 PM PDT 24 48340600 ps
T1108 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3332448801 May 21 02:39:25 PM PDT 24 May 21 02:40:04 PM PDT 24 37171200 ps
T1109 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4283983977 May 21 02:39:01 PM PDT 24 May 21 02:39:53 PM PDT 24 15286300 ps
T63 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1348372471 May 21 02:39:32 PM PDT 24 May 21 02:47:27 PM PDT 24 188559800 ps
T311 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3761119874 May 21 02:39:35 PM PDT 24 May 21 02:40:10 PM PDT 24 23648600 ps
T64 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2691295712 May 21 02:39:19 PM PDT 24 May 21 02:40:01 PM PDT 24 79513200 ps
T224 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2158973463 May 21 02:39:26 PM PDT 24 May 21 02:40:10 PM PDT 24 59255400 ps
T1110 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.749618246 May 21 02:41:03 PM PDT 24 May 21 02:41:31 PM PDT 24 11855600 ps
T310 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3150913943 May 21 02:39:33 PM PDT 24 May 21 02:40:09 PM PDT 24 28710700 ps
T198 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2149273912 May 21 02:38:53 PM PDT 24 May 21 02:40:28 PM PDT 24 4872375100 ps
T196 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.422611828 May 21 02:38:46 PM PDT 24 May 21 02:54:05 PM PDT 24 413019200 ps
T256 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.254438925 May 21 02:39:23 PM PDT 24 May 21 02:40:07 PM PDT 24 41132400 ps
T1111 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3787529852 May 21 02:38:40 PM PDT 24 May 21 02:39:32 PM PDT 24 21801800 ps
T312 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1743272462 May 21 02:38:54 PM PDT 24 May 21 02:39:45 PM PDT 24 39456000 ps
T257 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3524912926 May 21 02:39:14 PM PDT 24 May 21 02:40:02 PM PDT 24 127715200 ps
T313 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1448844003 May 21 02:38:40 PM PDT 24 May 21 02:39:31 PM PDT 24 15106400 ps
T240 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3148093735 May 21 02:39:00 PM PDT 24 May 21 02:39:53 PM PDT 24 84445400 ps
T309 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.403816574 May 21 02:38:53 PM PDT 24 May 21 02:40:29 PM PDT 24 1302821900 ps
T1112 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1242417917 May 21 02:39:25 PM PDT 24 May 21 02:40:06 PM PDT 24 84433800 ps
T1113 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3053025441 May 21 02:39:19 PM PDT 24 May 21 02:40:00 PM PDT 24 199756200 ps
T265 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1114826860 May 21 02:38:41 PM PDT 24 May 21 02:39:43 PM PDT 24 37761900 ps
T354 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3840638993 May 21 02:38:50 PM PDT 24 May 21 02:40:15 PM PDT 24 2290952500 ps
T353 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2214339777 May 21 02:38:47 PM PDT 24 May 21 02:39:39 PM PDT 24 25460300 ps
T197 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2989574988 May 21 02:41:07 PM PDT 24 May 21 02:47:36 PM PDT 24 192625800 ps
T266 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3556396941 May 21 02:38:42 PM PDT 24 May 21 02:40:04 PM PDT 24 163979500 ps
T315 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2259678084 May 21 02:39:32 PM PDT 24 May 21 02:40:08 PM PDT 24 18808000 ps
T355 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.149975000 May 21 02:38:43 PM PDT 24 May 21 02:39:34 PM PDT 24 410680400 ps
T267 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3454456852 May 21 02:38:54 PM PDT 24 May 21 02:40:02 PM PDT 24 20826000 ps
T1114 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3215478157 May 21 02:38:41 PM PDT 24 May 21 02:39:33 PM PDT 24 19984000 ps
T314 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3110098753 May 21 02:41:07 PM PDT 24 May 21 02:41:35 PM PDT 24 30578600 ps
T241 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3191325831 May 21 02:39:20 PM PDT 24 May 21 02:40:05 PM PDT 24 110784200 ps
T242 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2153412111 May 21 02:38:55 PM PDT 24 May 21 02:39:52 PM PDT 24 239453300 ps
T1115 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2402317398 May 21 02:38:41 PM PDT 24 May 21 02:39:53 PM PDT 24 623808300 ps
T243 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1661555461 May 21 02:41:00 PM PDT 24 May 21 02:41:34 PM PDT 24 201613700 ps
T316 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2489984241 May 21 02:39:13 PM PDT 24 May 21 02:39:58 PM PDT 24 19095500 ps
T244 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2233829442 May 21 02:39:25 PM PDT 24 May 21 02:40:09 PM PDT 24 223044200 ps
T245 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.282530049 May 21 02:39:24 PM PDT 24 May 21 02:40:08 PM PDT 24 95226000 ps
T290 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.435459946 May 21 02:38:52 PM PDT 24 May 21 02:40:43 PM PDT 24 2918044700 ps
T1116 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.814429684 May 21 02:41:04 PM PDT 24 May 21 02:41:37 PM PDT 24 379232300 ps
T1117 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.899863472 May 21 02:39:00 PM PDT 24 May 21 02:40:11 PM PDT 24 82519200 ps
T1118 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2515369552 May 21 02:39:16 PM PDT 24 May 21 02:40:01 PM PDT 24 35209800 ps
T247 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1483926869 May 21 02:38:53 PM PDT 24 May 21 02:39:44 PM PDT 24 17037300 ps
T291 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3014642797 May 21 02:39:27 PM PDT 24 May 21 02:54:40 PM PDT 24 1730479100 ps
T1119 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.444231410 May 21 02:39:34 PM PDT 24 May 21 02:40:09 PM PDT 24 90310700 ps
T1120 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1831929312 May 21 02:39:34 PM PDT 24 May 21 02:40:09 PM PDT 24 18311700 ps
T339 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1450414815 May 21 02:39:34 PM PDT 24 May 21 02:40:09 PM PDT 24 54517800 ps
T1121 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3557327365 May 21 02:39:35 PM PDT 24 May 21 02:40:10 PM PDT 24 20994600 ps
T1122 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2129238614 May 21 02:39:07 PM PDT 24 May 21 02:40:16 PM PDT 24 68534600 ps
T1123 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3216608789 May 21 02:39:02 PM PDT 24 May 21 02:39:53 PM PDT 24 11650100 ps
T263 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2024766220 May 21 02:38:45 PM PDT 24 May 21 02:39:42 PM PDT 24 853781100 ps
T271 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1965292621 May 21 02:39:13 PM PDT 24 May 21 02:40:03 PM PDT 24 33930100 ps
T1124 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3629075889 May 21 02:39:03 PM PDT 24 May 21 02:39:56 PM PDT 24 39103800 ps
T317 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.216909152 May 21 02:39:00 PM PDT 24 May 21 02:39:51 PM PDT 24 17544600 ps
T1125 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.4228193780 May 21 02:41:08 PM PDT 24 May 21 02:41:36 PM PDT 24 17153800 ps
T264 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2819175902 May 21 02:39:02 PM PDT 24 May 21 02:39:57 PM PDT 24 111417100 ps
T1126 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1717936953 May 21 02:38:44 PM PDT 24 May 21 02:39:36 PM PDT 24 19882000 ps
T340 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1763199132 May 21 02:39:36 PM PDT 24 May 21 02:40:11 PM PDT 24 32010800 ps
T1127 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2074576801 May 21 02:39:17 PM PDT 24 May 21 02:40:02 PM PDT 24 88143500 ps
T1128 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3099423555 May 21 02:38:54 PM PDT 24 May 21 02:39:48 PM PDT 24 103738900 ps
T1129 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1257510438 May 21 02:39:23 PM PDT 24 May 21 02:40:03 PM PDT 24 25475900 ps
T292 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.206490410 May 21 02:38:59 PM PDT 24 May 21 02:39:54 PM PDT 24 271786900 ps
T270 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3838255743 May 21 02:41:04 PM PDT 24 May 21 02:41:37 PM PDT 24 180029200 ps
T293 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.107963974 May 21 02:39:15 PM PDT 24 May 21 02:40:04 PM PDT 24 182981000 ps
T1130 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3615403653 May 21 02:38:46 PM PDT 24 May 21 02:39:36 PM PDT 24 15373400 ps
T268 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3653024467 May 21 02:39:22 PM PDT 24 May 21 02:40:07 PM PDT 24 220049000 ps
T1131 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2287729442 May 21 02:38:42 PM PDT 24 May 21 02:39:32 PM PDT 24 23110700 ps
T248 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3280441025 May 21 02:38:52 PM PDT 24 May 21 02:39:43 PM PDT 24 17025300 ps
T269 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3434674523 May 21 02:39:08 PM PDT 24 May 21 02:39:58 PM PDT 24 127646700 ps
T1132 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1501212607 May 21 02:39:06 PM PDT 24 May 21 02:39:57 PM PDT 24 14507600 ps
T1133 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4168224776 May 21 02:38:55 PM PDT 24 May 21 02:40:37 PM PDT 24 16034866200 ps
T1134 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2681535382 May 21 02:39:36 PM PDT 24 May 21 02:40:11 PM PDT 24 16585300 ps
T294 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.761182337 May 21 02:39:18 PM PDT 24 May 21 02:46:06 PM PDT 24 775509400 ps
T295 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4082334858 May 21 02:39:15 PM PDT 24 May 21 02:54:36 PM PDT 24 2301030600 ps
T1135 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2230839019 May 21 02:39:41 PM PDT 24 May 21 02:40:16 PM PDT 24 198547700 ps
T1136 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2444172412 May 21 02:39:02 PM PDT 24 May 21 02:39:54 PM PDT 24 44167200 ps
T1137 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1794211423 May 21 02:39:29 PM PDT 24 May 21 02:40:05 PM PDT 24 14199500 ps
T1138 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.922065841 May 21 02:39:30 PM PDT 24 May 21 02:40:06 PM PDT 24 19947300 ps
T1139 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4266477960 May 21 02:39:19 PM PDT 24 May 21 02:40:04 PM PDT 24 57328200 ps
T1140 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1426967151 May 21 02:39:02 PM PDT 24 May 21 02:39:55 PM PDT 24 116601400 ps
T1141 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.716094295 May 21 02:39:19 PM PDT 24 May 21 02:40:04 PM PDT 24 43496900 ps
T296 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1408237709 May 21 02:39:09 PM PDT 24 May 21 02:39:57 PM PDT 24 586949000 ps
T1142 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1028047511 May 21 02:39:39 PM PDT 24 May 21 02:40:13 PM PDT 24 20609300 ps
T1143 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3524071501 May 21 02:39:18 PM PDT 24 May 21 02:40:02 PM PDT 24 13626300 ps
T341 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1703665745 May 21 02:39:07 PM PDT 24 May 21 02:39:55 PM PDT 24 22005000 ps
T249 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2591549376 May 21 02:38:41 PM PDT 24 May 21 02:39:31 PM PDT 24 33164200 ps
T1144 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3747893115 May 21 02:39:41 PM PDT 24 May 21 02:40:15 PM PDT 24 19913100 ps
T1145 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1038709578 May 21 02:38:41 PM PDT 24 May 21 02:39:52 PM PDT 24 451378400 ps
T1146 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3087843514 May 21 02:39:42 PM PDT 24 May 21 02:40:15 PM PDT 24 19171500 ps
T1147 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3691151515 May 21 02:38:40 PM PDT 24 May 21 02:39:37 PM PDT 24 63937500 ps
T350 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4177503081 May 21 02:39:01 PM PDT 24 May 21 02:47:07 PM PDT 24 694912000 ps
T1148 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3721062697 May 21 02:39:02 PM PDT 24 May 21 02:39:57 PM PDT 24 37039100 ps
T1149 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1609754153 May 21 02:39:24 PM PDT 24 May 21 02:40:07 PM PDT 24 113388900 ps
T1150 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1278955446 May 21 02:39:21 PM PDT 24 May 21 02:40:06 PM PDT 24 361768200 ps
T1151 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2006673117 May 21 02:41:03 PM PDT 24 May 21 02:41:31 PM PDT 24 82958600 ps
T1152 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4140661168 May 21 02:39:09 PM PDT 24 May 21 02:39:56 PM PDT 24 72279400 ps
T1153 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.958952501 May 21 02:38:52 PM PDT 24 May 21 02:39:45 PM PDT 24 62729800 ps
T1154 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3890975665 May 21 02:38:51 PM PDT 24 May 21 02:39:46 PM PDT 24 21534700 ps
T1155 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.115349100 May 21 02:41:07 PM PDT 24 May 21 02:41:35 PM PDT 24 27616500 ps
T1156 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3194874399 May 21 02:39:16 PM PDT 24 May 21 02:40:02 PM PDT 24 19786400 ps
T1157 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3052235699 May 21 02:41:07 PM PDT 24 May 21 02:41:34 PM PDT 24 13340900 ps
T1158 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2474531533 May 21 02:39:06 PM PDT 24 May 21 02:39:54 PM PDT 24 14706300 ps
T1159 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.692128422 May 21 02:39:19 PM PDT 24 May 21 02:40:02 PM PDT 24 19845200 ps
T250 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1881956614 May 21 02:39:02 PM PDT 24 May 21 02:39:52 PM PDT 24 33739500 ps
T1160 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2803324406 May 21 02:39:29 PM PDT 24 May 21 02:40:08 PM PDT 24 12610000 ps
T272 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.621049687 May 21 02:39:26 PM PDT 24 May 21 02:40:07 PM PDT 24 134996400 ps
T1161 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3104274242 May 21 02:39:34 PM PDT 24 May 21 02:40:09 PM PDT 24 32478100 ps
T273 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.663972763 May 21 02:39:08 PM PDT 24 May 21 02:40:00 PM PDT 24 43097500 ps
T1162 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.717066619 May 21 02:39:15 PM PDT 24 May 21 02:40:04 PM PDT 24 50522900 ps
T344 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.480048690 May 21 02:39:42 PM PDT 24 May 21 02:54:53 PM PDT 24 1380313900 ps
T1163 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2183162050 May 21 02:39:22 PM PDT 24 May 21 02:40:02 PM PDT 24 28799900 ps
T297 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3594598064 May 21 02:39:00 PM PDT 24 May 21 02:39:56 PM PDT 24 135090600 ps
T1164 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2722649891 May 21 02:39:40 PM PDT 24 May 21 02:40:13 PM PDT 24 58922000 ps
T1165 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1684333450 May 21 02:39:06 PM PDT 24 May 21 02:39:56 PM PDT 24 39107300 ps
T1166 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3412381832 May 21 02:39:31 PM PDT 24 May 21 02:40:07 PM PDT 24 28171000 ps
T1167 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2417135477 May 21 02:39:02 PM PDT 24 May 21 02:52:03 PM PDT 24 889650400 ps
T1168 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2905731129 May 21 02:39:16 PM PDT 24 May 21 02:39:59 PM PDT 24 50555700 ps
T1169 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1618855997 May 21 02:38:54 PM PDT 24 May 21 02:39:48 PM PDT 24 35630800 ps
T1170 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.974061256 May 21 02:39:19 PM PDT 24 May 21 02:47:22 PM PDT 24 2608857400 ps
T1171 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.75679533 May 21 02:38:46 PM PDT 24 May 21 02:39:42 PM PDT 24 43725900 ps
T1172 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2303050930 May 21 02:41:45 PM PDT 24 May 21 02:42:07 PM PDT 24 80431600 ps
T1173 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4074276807 May 21 02:38:46 PM PDT 24 May 21 02:39:58 PM PDT 24 3555321700 ps
T1174 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1668965261 May 21 02:39:14 PM PDT 24 May 21 02:39:58 PM PDT 24 17480500 ps
T347 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2593465926 May 21 02:39:26 PM PDT 24 May 21 02:52:19 PM PDT 24 1416407000 ps
T1175 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2788594259 May 21 02:39:43 PM PDT 24 May 21 02:40:16 PM PDT 24 30037500 ps
T1176 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3841753368 May 21 02:39:26 PM PDT 24 May 21 02:40:05 PM PDT 24 38541100 ps
T1177 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.393311095 May 21 02:39:18 PM PDT 24 May 21 02:40:02 PM PDT 24 24616600 ps
T298 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4142449069 May 21 02:38:59 PM PDT 24 May 21 02:40:19 PM PDT 24 850946900 ps
T1178 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3960220827 May 21 02:39:17 PM PDT 24 May 21 02:40:05 PM PDT 24 62659200 ps
T1179 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4236274821 May 21 02:39:02 PM PDT 24 May 21 02:39:51 PM PDT 24 94291700 ps
T345 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2267625602 May 21 02:38:40 PM PDT 24 May 21 02:54:18 PM PDT 24 738643400 ps
T299 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3546883231 May 21 02:41:01 PM PDT 24 May 21 02:41:31 PM PDT 24 136944900 ps
T1180 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3606065863 May 21 02:39:34 PM PDT 24 May 21 02:40:10 PM PDT 24 31690500 ps
T1181 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2189980974 May 21 02:39:35 PM PDT 24 May 21 02:40:10 PM PDT 24 21789100 ps
T1182 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.66240539 May 21 02:39:43 PM PDT 24 May 21 02:40:16 PM PDT 24 26965000 ps
T1183 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3381711441 May 21 02:39:02 PM PDT 24 May 21 02:39:52 PM PDT 24 57785000 ps
T1184 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2149388926 May 21 02:39:25 PM PDT 24 May 21 02:40:04 PM PDT 24 38138800 ps
T1185 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2955154209 May 21 02:38:41 PM PDT 24 May 21 02:39:33 PM PDT 24 145622200 ps
T1186 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1307166456 May 21 02:38:41 PM PDT 24 May 21 02:39:33 PM PDT 24 32499000 ps
T1187 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4010493262 May 21 02:39:29 PM PDT 24 May 21 02:40:21 PM PDT 24 985833300 ps
T342 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2859215294 May 21 02:38:40 PM PDT 24 May 21 02:46:47 PM PDT 24 1734652600 ps
T1188 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1847323544 May 21 02:38:34 PM PDT 24 May 21 02:39:21 PM PDT 24 133408900 ps
T1189 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.264267391 May 21 02:39:29 PM PDT 24 May 21 02:40:07 PM PDT 24 23916000 ps
T1190 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2492429820 May 21 02:39:42 PM PDT 24 May 21 02:40:18 PM PDT 24 135164300 ps
T1191 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.115245443 May 21 02:38:54 PM PDT 24 May 21 02:39:45 PM PDT 24 207372100 ps
T1192 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.686211822 May 21 02:39:18 PM PDT 24 May 21 02:40:00 PM PDT 24 55814300 ps
T300 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4064620324 May 21 02:39:09 PM PDT 24 May 21 02:40:01 PM PDT 24 117777300 ps
T1193 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3631071391 May 21 02:39:23 PM PDT 24 May 21 02:40:03 PM PDT 24 58102400 ps
T1194 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1888051141 May 21 02:39:08 PM PDT 24 May 21 02:40:00 PM PDT 24 173320500 ps
T1195 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1355558178 May 21 02:39:07 PM PDT 24 May 21 02:40:09 PM PDT 24 117267800 ps
T1196 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2369107530 May 21 02:39:36 PM PDT 24 May 21 02:40:10 PM PDT 24 31719800 ps
T1197 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3776206670 May 21 02:38:50 PM PDT 24 May 21 02:39:44 PM PDT 24 60402200 ps
T251 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2388946612 May 21 02:38:41 PM PDT 24 May 21 02:39:31 PM PDT 24 27740500 ps
T351 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4254940317 May 21 02:39:14 PM PDT 24 May 21 02:47:17 PM PDT 24 1336246600 ps
T1198 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.431737338 May 21 02:39:01 PM PDT 24 May 21 02:39:53 PM PDT 24 14928600 ps
T1199 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1380929951 May 21 02:38:53 PM PDT 24 May 21 02:46:58 PM PDT 24 395341900 ps
T1200 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2915825848 May 21 02:39:17 PM PDT 24 May 21 02:40:05 PM PDT 24 56437200 ps
T301 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2011199291 May 21 02:39:30 PM PDT 24 May 21 02:40:14 PM PDT 24 204675900 ps
T1201 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3873876247 May 21 02:39:36 PM PDT 24 May 21 02:40:10 PM PDT 24 16737800 ps
T1202 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.200198116 May 21 02:38:52 PM PDT 24 May 21 02:39:43 PM PDT 24 25891000 ps
T1203 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3159549837 May 21 02:39:24 PM PDT 24 May 21 02:40:04 PM PDT 24 16935800 ps
T1204 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.629053733 May 21 02:38:46 PM PDT 24 May 21 02:39:54 PM PDT 24 64217400 ps
T302 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.558445902 May 21 02:38:53 PM PDT 24 May 21 02:39:50 PM PDT 24 108970800 ps
T1205 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1546613677 May 21 02:39:15 PM PDT 24 May 21 02:39:58 PM PDT 24 130456100 ps
T1206 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.962051560 May 21 02:38:51 PM PDT 24 May 21 02:39:46 PM PDT 24 44561800 ps
T1207 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2947181743 May 21 02:39:35 PM PDT 24 May 21 02:40:10 PM PDT 24 25771900 ps
T1208 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2289102664 May 21 02:38:41 PM PDT 24 May 21 02:40:03 PM PDT 24 2862351800 ps
T1209 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.949483541 May 21 02:41:06 PM PDT 24 May 21 02:41:34 PM PDT 24 45056000 ps
T1210 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1370712008 May 21 02:39:26 PM PDT 24 May 21 02:40:12 PM PDT 24 56863400 ps
T1211 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.864709099 May 21 02:38:53 PM PDT 24 May 21 02:39:50 PM PDT 24 62044100 ps
T1212 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3673024555 May 21 02:39:18 PM PDT 24 May 21 02:40:00 PM PDT 24 41755900 ps
T1213 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2933143857 May 21 02:39:42 PM PDT 24 May 21 02:40:19 PM PDT 24 74101600 ps
T1214 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2491229277 May 21 02:38:47 PM PDT 24 May 21 02:39:53 PM PDT 24 130017700 ps
T1215 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.524193306 May 21 02:39:16 PM PDT 24 May 21 02:40:20 PM PDT 24 121083900 ps
T1216 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2297819228 May 21 02:39:02 PM PDT 24 May 21 02:39:52 PM PDT 24 15443100 ps
T1217 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1571350353 May 21 02:39:31 PM PDT 24 May 21 02:40:09 PM PDT 24 46810000 ps
T1218 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.537138362 May 21 02:39:37 PM PDT 24 May 21 02:40:15 PM PDT 24 67193300 ps
T1219 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1656959952 May 21 02:39:41 PM PDT 24 May 21 02:40:14 PM PDT 24 29851300 ps
T343 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.570038867 May 21 02:38:58 PM PDT 24 May 21 02:47:08 PM PDT 24 1374016200 ps
T1220 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.422978441 May 21 02:39:36 PM PDT 24 May 21 02:40:10 PM PDT 24 27743800 ps
T1221 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1111758015 May 21 02:39:14 PM PDT 24 May 21 02:40:02 PM PDT 24 209707700 ps
T346 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1715616013 May 21 02:39:06 PM PDT 24 May 21 02:54:58 PM PDT 24 6074972400 ps
T1222 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2192034519 May 21 02:39:02 PM PDT 24 May 21 02:40:09 PM PDT 24 50719700 ps
T349 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2489279532 May 21 02:39:17 PM PDT 24 May 21 02:54:37 PM PDT 24 369165800 ps
T1223 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.520295520 May 21 02:41:02 PM PDT 24 May 21 02:41:31 PM PDT 24 70315600 ps
T1224 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2034404555 May 21 02:39:41 PM PDT 24 May 21 02:40:14 PM PDT 24 136774400 ps
T1225 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.749228399 May 21 02:39:00 PM PDT 24 May 21 02:39:53 PM PDT 24 23423700 ps
T1226 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.950586533 May 21 02:41:09 PM PDT 24 May 21 02:41:39 PM PDT 24 122352900 ps
T1227 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2728689385 May 21 02:39:08 PM PDT 24 May 21 02:54:23 PM PDT 24 1290453600 ps
T1228 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4110973432 May 21 02:39:18 PM PDT 24 May 21 02:40:02 PM PDT 24 102085500 ps
T1229 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1557462584 May 21 02:39:09 PM PDT 24 May 21 02:39:58 PM PDT 24 22692300 ps
T303 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3493271999 May 21 02:38:53 PM PDT 24 May 21 02:40:07 PM PDT 24 851240800 ps
T1230 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1503346116 May 21 02:39:18 PM PDT 24 May 21 02:40:03 PM PDT 24 13130100 ps
T1231 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2799050069 May 21 02:39:22 PM PDT 24 May 21 02:40:04 PM PDT 24 20728100 ps
T1232 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2474464039 May 21 02:38:42 PM PDT 24 May 21 02:39:35 PM PDT 24 46973700 ps
T1233 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3064361079 May 21 02:39:14 PM PDT 24 May 21 02:39:59 PM PDT 24 203564600 ps
T1234 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1604593385 May 21 02:39:30 PM PDT 24 May 21 02:40:11 PM PDT 24 47902000 ps
T348 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1636069014 May 21 02:39:02 PM PDT 24 May 21 02:47:08 PM PDT 24 379871300 ps
T1235 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1649415438 May 21 02:39:31 PM PDT 24 May 21 02:40:07 PM PDT 24 30870700 ps
T1236 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4118492348 May 21 02:39:01 PM PDT 24 May 21 02:39:51 PM PDT 24 190233500 ps
T1237 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2244718383 May 21 02:39:36 PM PDT 24 May 21 02:40:11 PM PDT 24 16000600 ps
T1238 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.337480403 May 21 02:39:29 PM PDT 24 May 21 02:40:09 PM PDT 24 111513000 ps
T1239 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1906680426 May 21 02:39:16 PM PDT 24 May 21 02:40:04 PM PDT 24 141381100 ps
T1240 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.677699169 May 21 02:39:33 PM PDT 24 May 21 02:40:28 PM PDT 24 221269800 ps
T1241 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.416534215 May 21 02:38:53 PM PDT 24 May 21 02:39:48 PM PDT 24 169088800 ps
T1242 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3836475991 May 21 02:39:19 PM PDT 24 May 21 02:40:02 PM PDT 24 23564400 ps
T1243 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2911191734 May 21 02:39:21 PM PDT 24 May 21 02:40:04 PM PDT 24 35656000 ps
T1244 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.443287186 May 21 02:39:01 PM PDT 24 May 21 02:39:53 PM PDT 24 25108600 ps
T1245 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.34985822 May 21 02:41:04 PM PDT 24 May 21 02:41:39 PM PDT 24 291572100 ps
T1246 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.458488152 May 21 02:38:41 PM PDT 24 May 21 02:39:31 PM PDT 24 52769100 ps

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1060844546
Short name T18
Test name
Test status
Simulation time 255012400 ps
CPU time 1037.75 seconds
Started May 21 03:14:04 PM PDT 24
Finished May 21 03:31:23 PM PDT 24
Peak memory 283224 kb
Host smart-d903de62-764b-4969-b557-e445a1f84c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060844546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1060844546
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.422611828
Short name T196
Test name
Test status
Simulation time 413019200 ps
CPU time 882.42 seconds
Started May 21 02:38:46 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 264200 kb
Host smart-7d47fdd3-2304-47d5-9659-57ed3ef99912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422611828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.422611828
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.4211585557
Short name T10
Test name
Test status
Simulation time 79410600 ps
CPU time 133.97 seconds
Started May 21 03:25:59 PM PDT 24
Finished May 21 03:28:14 PM PDT 24
Peak memory 264812 kb
Host smart-dc20d68b-fb79-43f1-a531-e9fec3e356fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211585557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.4211585557
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2880526782
Short name T36
Test name
Test status
Simulation time 670172600 ps
CPU time 101.63 seconds
Started May 21 03:17:03 PM PDT 24
Finished May 21 03:18:46 PM PDT 24
Peak memory 272608 kb
Host smart-2b69d50c-55c3-4b6a-8989-118181e2f3f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880526782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2880526782
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1816742287
Short name T66
Test name
Test status
Simulation time 247331869500 ps
CPU time 2735.3 seconds
Started May 21 03:15:39 PM PDT 24
Finished May 21 04:01:16 PM PDT 24
Peak memory 265264 kb
Host smart-6bbf420b-c310-4a84-b6d7-98e07ac7e13f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816742287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1816742287
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.396698111
Short name T19
Test name
Test status
Simulation time 8396100700 ps
CPU time 72.21 seconds
Started May 21 03:17:40 PM PDT 24
Finished May 21 03:18:53 PM PDT 24
Peak memory 260564 kb
Host smart-87132135-7ad2-44e1-9457-f1f25e326684
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396698111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.396698111
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.812050084
Short name T54
Test name
Test status
Simulation time 2587402400 ps
CPU time 4927.78 seconds
Started May 21 03:15:07 PM PDT 24
Finished May 21 04:37:16 PM PDT 24
Peak memory 287652 kb
Host smart-1f191926-8cda-40aa-9f2b-a2d923695db6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812050084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.812050084
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3191325831
Short name T241
Test name
Test status
Simulation time 110784200 ps
CPU time 17.11 seconds
Started May 21 02:39:20 PM PDT 24
Finished May 21 02:40:05 PM PDT 24
Peak memory 272396 kb
Host smart-8f81fb78-0a10-4423-8594-b7356aed72f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191325831 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3191325831
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.1431252280
Short name T98
Test name
Test status
Simulation time 20923659900 ps
CPU time 240.2 seconds
Started May 21 03:13:50 PM PDT 24
Finished May 21 03:17:50 PM PDT 24
Peak memory 274616 kb
Host smart-a8339287-301d-4201-956d-38547cd0b448
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431252280 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.1431252280
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3946005924
Short name T21
Test name
Test status
Simulation time 708924300 ps
CPU time 135.5 seconds
Started May 21 03:20:42 PM PDT 24
Finished May 21 03:22:58 PM PDT 24
Peak memory 292956 kb
Host smart-345e8ed8-a69c-4735-9029-98de5ca37b49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946005924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3946005924
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.411630401
Short name T117
Test name
Test status
Simulation time 951962400 ps
CPU time 69.05 seconds
Started May 21 03:15:51 PM PDT 24
Finished May 21 03:17:01 PM PDT 24
Peak memory 259724 kb
Host smart-1e8850a0-dc36-4b66-9353-437582f05330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411630401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.411630401
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.4243455501
Short name T49
Test name
Test status
Simulation time 23984110800 ps
CPU time 703.83 seconds
Started May 21 03:16:15 PM PDT 24
Finished May 21 03:27:59 PM PDT 24
Peak memory 334208 kb
Host smart-fb322c6f-197d-4e3b-89a1-b91c5769931b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243455501 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.4243455501
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3790306239
Short name T120
Test name
Test status
Simulation time 18619037500 ps
CPU time 678.44 seconds
Started May 21 03:12:01 PM PDT 24
Finished May 21 03:23:20 PM PDT 24
Peak memory 263172 kb
Host smart-e403e382-dbef-486c-9336-4b970aa2d48e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790306239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3790306239
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1507398948
Short name T43
Test name
Test status
Simulation time 4072873400 ps
CPU time 141.42 seconds
Started May 21 03:20:12 PM PDT 24
Finished May 21 03:22:34 PM PDT 24
Peak memory 262668 kb
Host smart-5d622792-886b-4f6f-8618-a3602653e4b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507398948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1507398948
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.3418431475
Short name T149
Test name
Test status
Simulation time 43183500 ps
CPU time 112.66 seconds
Started May 21 03:23:32 PM PDT 24
Finished May 21 03:25:26 PM PDT 24
Peak memory 263876 kb
Host smart-7fd045b5-8a92-43bc-a262-5cedf7c4524c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418431475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.3418431475
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.3770863431
Short name T13
Test name
Test status
Simulation time 15245700 ps
CPU time 13.9 seconds
Started May 21 03:15:40 PM PDT 24
Finished May 21 03:15:55 PM PDT 24
Peak memory 265404 kb
Host smart-01e638d6-242e-4df9-92a7-f74e8877d63a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770863431 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3770863431
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2489984241
Short name T316
Test name
Test status
Simulation time 19095500 ps
CPU time 13.17 seconds
Started May 21 02:39:13 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 262516 kb
Host smart-8dcad9b7-1565-47c5-90f3-6a23e72732e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489984241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2489984241
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2729080873
Short name T12
Test name
Test status
Simulation time 200376100 ps
CPU time 131.74 seconds
Started May 21 03:24:54 PM PDT 24
Finished May 21 03:27:07 PM PDT 24
Peak memory 260960 kb
Host smart-93272ab6-24e2-4429-b620-54df81780922
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729080873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2729080873
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1329634095
Short name T116
Test name
Test status
Simulation time 10015902500 ps
CPU time 117.65 seconds
Started May 21 03:21:57 PM PDT 24
Finished May 21 03:23:56 PM PDT 24
Peak memory 350812 kb
Host smart-ac5a0bfd-6344-4bbe-aeed-165d9b7e85c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329634095 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1329634095
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2153412111
Short name T242
Test name
Test status
Simulation time 239453300 ps
CPU time 19.14 seconds
Started May 21 02:38:55 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 264232 kb
Host smart-6aa33353-a518-4f35-8b32-992ad7fa1642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153412111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2
153412111
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.596457480
Short name T173
Test name
Test status
Simulation time 39818982600 ps
CPU time 77.95 seconds
Started May 21 03:22:53 PM PDT 24
Finished May 21 03:24:13 PM PDT 24
Peak memory 262972 kb
Host smart-ee82589e-0154-491e-85e4-fd5a872c8cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596457480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.596457480
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3390257614
Short name T186
Test name
Test status
Simulation time 92299200 ps
CPU time 13.77 seconds
Started May 21 03:24:36 PM PDT 24
Finished May 21 03:24:52 PM PDT 24
Peak memory 265208 kb
Host smart-ac6c9514-9515-442f-a676-f132b1a652ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390257614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3390257614
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.3005409383
Short name T163
Test name
Test status
Simulation time 10222300 ps
CPU time 21.06 seconds
Started May 21 03:22:07 PM PDT 24
Finished May 21 03:22:30 PM PDT 24
Peak memory 265292 kb
Host smart-25cb9ea4-a61c-4af3-8855-7bb1ebe1c9e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005409383 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.3005409383
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3690400627
Short name T134
Test name
Test status
Simulation time 40404500 ps
CPU time 130.97 seconds
Started May 21 03:26:56 PM PDT 24
Finished May 21 03:29:09 PM PDT 24
Peak memory 261124 kb
Host smart-0658a88f-5fcd-412b-a7f8-ca75068c03b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690400627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3690400627
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.806127271
Short name T155
Test name
Test status
Simulation time 1514026045700 ps
CPU time 2073.97 seconds
Started May 21 03:13:30 PM PDT 24
Finished May 21 03:48:04 PM PDT 24
Peak memory 265276 kb
Host smart-edd12349-3c81-4ae4-b159-f40515fc6f87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806127271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_host_ctrl_arb.806127271
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2074969754
Short name T50
Test name
Test status
Simulation time 973588700 ps
CPU time 27.29 seconds
Started May 21 03:16:40 PM PDT 24
Finished May 21 03:17:08 PM PDT 24
Peak memory 265400 kb
Host smart-0ec10585-c946-404e-aeca-fe9cdb4bc2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074969754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2074969754
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.173056193
Short name T933
Test name
Test status
Simulation time 37447600 ps
CPU time 109.84 seconds
Started May 21 03:24:37 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 259944 kb
Host smart-88187f6e-6f09-47b3-aeec-5afbe38a7a63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173056193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.173056193
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2656224388
Short name T160
Test name
Test status
Simulation time 157537920000 ps
CPU time 1029.93 seconds
Started May 21 03:13:01 PM PDT 24
Finished May 21 03:30:12 PM PDT 24
Peak memory 259352 kb
Host smart-57b61ac5-e341-49df-b6ed-504fa6d90e7a
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656224388 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2656224388
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2018827495
Short name T20
Test name
Test status
Simulation time 8908153200 ps
CPU time 222.97 seconds
Started May 21 03:20:48 PM PDT 24
Finished May 21 03:24:32 PM PDT 24
Peak memory 284412 kb
Host smart-8a656106-c475-4351-8d47-1da087e72e17
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018827495 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2018827495
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3972153377
Short name T115
Test name
Test status
Simulation time 10013589400 ps
CPU time 305.9 seconds
Started May 21 03:16:25 PM PDT 24
Finished May 21 03:21:32 PM PDT 24
Peak memory 321580 kb
Host smart-81b6c564-935b-48a8-a1c7-ae1f43618df4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972153377 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3972153377
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.3912814713
Short name T190
Test name
Test status
Simulation time 4482412300 ps
CPU time 723.92 seconds
Started May 21 03:18:28 PM PDT 24
Finished May 21 03:30:34 PM PDT 24
Peak memory 335216 kb
Host smart-b7b3a576-b27f-4cc0-b663-19e5d03df649
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912814713 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.3912814713
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.522229106
Short name T5
Test name
Test status
Simulation time 705074300 ps
CPU time 173.43 seconds
Started May 21 03:24:31 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 293044 kb
Host smart-bf5300fa-f9f1-4d76-9c28-e5409a7eaa39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522229106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.522229106
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1271405738
Short name T511
Test name
Test status
Simulation time 64989000 ps
CPU time 14.23 seconds
Started May 21 03:23:00 PM PDT 24
Finished May 21 03:23:17 PM PDT 24
Peak memory 265132 kb
Host smart-f37a66c9-8bfd-4da2-810a-38d1031a8001
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271405738 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1271405738
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1239040755
Short name T212
Test name
Test status
Simulation time 74023400 ps
CPU time 37.91 seconds
Started May 21 03:17:51 PM PDT 24
Finished May 21 03:18:30 PM PDT 24
Peak memory 267492 kb
Host smart-8a582ba4-7df5-4618-89bf-c3c80d22f6e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239040755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1239040755
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2158973463
Short name T224
Test name
Test status
Simulation time 59255400 ps
CPU time 19.02 seconds
Started May 21 02:39:26 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 264188 kb
Host smart-18d1c893-0a13-4867-b515-ed0e2617297f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158973463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2158973463
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2591549376
Short name T249
Test name
Test status
Simulation time 33164200 ps
CPU time 13.62 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:31 PM PDT 24
Peak memory 264100 kb
Host smart-b475396c-baed-4787-a45b-09a280d0ee26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591549376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2591549376
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.4103640089
Short name T94
Test name
Test status
Simulation time 694188800 ps
CPU time 45.89 seconds
Started May 21 03:14:02 PM PDT 24
Finished May 21 03:14:50 PM PDT 24
Peak memory 262036 kb
Host smart-404b4dc7-46af-41d4-87bd-c1a926e08e4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103640089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.4103640089
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.78966043
Short name T68
Test name
Test status
Simulation time 717325100 ps
CPU time 17.82 seconds
Started May 21 03:17:19 PM PDT 24
Finished May 21 03:17:38 PM PDT 24
Peak memory 262496 kb
Host smart-e457b2fb-7328-46ea-a3e3-871cd8f8a356
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78966043 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.78966043
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2862791782
Short name T95
Test name
Test status
Simulation time 3768698500 ps
CPU time 567.63 seconds
Started May 21 03:23:13 PM PDT 24
Finished May 21 03:32:43 PM PDT 24
Peak memory 313812 kb
Host smart-35be00d9-a559-4fca-a4e8-fbac17815485
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862791782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.2862791782
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.2645806094
Short name T146
Test name
Test status
Simulation time 82849700 ps
CPU time 135.06 seconds
Started May 21 03:13:42 PM PDT 24
Finished May 21 03:15:58 PM PDT 24
Peak memory 261348 kb
Host smart-a0132b0b-680c-4c95-92b8-4c34ee9cdab5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645806094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.2645806094
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2974534797
Short name T177
Test name
Test status
Simulation time 2404534100 ps
CPU time 830.81 seconds
Started May 21 03:18:13 PM PDT 24
Finished May 21 03:32:04 PM PDT 24
Peak memory 273312 kb
Host smart-08a0ea81-9968-4c52-952a-585bf91378ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974534797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2974534797
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3690649557
Short name T9
Test name
Test status
Simulation time 189153100 ps
CPU time 16.08 seconds
Started May 21 03:12:53 PM PDT 24
Finished May 21 03:13:10 PM PDT 24
Peak memory 265208 kb
Host smart-0eaf2f48-67e0-482b-9a0a-78680940e399
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690649557 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3690649557
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3342307079
Short name T81
Test name
Test status
Simulation time 21001560500 ps
CPU time 717.19 seconds
Started May 21 03:18:20 PM PDT 24
Finished May 21 03:30:20 PM PDT 24
Peak memory 273928 kb
Host smart-8c5cd17f-812c-4366-87dd-0507167ee8c3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342307079 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3342307079
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.559124458
Short name T56
Test name
Test status
Simulation time 17643600 ps
CPU time 14.16 seconds
Started May 21 03:17:30 PM PDT 24
Finished May 21 03:17:45 PM PDT 24
Peak memory 278416 kb
Host smart-8208da2d-5ba5-4bb9-b32d-010266828928
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=559124458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.559124458
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.230390360
Short name T260
Test name
Test status
Simulation time 32657600 ps
CPU time 13.31 seconds
Started May 21 02:38:42 PM PDT 24
Finished May 21 02:39:33 PM PDT 24
Peak memory 262532 kb
Host smart-9a6cd902-71da-4985-8888-4f316df967e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230390360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.230390360
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.2620527298
Short name T213
Test name
Test status
Simulation time 4444777900 ps
CPU time 518.09 seconds
Started May 21 03:14:48 PM PDT 24
Finished May 21 03:23:27 PM PDT 24
Peak memory 309576 kb
Host smart-d145817f-1e91-43d2-bb21-0e26f1433f65
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620527298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.2620527298
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.189135221
Short name T325
Test name
Test status
Simulation time 581738000 ps
CPU time 32.09 seconds
Started May 21 03:20:11 PM PDT 24
Finished May 21 03:20:44 PM PDT 24
Peak memory 273576 kb
Host smart-1ab156a5-6d58-4f8c-ae7e-e2b095b304fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189135221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.189135221
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1715616013
Short name T346
Test name
Test status
Simulation time 6074972400 ps
CPU time 916.68 seconds
Started May 21 02:39:06 PM PDT 24
Finished May 21 02:54:58 PM PDT 24
Peak memory 262020 kb
Host smart-35318b0e-a156-46e6-bc5b-4254578ea9bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715616013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1715616013
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.579203703
Short name T17
Test name
Test status
Simulation time 3047945800 ps
CPU time 994.07 seconds
Started May 21 03:20:13 PM PDT 24
Finished May 21 03:36:47 PM PDT 24
Peak memory 286036 kb
Host smart-e50d8873-d604-4090-b7b6-349a4a1a4952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579203703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.579203703
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.778474460
Short name T218
Test name
Test status
Simulation time 75514800 ps
CPU time 32.1 seconds
Started May 21 03:17:57 PM PDT 24
Finished May 21 03:18:30 PM PDT 24
Peak memory 275628 kb
Host smart-ceba0cfb-b987-4f80-b6e2-943810eb19bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778474460 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.778474460
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4082334858
Short name T295
Test name
Test status
Simulation time 2301030600 ps
CPU time 891.1 seconds
Started May 21 02:39:15 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 264168 kb
Host smart-a05e302f-1a6d-4ba7-add5-026b601c2f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082334858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.4082334858
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2593465926
Short name T347
Test name
Test status
Simulation time 1416407000 ps
CPU time 748.3 seconds
Started May 21 02:39:26 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 264200 kb
Host smart-ccd80cd9-0a3a-490c-9a3b-8cf12eba0a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593465926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.2593465926
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3252684851
Short name T686
Test name
Test status
Simulation time 15115500 ps
CPU time 13.7 seconds
Started May 21 03:20:32 PM PDT 24
Finished May 21 03:20:47 PM PDT 24
Peak memory 265148 kb
Host smart-1a6207a8-c209-46de-9e76-73abb64d6554
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252684851 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3252684851
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2624456379
Short name T847
Test name
Test status
Simulation time 8928374500 ps
CPU time 697.35 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:33:48 PM PDT 24
Peak memory 313740 kb
Host smart-6c04c9bc-d583-4ed7-8cce-b9e5f4b2842a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624456379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.2624456379
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3472692539
Short name T192
Test name
Test status
Simulation time 34386700 ps
CPU time 13.3 seconds
Started May 21 03:23:17 PM PDT 24
Finished May 21 03:23:32 PM PDT 24
Peak memory 275672 kb
Host smart-53ed319a-6b32-46e5-a832-6ba3d9e6cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472692539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3472692539
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1025756393
Short name T176
Test name
Test status
Simulation time 503105800 ps
CPU time 2966.11 seconds
Started May 21 03:12:07 PM PDT 24
Finished May 21 04:01:34 PM PDT 24
Peak memory 265160 kb
Host smart-a4cc6ff3-96ec-4b7d-b9a4-953147742c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025756393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1025756393
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2024766220
Short name T263
Test name
Test status
Simulation time 853781100 ps
CPU time 20.07 seconds
Started May 21 02:38:45 PM PDT 24
Finished May 21 02:39:42 PM PDT 24
Peak memory 264200 kb
Host smart-af7228e4-648a-4e66-8959-8ef1fb88b842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024766220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
024766220
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3283545878
Short name T70
Test name
Test status
Simulation time 835950700 ps
CPU time 24.77 seconds
Started May 21 03:14:03 PM PDT 24
Finished May 21 03:14:30 PM PDT 24
Peak memory 265392 kb
Host smart-578cf0e6-d7e7-4ba4-b2d1-5d121ce850f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283545878 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3283545878
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2013392847
Short name T127
Test name
Test status
Simulation time 17072200 ps
CPU time 14.21 seconds
Started May 21 03:12:59 PM PDT 24
Finished May 21 03:13:14 PM PDT 24
Peak memory 265416 kb
Host smart-39b6659d-cdff-45d6-b4ec-20bf231cea74
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013392847 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2013392847
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.1280776258
Short name T23
Test name
Test status
Simulation time 33746600 ps
CPU time 13.5 seconds
Started May 21 03:14:21 PM PDT 24
Finished May 21 03:14:36 PM PDT 24
Peak memory 265292 kb
Host smart-579540c1-828c-4981-8999-95453f8a441f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280776258 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1280776258
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3253485108
Short name T287
Test name
Test status
Simulation time 15322100 ps
CPU time 14.41 seconds
Started May 21 03:13:00 PM PDT 24
Finished May 21 03:13:15 PM PDT 24
Peak memory 265188 kb
Host smart-ee3d8a79-9657-4777-9364-fe6485ebe11c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253485108 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3253485108
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.2198607545
Short name T557
Test name
Test status
Simulation time 25967400 ps
CPU time 13.42 seconds
Started May 21 03:13:00 PM PDT 24
Finished May 21 03:13:14 PM PDT 24
Peak memory 265392 kb
Host smart-318eebe8-eb50-44fd-8546-9215595c0146
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198607545 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2198607545
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.28811373
Short name T147
Test name
Test status
Simulation time 10025751200 ps
CPU time 50.9 seconds
Started May 21 03:14:14 PM PDT 24
Finished May 21 03:15:07 PM PDT 24
Peak memory 265452 kb
Host smart-d9964992-3b1a-4370-a1b9-6dbb686b2510
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811373 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.28811373
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.4252260456
Short name T387
Test name
Test status
Simulation time 384816000 ps
CPU time 52.03 seconds
Started May 21 03:20:55 PM PDT 24
Finished May 21 03:21:48 PM PDT 24
Peak memory 264072 kb
Host smart-16daba3e-d4a4-41bf-a333-41aa42474a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252260456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.4252260456
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2178903263
Short name T390
Test name
Test status
Simulation time 1081257800 ps
CPU time 64.73 seconds
Started May 21 03:21:17 PM PDT 24
Finished May 21 03:22:22 PM PDT 24
Peak memory 263312 kb
Host smart-d25d4abe-9d24-46b9-a385-b521362a205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178903263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2178903263
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.1627052032
Short name T370
Test name
Test status
Simulation time 7932953900 ps
CPU time 65.4 seconds
Started May 21 03:24:41 PM PDT 24
Finished May 21 03:25:48 PM PDT 24
Peak memory 263040 kb
Host smart-8e6170c5-dae6-4311-b1a3-1e2330acea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627052032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1627052032
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1694056668
Short name T368
Test name
Test status
Simulation time 1197960600 ps
CPU time 62.06 seconds
Started May 21 03:26:08 PM PDT 24
Finished May 21 03:27:13 PM PDT 24
Peak memory 263028 kb
Host smart-3f836033-a23b-4412-a0fc-c8eedb277046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694056668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1694056668
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1031262494
Short name T184
Test name
Test status
Simulation time 22413543900 ps
CPU time 210.95 seconds
Started May 21 03:24:03 PM PDT 24
Finished May 21 03:27:36 PM PDT 24
Peak memory 292028 kb
Host smart-fe7f3851-923f-450d-a3b7-1a23d3c86246
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031262494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1031262494
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.292644863
Short name T203
Test name
Test status
Simulation time 576629900 ps
CPU time 147.31 seconds
Started May 21 03:19:50 PM PDT 24
Finished May 21 03:22:19 PM PDT 24
Peak memory 281716 kb
Host smart-7b4e5f9d-1b91-43d3-b0ce-7b427cefe934
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
292644863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.292644863
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2010835411
Short name T365
Test name
Test status
Simulation time 17898800 ps
CPU time 22.59 seconds
Started May 21 03:12:43 PM PDT 24
Finished May 21 03:13:06 PM PDT 24
Peak memory 265340 kb
Host smart-c933855f-2275-4e7c-9f30-8e0cd0de2f5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010835411 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2010835411
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3189625963
Short name T71
Test name
Test status
Simulation time 789154800 ps
CPU time 15.76 seconds
Started May 21 03:13:03 PM PDT 24
Finished May 21 03:13:20 PM PDT 24
Peak memory 265420 kb
Host smart-4e6da791-294d-454f-abf3-19ef3ff4225c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189625963 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3189625963
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.1090914319
Short name T14
Test name
Test status
Simulation time 3125101200 ps
CPU time 4888 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 04:35:27 PM PDT 24
Peak memory 288292 kb
Host smart-916de867-9679-41a2-afec-224dc1db0306
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090914319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1090914319
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3993620774
Short name T363
Test name
Test status
Simulation time 12715600 ps
CPU time 22.34 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:14:21 PM PDT 24
Peak memory 265404 kb
Host smart-b1bdc4e0-be59-4fab-9eda-067aa484d2b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993620774 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3993620774
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3830808442
Short name T67
Test name
Test status
Simulation time 376919436400 ps
CPU time 2331.91 seconds
Started May 21 03:12:01 PM PDT 24
Finished May 21 03:50:54 PM PDT 24
Peak memory 264176 kb
Host smart-0d5a39a4-b2c2-4e77-873c-71e79b84c5c3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830808442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3830808442
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2267625602
Short name T345
Test name
Test status
Simulation time 738643400 ps
CPU time 900.89 seconds
Started May 21 02:38:40 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 261800 kb
Host smart-65306adb-0f1e-4676-98ea-af21c30b36b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267625602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2267625602
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.761182337
Short name T294
Test name
Test status
Simulation time 775509400 ps
CPU time 380.01 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:46:06 PM PDT 24
Peak memory 264216 kb
Host smart-eba3b577-0214-49ce-9280-f46c254f1ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761182337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.761182337
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1257510438
Short name T1129
Test name
Test status
Simulation time 25475900 ps
CPU time 13.26 seconds
Started May 21 02:39:23 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 262720 kb
Host smart-9d538389-ccbe-4f55-86d5-4aa7e32d129b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257510438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1257510438
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.4154788307
Short name T82
Test name
Test status
Simulation time 77958570400 ps
CPU time 2698.4 seconds
Started May 21 03:12:08 PM PDT 24
Finished May 21 03:57:08 PM PDT 24
Peak memory 264552 kb
Host smart-bac89eec-ebd7-4aeb-9f36-1bc33ba4d86d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154788307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.4154788307
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.1197998448
Short name T352
Test name
Test status
Simulation time 25497500 ps
CPU time 13.81 seconds
Started May 21 03:14:09 PM PDT 24
Finished May 21 03:14:23 PM PDT 24
Peak memory 265172 kb
Host smart-3eae0f10-bcd1-461e-8200-c21e0d46d277
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197998448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.1197998448
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.2094219127
Short name T57
Test name
Test status
Simulation time 37858400 ps
CPU time 22.25 seconds
Started May 21 03:20:53 PM PDT 24
Finished May 21 03:21:16 PM PDT 24
Peak memory 265416 kb
Host smart-5714f380-cb17-477c-9742-e8fd64750e94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094219127 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.2094219127
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1888920284
Short name T443
Test name
Test status
Simulation time 8697563500 ps
CPU time 163.49 seconds
Started May 21 03:21:04 PM PDT 24
Finished May 21 03:23:48 PM PDT 24
Peak memory 265224 kb
Host smart-f690e320-28a5-411f-9bc1-445c0509052a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888920284 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.1888920284
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2244780747
Short name T388
Test name
Test status
Simulation time 349816600 ps
CPU time 56.07 seconds
Started May 21 03:21:30 PM PDT 24
Finished May 21 03:22:28 PM PDT 24
Peak memory 262416 kb
Host smart-82e98260-bbbe-4684-9a60-c5d3fa1cabd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244780747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2244780747
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.2742710041
Short name T360
Test name
Test status
Simulation time 14360900 ps
CPU time 22.38 seconds
Started May 21 03:22:42 PM PDT 24
Finished May 21 03:23:06 PM PDT 24
Peak memory 265312 kb
Host smart-abc27377-73e0-4d5c-80e1-4a0ffbe5c260
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742710041 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.2742710041
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.3964761043
Short name T632
Test name
Test status
Simulation time 17147400 ps
CPU time 22.15 seconds
Started May 21 03:23:00 PM PDT 24
Finished May 21 03:23:25 PM PDT 24
Peak memory 265316 kb
Host smart-3697cc21-a00f-429c-8e07-b8cb4f3dda5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964761043 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.3964761043
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3547826326
Short name T111
Test name
Test status
Simulation time 26083800 ps
CPU time 22.45 seconds
Started May 21 03:25:28 PM PDT 24
Finished May 21 03:25:52 PM PDT 24
Peak memory 265320 kb
Host smart-f22c1313-322e-4feb-9219-9aaf60363720
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547826326 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3547826326
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.366689067
Short name T179
Test name
Test status
Simulation time 77094300 ps
CPU time 126.89 seconds
Started May 21 03:14:30 PM PDT 24
Finished May 21 03:16:39 PM PDT 24
Peak memory 259892 kb
Host smart-a125928e-94a4-4f3b-9a1d-5adca1475fe6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366689067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp
_reset.366689067
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2258062035
Short name T540
Test name
Test status
Simulation time 99457774400 ps
CPU time 286.18 seconds
Started May 21 03:13:51 PM PDT 24
Finished May 21 03:18:38 PM PDT 24
Peak memory 265232 kb
Host smart-e8464b54-783d-41a9-a692-619c7f39a924
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225
8062035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2258062035
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2923595361
Short name T141
Test name
Test status
Simulation time 40125681600 ps
CPU time 846.26 seconds
Started May 21 03:19:01 PM PDT 24
Finished May 21 03:33:09 PM PDT 24
Peak memory 263272 kb
Host smart-6b45de2b-f3b2-4202-92bc-f06063aa1d97
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923595361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2923595361
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.3387762964
Short name T6
Test name
Test status
Simulation time 221528300 ps
CPU time 102.57 seconds
Started May 21 03:11:56 PM PDT 24
Finished May 21 03:13:39 PM PDT 24
Peak memory 262488 kb
Host smart-ac7d7189-f3d0-4757-9195-e66892a67ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387762964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3387762964
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.823099681
Short name T278
Test name
Test status
Simulation time 9902819200 ps
CPU time 629.9 seconds
Started May 21 03:16:57 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 330536 kb
Host smart-a9f1f59b-a9ed-41ed-816d-eb942df9754e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823099681 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_rw_derr.823099681
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.717066619
Short name T1162
Test name
Test status
Simulation time 50522900 ps
CPU time 18.79 seconds
Started May 21 02:39:15 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 264208 kb
Host smart-5617182e-ed9f-417e-98ac-7a550ea2c6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717066619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.717066619
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.663972763
Short name T273
Test name
Test status
Simulation time 43097500 ps
CPU time 18.3 seconds
Started May 21 02:39:08 PM PDT 24
Finished May 21 02:40:00 PM PDT 24
Peak memory 272348 kb
Host smart-8255790c-48d7-4aab-917e-54d86bc5400d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663972763 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.663972763
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2289795241
Short name T288
Test name
Test status
Simulation time 3747059300 ps
CPU time 2470.26 seconds
Started May 21 03:12:08 PM PDT 24
Finished May 21 03:53:19 PM PDT 24
Peak memory 264932 kb
Host smart-356cd7a5-7464-462a-9a60-ded0aa8f4994
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289795241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2289795241
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.92521504
Short name T156
Test name
Test status
Simulation time 376935560800 ps
CPU time 1954.48 seconds
Started May 21 03:14:42 PM PDT 24
Finished May 21 03:47:18 PM PDT 24
Peak memory 264900 kb
Host smart-241e2f1a-6176-4561-b2a4-c202162e50b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92521504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST
_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_host_ctrl_arb.92521504
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2442884660
Short name T119
Test name
Test status
Simulation time 3308580000 ps
CPU time 71.51 seconds
Started May 21 03:14:48 PM PDT 24
Finished May 21 03:16:00 PM PDT 24
Peak memory 260836 kb
Host smart-14b86241-3f43-4185-896e-956f55f9bd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442884660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2442884660
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2402317398
Short name T1115
Test name
Test status
Simulation time 623808300 ps
CPU time 35.44 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260688 kb
Host smart-971b9462-a1c8-48b6-850f-8678b410fdf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402317398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2402317398
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2289102664
Short name T1208
Test name
Test status
Simulation time 2862351800 ps
CPU time 45.48 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 262380 kb
Host smart-0980b350-eb3e-420c-993b-d9f6149f2dcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289102664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.2289102664
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1114826860
Short name T265
Test name
Test status
Simulation time 37761900 ps
CPU time 25.7 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:43 PM PDT 24
Peak memory 260472 kb
Host smart-ae886608-1e22-4e9b-8e15-116f899d2d56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114826860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1114826860
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2955154209
Short name T1185
Test name
Test status
Simulation time 145622200 ps
CPU time 15.11 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:33 PM PDT 24
Peak memory 272396 kb
Host smart-9ba3fc25-8e09-410d-b504-d4f579c19df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955154209 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2955154209
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.149975000
Short name T355
Test name
Test status
Simulation time 410680400 ps
CPU time 14.57 seconds
Started May 21 02:38:43 PM PDT 24
Finished May 21 02:39:34 PM PDT 24
Peak memory 260444 kb
Host smart-001dc472-3d93-4177-b88e-f3e52eaccfc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149975000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_csr_rw.149975000
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1448844003
Short name T313
Test name
Test status
Simulation time 15106400 ps
CPU time 13.27 seconds
Started May 21 02:38:40 PM PDT 24
Finished May 21 02:39:31 PM PDT 24
Peak memory 262904 kb
Host smart-380482db-ac94-4def-ba5b-68c117c24eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448844003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
448844003
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2287729442
Short name T1131
Test name
Test status
Simulation time 23110700 ps
CPU time 13.34 seconds
Started May 21 02:38:42 PM PDT 24
Finished May 21 02:39:32 PM PDT 24
Peak memory 262708 kb
Host smart-dbfb8fdf-2af6-41d9-827b-f8c7e87b8096
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287729442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2287729442
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1038709578
Short name T1145
Test name
Test status
Simulation time 451378400 ps
CPU time 34.33 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 262048 kb
Host smart-fdba882d-ac77-4190-b145-aa73e8270b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038709578 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1038709578
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2474464039
Short name T1232
Test name
Test status
Simulation time 46973700 ps
CPU time 15.93 seconds
Started May 21 02:38:42 PM PDT 24
Finished May 21 02:39:35 PM PDT 24
Peak memory 260472 kb
Host smart-f173a911-865c-41f6-823d-d2adc4387fa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474464039 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2474464039
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3787529852
Short name T1111
Test name
Test status
Simulation time 21801800 ps
CPU time 15.42 seconds
Started May 21 02:38:40 PM PDT 24
Finished May 21 02:39:32 PM PDT 24
Peak memory 260384 kb
Host smart-dedc5ec8-046b-4c4c-9a3a-e233118b5549
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787529852 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3787529852
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1847323544
Short name T1188
Test name
Test status
Simulation time 133408900 ps
CPU time 16.76 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:21 PM PDT 24
Peak memory 264156 kb
Host smart-f056699d-7b7a-4f70-8993-ce7cd2551a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847323544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
847323544
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4074276807
Short name T1173
Test name
Test status
Simulation time 3555321700 ps
CPU time 34.76 seconds
Started May 21 02:38:46 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 260496 kb
Host smart-51d959f6-c6a8-4316-9c8d-018f28f1c775
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074276807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.4074276807
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3840638993
Short name T354
Test name
Test status
Simulation time 2290952500 ps
CPU time 46.31 seconds
Started May 21 02:38:50 PM PDT 24
Finished May 21 02:40:15 PM PDT 24
Peak memory 263320 kb
Host smart-c35650f6-280d-4925-97d4-bd94422358f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840638993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3840638993
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3556396941
Short name T266
Test name
Test status
Simulation time 163979500 ps
CPU time 45.8 seconds
Started May 21 02:38:42 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260248 kb
Host smart-59e330cc-472d-46b9-a446-ecc4781970e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556396941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3556396941
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.75679533
Short name T1171
Test name
Test status
Simulation time 43725900 ps
CPU time 19.03 seconds
Started May 21 02:38:46 PM PDT 24
Finished May 21 02:39:42 PM PDT 24
Peak memory 278804 kb
Host smart-ef7b32de-871a-48e6-a4a1-b5577f16c0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75679533 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.75679533
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.958952501
Short name T1153
Test name
Test status
Simulation time 62729800 ps
CPU time 14.6 seconds
Started May 21 02:38:52 PM PDT 24
Finished May 21 02:39:45 PM PDT 24
Peak memory 260576 kb
Host smart-cd31ac20-c32b-4e62-bcfc-03ff0515787a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958952501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_csr_rw.958952501
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2388946612
Short name T251
Test name
Test status
Simulation time 27740500 ps
CPU time 13.12 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:31 PM PDT 24
Peak memory 263704 kb
Host smart-5d3ef433-9ee0-487a-a06a-ca4f9081c0dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388946612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2388946612
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.458488152
Short name T1246
Test name
Test status
Simulation time 52769100 ps
CPU time 13.25 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:31 PM PDT 24
Peak memory 262748 kb
Host smart-f0f32f95-3301-410a-ac67-ffc2e0990a84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458488152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.458488152
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2491229277
Short name T1214
Test name
Test status
Simulation time 130017700 ps
CPU time 28.58 seconds
Started May 21 02:38:47 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260580 kb
Host smart-76824c27-b41b-4e7b-a2a1-aa9696c8aeb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491229277 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2491229277
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1307166456
Short name T1186
Test name
Test status
Simulation time 32499000 ps
CPU time 15.57 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:33 PM PDT 24
Peak memory 260512 kb
Host smart-ad463639-220a-45ee-8532-c2f3dc0139ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307166456 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.1307166456
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3215478157
Short name T1114
Test name
Test status
Simulation time 19984000 ps
CPU time 15.48 seconds
Started May 21 02:38:41 PM PDT 24
Finished May 21 02:39:33 PM PDT 24
Peak memory 260324 kb
Host smart-3ef59908-5489-4a8a-aa16-60b26770d7e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215478157 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3215478157
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3691151515
Short name T1147
Test name
Test status
Simulation time 63937500 ps
CPU time 19.95 seconds
Started May 21 02:38:40 PM PDT 24
Finished May 21 02:39:37 PM PDT 24
Peak memory 264200 kb
Host smart-3b4eac8b-9cf6-4f4b-8602-ddeb708cbb01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691151515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
691151515
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2859215294
Short name T342
Test name
Test status
Simulation time 1734652600 ps
CPU time 450.39 seconds
Started May 21 02:38:40 PM PDT 24
Finished May 21 02:46:47 PM PDT 24
Peak memory 260456 kb
Host smart-65d19af7-e363-4e71-b1c8-f7a119595c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859215294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2859215294
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1906680426
Short name T1239
Test name
Test status
Simulation time 141381100 ps
CPU time 18.46 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 272356 kb
Host smart-694d5b82-2be4-455e-9c28-156442bd836b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906680426 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1906680426
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.814429684
Short name T1116
Test name
Test status
Simulation time 379232300 ps
CPU time 17.51 seconds
Started May 21 02:41:04 PM PDT 24
Finished May 21 02:41:37 PM PDT 24
Peak memory 260612 kb
Host smart-a112dbf2-0528-4143-9da6-6fc3509fcca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814429684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.814429684
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2905731129
Short name T1168
Test name
Test status
Simulation time 50555700 ps
CPU time 13.23 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:39:59 PM PDT 24
Peak memory 262672 kb
Host smart-87b730cf-ac0b-4d59-a827-0b65e2f4c95a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905731129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2905731129
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3524912926
Short name T257
Test name
Test status
Simulation time 127715200 ps
CPU time 17.55 seconds
Started May 21 02:39:14 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260548 kb
Host smart-775a4926-bb39-4c64-9276-a05e27df923f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524912926 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3524912926
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2515369552
Short name T1118
Test name
Test status
Simulation time 35209800 ps
CPU time 15.28 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:40:01 PM PDT 24
Peak memory 260476 kb
Host smart-1ab9af70-633f-4bcb-a80f-1ec4e36b26fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515369552 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2515369552
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3194874399
Short name T1156
Test name
Test status
Simulation time 19786400 ps
CPU time 15.72 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260520 kb
Host smart-9a62a422-c237-46c8-90f9-696fa910d0f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194874399 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3194874399
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1563557490
Short name T195
Test name
Test status
Simulation time 48340600 ps
CPU time 16.13 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 264212 kb
Host smart-daf440a4-7f27-4957-8300-0c6c3c88401d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563557490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1563557490
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1965292621
Short name T271
Test name
Test status
Simulation time 33930100 ps
CPU time 18.66 seconds
Started May 21 02:39:13 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 280552 kb
Host smart-25d9d8e5-7349-4f31-95a9-e77b1126fda0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965292621 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1965292621
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1111758015
Short name T1221
Test name
Test status
Simulation time 209707700 ps
CPU time 17.5 seconds
Started May 21 02:39:14 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260692 kb
Host smart-97a14db4-3e57-41e5-b867-7aee97eaf184
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111758015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1111758015
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1668965261
Short name T1174
Test name
Test status
Simulation time 17480500 ps
CPU time 13.52 seconds
Started May 21 02:39:14 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 262552 kb
Host smart-603d5f76-58ff-4fc7-b011-f9d74ab3de87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668965261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1668965261
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.524193306
Short name T1215
Test name
Test status
Simulation time 121083900 ps
CPU time 34 seconds
Started May 21 02:39:16 PM PDT 24
Finished May 21 02:40:20 PM PDT 24
Peak memory 260552 kb
Host smart-92cb1424-e282-4bd8-92d0-056eefd1f1e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524193306 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.524193306
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3836475991
Short name T1242
Test name
Test status
Simulation time 23564400 ps
CPU time 15.58 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260492 kb
Host smart-acaeb323-54c5-4186-a2b6-31a6bb8f3cb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836475991 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3836475991
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1546613677
Short name T1205
Test name
Test status
Simulation time 130456100 ps
CPU time 12.99 seconds
Started May 21 02:39:15 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 260480 kb
Host smart-cedc7772-4e1e-4a33-8b2c-0f3832c3aaa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546613677 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1546613677
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.107963974
Short name T293
Test name
Test status
Simulation time 182981000 ps
CPU time 18.66 seconds
Started May 21 02:39:15 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 271516 kb
Host smart-dff1e557-728d-4929-bb3d-55c6f10947f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107963974 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.107963974
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3064361079
Short name T1233
Test name
Test status
Simulation time 203564600 ps
CPU time 14.68 seconds
Started May 21 02:39:14 PM PDT 24
Finished May 21 02:39:59 PM PDT 24
Peak memory 262120 kb
Host smart-d4f38536-50ef-44db-a6ee-25e4da8421dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064361079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3064361079
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.716094295
Short name T1141
Test name
Test status
Simulation time 43496900 ps
CPU time 17.7 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260588 kb
Host smart-f99bf263-99ff-4d3c-9d17-d9c38797c077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716094295 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.716094295
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3053025441
Short name T1113
Test name
Test status
Simulation time 199756200 ps
CPU time 13.61 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:00 PM PDT 24
Peak memory 260620 kb
Host smart-65f859a5-2494-465e-ae75-6e729dad20a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053025441 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3053025441
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.692128422
Short name T1159
Test name
Test status
Simulation time 19845200 ps
CPU time 15.49 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260520 kb
Host smart-517608b9-8499-49be-a836-32c65f2663d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692128422 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.692128422
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3838255743
Short name T270
Test name
Test status
Simulation time 180029200 ps
CPU time 18.26 seconds
Started May 21 02:41:04 PM PDT 24
Finished May 21 02:41:37 PM PDT 24
Peak memory 264220 kb
Host smart-9ccf2081-bd43-43ed-8396-4aaf8ac7e276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838255743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3838255743
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4254940317
Short name T351
Test name
Test status
Simulation time 1336246600 ps
CPU time 452.34 seconds
Started May 21 02:39:14 PM PDT 24
Finished May 21 02:47:17 PM PDT 24
Peak memory 262740 kb
Host smart-49848e2f-f66e-47c3-bd73-e3a589ca42a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254940317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.4254940317
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2691295712
Short name T64
Test name
Test status
Simulation time 79513200 ps
CPU time 14.08 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:01 PM PDT 24
Peak memory 260628 kb
Host smart-9293bdc0-f1d9-475e-95f8-f9c38736e9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691295712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.2691295712
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2183162050
Short name T1163
Test name
Test status
Simulation time 28799900 ps
CPU time 13.26 seconds
Started May 21 02:39:22 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 262968 kb
Host smart-8e95a0c3-0e6e-41e6-ab2b-eaf67ab858c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183162050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
2183162050
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.254438925
Short name T256
Test name
Test status
Simulation time 41132400 ps
CPU time 17.18 seconds
Started May 21 02:39:23 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 260560 kb
Host smart-9a3b3200-02d4-43e8-88f9-6916b9153ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254438925 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.254438925
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3631071391
Short name T1193
Test name
Test status
Simulation time 58102400 ps
CPU time 12.85 seconds
Started May 21 02:39:23 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 260496 kb
Host smart-bc686ce6-c875-4121-b13d-e30f1694b612
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631071391 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3631071391
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2799050069
Short name T1231
Test name
Test status
Simulation time 20728100 ps
CPU time 15.4 seconds
Started May 21 02:39:22 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260548 kb
Host smart-073bab70-98c2-4ceb-aedb-2f32188ff4c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799050069 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.2799050069
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4110973432
Short name T1228
Test name
Test status
Simulation time 102085500 ps
CPU time 15.46 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 264176 kb
Host smart-81d7922c-4044-41ce-ae04-de88e72b4701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110973432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
4110973432
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2489279532
Short name T349
Test name
Test status
Simulation time 369165800 ps
CPU time 891.05 seconds
Started May 21 02:39:17 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 261792 kb
Host smart-5df73f43-3e88-41a2-be54-26426f353493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489279532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2489279532
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2074576801
Short name T1127
Test name
Test status
Simulation time 88143500 ps
CPU time 16.31 seconds
Started May 21 02:39:17 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 271700 kb
Host smart-1ec80f35-0666-4f94-a925-c2f92c5e24b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074576801 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2074576801
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4266477960
Short name T1139
Test name
Test status
Simulation time 57328200 ps
CPU time 17.32 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260480 kb
Host smart-1e7d655e-7298-4604-bfae-bd72538cf644
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266477960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.4266477960
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.520295520
Short name T1223
Test name
Test status
Simulation time 70315600 ps
CPU time 13.25 seconds
Started May 21 02:41:02 PM PDT 24
Finished May 21 02:41:31 PM PDT 24
Peak memory 262844 kb
Host smart-fbb948a5-82d6-428a-ac85-376cf6641fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520295520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.520295520
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1278955446
Short name T1150
Test name
Test status
Simulation time 361768200 ps
CPU time 18.02 seconds
Started May 21 02:39:21 PM PDT 24
Finished May 21 02:40:06 PM PDT 24
Peak memory 260584 kb
Host smart-4b703370-77e4-4d5d-92df-f1bf39087300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278955446 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1278955446
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1503346116
Short name T1230
Test name
Test status
Simulation time 13130100 ps
CPU time 16.14 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 260568 kb
Host smart-10c68748-1368-4876-b879-11518203cee3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503346116 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1503346116
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.393311095
Short name T1177
Test name
Test status
Simulation time 24616600 ps
CPU time 15.46 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260528 kb
Host smart-00d7dd04-e82c-44de-985b-8a7be52d12d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393311095 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.393311095
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3653024467
Short name T268
Test name
Test status
Simulation time 220049000 ps
CPU time 18.57 seconds
Started May 21 02:39:22 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 264232 kb
Host smart-6a11e8ac-8cfb-4727-881c-85c5fc2bc181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653024467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3653024467
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2989574988
Short name T197
Test name
Test status
Simulation time 192625800 ps
CPU time 374.52 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:47:36 PM PDT 24
Peak memory 264172 kb
Host smart-77856d59-288a-409e-ad06-936966a91f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989574988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.2989574988
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.282530049
Short name T245
Test name
Test status
Simulation time 95226000 ps
CPU time 17.46 seconds
Started May 21 02:39:24 PM PDT 24
Finished May 21 02:40:08 PM PDT 24
Peak memory 270676 kb
Host smart-11f19075-cbcf-48d8-934c-59f7883550b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282530049 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.282530049
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2911191734
Short name T1243
Test name
Test status
Simulation time 35656000 ps
CPU time 16.46 seconds
Started May 21 02:39:21 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260496 kb
Host smart-2fefc904-c158-4d2f-9bf4-776a991636d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911191734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2911191734
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.686211822
Short name T1192
Test name
Test status
Simulation time 55814300 ps
CPU time 13.79 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:00 PM PDT 24
Peak memory 262640 kb
Host smart-23334a78-9b01-4caf-8391-33ef6607d401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686211822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.686211822
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3960220827
Short name T1178
Test name
Test status
Simulation time 62659200 ps
CPU time 19.21 seconds
Started May 21 02:39:17 PM PDT 24
Finished May 21 02:40:05 PM PDT 24
Peak memory 261932 kb
Host smart-ea592e9d-52f8-48b5-9e2a-3a3c00a5fbd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960220827 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3960220827
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3524071501
Short name T1143
Test name
Test status
Simulation time 13626300 ps
CPU time 15.59 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260516 kb
Host smart-8b009a05-a728-405d-ac48-be363571eaf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524071501 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3524071501
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3673024555
Short name T1212
Test name
Test status
Simulation time 41755900 ps
CPU time 13.34 seconds
Started May 21 02:39:18 PM PDT 24
Finished May 21 02:40:00 PM PDT 24
Peak memory 260496 kb
Host smart-5d82a432-fff8-48be-b2e1-1e1a46cc6df3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673024555 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3673024555
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2915825848
Short name T1200
Test name
Test status
Simulation time 56437200 ps
CPU time 18.91 seconds
Started May 21 02:39:17 PM PDT 24
Finished May 21 02:40:05 PM PDT 24
Peak memory 264208 kb
Host smart-9765069d-baae-4f6f-bb95-483e9cacf41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915825848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2915825848
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.974061256
Short name T1170
Test name
Test status
Simulation time 2608857400 ps
CPU time 455.41 seconds
Started May 21 02:39:19 PM PDT 24
Finished May 21 02:47:22 PM PDT 24
Peak memory 264160 kb
Host smart-42fe84fa-f70d-45a5-879e-9d55c8c5db31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974061256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.974061256
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2233829442
Short name T244
Test name
Test status
Simulation time 223044200 ps
CPU time 18.38 seconds
Started May 21 02:39:25 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 277736 kb
Host smart-36de5d1e-e5cd-40cc-9d01-df0da29da56c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233829442 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2233829442
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.337480403
Short name T1238
Test name
Test status
Simulation time 111513000 ps
CPU time 17.12 seconds
Started May 21 02:39:29 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262856 kb
Host smart-db181fed-de02-4271-b753-5efaa3dc2989
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337480403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_csr_rw.337480403
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3159549837
Short name T1203
Test name
Test status
Simulation time 16935800 ps
CPU time 13.4 seconds
Started May 21 02:39:24 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 262908 kb
Host smart-a17888be-963f-48c9-8189-d8a2e549abf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159549837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
3159549837
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4010493262
Short name T1187
Test name
Test status
Simulation time 985833300 ps
CPU time 28.61 seconds
Started May 21 02:39:29 PM PDT 24
Finished May 21 02:40:21 PM PDT 24
Peak memory 260560 kb
Host smart-e0d6eb0e-fe81-4de3-a081-6ebf413eee83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010493262 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.4010493262
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.264267391
Short name T1189
Test name
Test status
Simulation time 23916000 ps
CPU time 15.23 seconds
Started May 21 02:39:29 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 260532 kb
Host smart-51bb8f8a-05cb-4f26-bdf9-e997b0e406c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264267391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.264267391
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1503702875
Short name T1107
Test name
Test status
Simulation time 11328100 ps
CPU time 15.21 seconds
Started May 21 02:39:30 PM PDT 24
Finished May 21 02:40:08 PM PDT 24
Peak memory 260528 kb
Host smart-2e79c8f8-6f79-429b-8f43-41e1f8690c64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503702875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1503702875
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1370712008
Short name T1210
Test name
Test status
Simulation time 56863400 ps
CPU time 20.06 seconds
Started May 21 02:39:26 PM PDT 24
Finished May 21 02:40:12 PM PDT 24
Peak memory 264192 kb
Host smart-aae48ae1-73ef-4db0-a941-5ad795d478fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370712008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1370712008
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1609754153
Short name T1149
Test name
Test status
Simulation time 113388900 ps
CPU time 16.54 seconds
Started May 21 02:39:24 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 279520 kb
Host smart-ef60a571-c1a6-4432-a09d-94a926bc0655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609754153 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1609754153
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.950586533
Short name T1226
Test name
Test status
Simulation time 122352900 ps
CPU time 16.75 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:41:39 PM PDT 24
Peak memory 260548 kb
Host smart-d55cf946-0406-413f-bc9c-81ea7790d4a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950586533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.950586533
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1242417917
Short name T1112
Test name
Test status
Simulation time 84433800 ps
CPU time 15.15 seconds
Started May 21 02:39:25 PM PDT 24
Finished May 21 02:40:06 PM PDT 24
Peak memory 264140 kb
Host smart-8673621f-019d-4969-9bed-bc9c8d4330ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242417917 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1242417917
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3332448801
Short name T1108
Test name
Test status
Simulation time 37171200 ps
CPU time 13.48 seconds
Started May 21 02:39:25 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260512 kb
Host smart-67297d25-1448-44a3-9386-beef9ce3944d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332448801 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3332448801
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2149388926
Short name T1184
Test name
Test status
Simulation time 38138800 ps
CPU time 13.04 seconds
Started May 21 02:39:25 PM PDT 24
Finished May 21 02:40:04 PM PDT 24
Peak memory 260556 kb
Host smart-bffdcedd-6308-43a2-a3d3-33292e585b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149388926 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2149388926
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.621049687
Short name T272
Test name
Test status
Simulation time 134996400 ps
CPU time 16.19 seconds
Started May 21 02:39:26 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 264208 kb
Host smart-7e4c8c06-7ea1-45c4-8fd4-09e661cb0ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621049687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.621049687
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3014642797
Short name T291
Test name
Test status
Simulation time 1730479100 ps
CPU time 888.33 seconds
Started May 21 02:39:27 PM PDT 24
Finished May 21 02:54:40 PM PDT 24
Peak memory 264224 kb
Host smart-c26905bb-adb4-4e7a-b056-6bc1fd30ae68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014642797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3014642797
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1604593385
Short name T1234
Test name
Test status
Simulation time 47902000 ps
CPU time 17.63 seconds
Started May 21 02:39:30 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 277708 kb
Host smart-e248a00d-0e0e-443a-9466-1e7b697a5873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604593385 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1604593385
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1571350353
Short name T1217
Test name
Test status
Simulation time 46810000 ps
CPU time 14.68 seconds
Started May 21 02:39:31 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 260724 kb
Host smart-870f5ca6-eedb-4b3c-9eaa-0908be4d22fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571350353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1571350353
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3412381832
Short name T1166
Test name
Test status
Simulation time 28171000 ps
CPU time 13.44 seconds
Started May 21 02:39:31 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 262636 kb
Host smart-559516e7-6b37-400b-9397-868e59ec01ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412381832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3412381832
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.677699169
Short name T1240
Test name
Test status
Simulation time 221269800 ps
CPU time 32.57 seconds
Started May 21 02:39:33 PM PDT 24
Finished May 21 02:40:28 PM PDT 24
Peak memory 263500 kb
Host smart-c6079df2-c973-4b42-9ab9-51b0177e7465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677699169 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.677699169
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1794211423
Short name T1137
Test name
Test status
Simulation time 14199500 ps
CPU time 12.91 seconds
Started May 21 02:39:29 PM PDT 24
Finished May 21 02:40:05 PM PDT 24
Peak memory 260536 kb
Host smart-e4eb07ea-ff2f-46e8-aa68-e422a4c4ef13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794211423 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1794211423
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.922065841
Short name T1138
Test name
Test status
Simulation time 19947300 ps
CPU time 13.04 seconds
Started May 21 02:39:30 PM PDT 24
Finished May 21 02:40:06 PM PDT 24
Peak memory 260540 kb
Host smart-dbba5a68-5845-4f5c-8fd5-ecc669695322
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922065841 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.922065841
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.480048690
Short name T344
Test name
Test status
Simulation time 1380313900 ps
CPU time 891.35 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 261852 kb
Host smart-83c4ff81-4f45-4710-9168-b0b813541ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480048690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_tl_intg_err.480048690
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2230839019
Short name T1135
Test name
Test status
Simulation time 198547700 ps
CPU time 14.59 seconds
Started May 21 02:39:41 PM PDT 24
Finished May 21 02:40:16 PM PDT 24
Peak memory 270868 kb
Host smart-1e175ba3-e61f-421d-8ce5-d6e3bd89b36e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230839019 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2230839019
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2933143857
Short name T1213
Test name
Test status
Simulation time 74101600 ps
CPU time 16.11 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:19 PM PDT 24
Peak memory 260532 kb
Host smart-f639e570-4056-45c5-a24c-da7b58f56ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933143857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2933143857
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1649415438
Short name T1235
Test name
Test status
Simulation time 30870700 ps
CPU time 13.19 seconds
Started May 21 02:39:31 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 262876 kb
Host smart-2fbe3963-545e-438b-bd89-2b27f2a8acd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649415438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1649415438
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2011199291
Short name T301
Test name
Test status
Simulation time 204675900 ps
CPU time 21.17 seconds
Started May 21 02:39:30 PM PDT 24
Finished May 21 02:40:14 PM PDT 24
Peak memory 262460 kb
Host smart-97b85559-39ad-4453-8790-ed9234d4d530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011199291 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2011199291
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.749618246
Short name T1110
Test name
Test status
Simulation time 11855600 ps
CPU time 13.12 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:41:31 PM PDT 24
Peak memory 260528 kb
Host smart-6b5351eb-5030-4950-a882-682d6ecf1da5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749618246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.749618246
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2803324406
Short name T1160
Test name
Test status
Simulation time 12610000 ps
CPU time 15.51 seconds
Started May 21 02:39:29 PM PDT 24
Finished May 21 02:40:08 PM PDT 24
Peak memory 260488 kb
Host smart-f4e73cff-3c61-469d-a860-f79a6b8ff168
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803324406 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2803324406
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2492429820
Short name T1190
Test name
Test status
Simulation time 135164300 ps
CPU time 16.42 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:18 PM PDT 24
Peak memory 264224 kb
Host smart-acb19b54-3126-4bb2-a215-eb2bcbbaec63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492429820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
2492429820
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1348372471
Short name T63
Test name
Test status
Simulation time 188559800 ps
CPU time 452.4 seconds
Started May 21 02:39:32 PM PDT 24
Finished May 21 02:47:27 PM PDT 24
Peak memory 264220 kb
Host smart-8760565e-31aa-4f8a-9da0-bcedc159a793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348372471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1348372471
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4168224776
Short name T1133
Test name
Test status
Simulation time 16034866200 ps
CPU time 64.8 seconds
Started May 21 02:38:55 PM PDT 24
Finished May 21 02:40:37 PM PDT 24
Peak memory 260588 kb
Host smart-d84bfca5-0e9b-48d3-9470-f717d53e5b8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168224776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.4168224776
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2149273912
Short name T198
Test name
Test status
Simulation time 4872375100 ps
CPU time 57.1 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:40:28 PM PDT 24
Peak memory 262376 kb
Host smart-e7cc3ad3-2d10-41c6-a8f3-d7423cf159f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149273912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.2149273912
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.629053733
Short name T1204
Test name
Test status
Simulation time 64217400 ps
CPU time 30.89 seconds
Started May 21 02:38:46 PM PDT 24
Finished May 21 02:39:54 PM PDT 24
Peak memory 260532 kb
Host smart-14f594b8-19f3-4538-afa2-c2d9c26c92c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629053733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.629053733
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.558445902
Short name T302
Test name
Test status
Simulation time 108970800 ps
CPU time 19.38 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:39:50 PM PDT 24
Peak memory 270496 kb
Host smart-bfe6ba00-1a97-4132-a49b-69addff3f224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558445902 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.558445902
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2214339777
Short name T353
Test name
Test status
Simulation time 25460300 ps
CPU time 14.83 seconds
Started May 21 02:38:47 PM PDT 24
Finished May 21 02:39:39 PM PDT 24
Peak memory 260524 kb
Host smart-fbbb0ee9-1a57-459d-8370-6e649f74b342
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214339777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.2214339777
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3615403653
Short name T1130
Test name
Test status
Simulation time 15373400 ps
CPU time 13.13 seconds
Started May 21 02:38:46 PM PDT 24
Finished May 21 02:39:36 PM PDT 24
Peak memory 262744 kb
Host smart-c0aa06c1-1207-4bf5-b449-d1aaf62e09e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615403653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
615403653
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3280441025
Short name T248
Test name
Test status
Simulation time 17025300 ps
CPU time 13.27 seconds
Started May 21 02:38:52 PM PDT 24
Finished May 21 02:39:43 PM PDT 24
Peak memory 264100 kb
Host smart-36c37518-430b-4879-ac9b-661df8fa09eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280441025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.3280441025
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.200198116
Short name T1202
Test name
Test status
Simulation time 25891000 ps
CPU time 13.1 seconds
Started May 21 02:38:52 PM PDT 24
Finished May 21 02:39:43 PM PDT 24
Peak memory 262860 kb
Host smart-b8e9c5a6-087e-4f07-8de6-6ada5dcab4f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200198116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.200198116
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3493271999
Short name T303
Test name
Test status
Simulation time 851240800 ps
CPU time 35.43 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 260572 kb
Host smart-997c99c1-f2c1-49da-94e0-caefb5326c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493271999 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3493271999
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3776206670
Short name T1197
Test name
Test status
Simulation time 60402200 ps
CPU time 15.36 seconds
Started May 21 02:38:50 PM PDT 24
Finished May 21 02:39:44 PM PDT 24
Peak memory 260480 kb
Host smart-52054cfe-99fd-455c-b2ab-dcf6e01b434c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776206670 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3776206670
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1717936953
Short name T1126
Test name
Test status
Simulation time 19882000 ps
CPU time 15.56 seconds
Started May 21 02:38:44 PM PDT 24
Finished May 21 02:39:36 PM PDT 24
Peak memory 260508 kb
Host smart-87d765ee-6b0d-4c2b-84e5-3446de1c5163
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717936953 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1717936953
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3110098753
Short name T314
Test name
Test status
Simulation time 30578600 ps
CPU time 13.31 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:41:35 PM PDT 24
Peak memory 262496 kb
Host smart-19608cea-66c5-4eaa-832c-1c0bb2ab7919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110098753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3110098753
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2259678084
Short name T315
Test name
Test status
Simulation time 18808000 ps
CPU time 13.37 seconds
Started May 21 02:39:32 PM PDT 24
Finished May 21 02:40:08 PM PDT 24
Peak memory 262676 kb
Host smart-1b40e6d3-2dee-4e32-91cf-58a0ee50bb40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259678084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2259678084
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3150913943
Short name T310
Test name
Test status
Simulation time 28710700 ps
CPU time 13.21 seconds
Started May 21 02:39:33 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262744 kb
Host smart-aed50cdb-e0eb-4009-8e62-63a78ebcaa33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150913943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3150913943
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1656959952
Short name T1219
Test name
Test status
Simulation time 29851300 ps
CPU time 13.21 seconds
Started May 21 02:39:41 PM PDT 24
Finished May 21 02:40:14 PM PDT 24
Peak memory 262928 kb
Host smart-4e859686-8c5e-47bd-b6da-de762e58c8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656959952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1656959952
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2034404555
Short name T1224
Test name
Test status
Simulation time 136774400 ps
CPU time 13.22 seconds
Started May 21 02:39:41 PM PDT 24
Finished May 21 02:40:14 PM PDT 24
Peak memory 262840 kb
Host smart-29388275-2270-43eb-8c7d-0c7a846f45f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034404555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2034404555
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3104274242
Short name T1161
Test name
Test status
Simulation time 32478100 ps
CPU time 13.16 seconds
Started May 21 02:39:34 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262796 kb
Host smart-184c55d4-d76e-40d1-9849-1f6569e13a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104274242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
3104274242
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3747893115
Short name T1144
Test name
Test status
Simulation time 19913100 ps
CPU time 13.24 seconds
Started May 21 02:39:41 PM PDT 24
Finished May 21 02:40:15 PM PDT 24
Peak memory 262912 kb
Host smart-5e3d63bd-c689-4e1c-960d-dbf875038123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747893115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
3747893115
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.193646057
Short name T262
Test name
Test status
Simulation time 16937400 ps
CPU time 13.66 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 262948 kb
Host smart-0dbfca58-0985-45a9-bdb0-6ab5164bdd53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193646057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.193646057
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1028047511
Short name T1142
Test name
Test status
Simulation time 20609300 ps
CPU time 13.59 seconds
Started May 21 02:39:39 PM PDT 24
Finished May 21 02:40:13 PM PDT 24
Peak memory 262332 kb
Host smart-b13fa3ad-5013-480f-bdc6-b116a99e89bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028047511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1028047511
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.4228193780
Short name T1125
Test name
Test status
Simulation time 17153800 ps
CPU time 13.52 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:41:36 PM PDT 24
Peak memory 262552 kb
Host smart-dc798ee4-1683-4738-b4fe-903fa8f77f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228193780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
4228193780
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.403816574
Short name T309
Test name
Test status
Simulation time 1302821900 ps
CPU time 58.23 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:40:29 PM PDT 24
Peak memory 260512 kb
Host smart-ac22c759-455f-49d2-b242-8ceb33d51a0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403816574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.403816574
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.435459946
Short name T290
Test name
Test status
Simulation time 2918044700 ps
CPU time 72.59 seconds
Started May 21 02:38:52 PM PDT 24
Finished May 21 02:40:43 PM PDT 24
Peak memory 260520 kb
Host smart-37b203e9-45ce-4fe8-a20d-58e953e010e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435459946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.435459946
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3454456852
Short name T267
Test name
Test status
Simulation time 20826000 ps
CPU time 30.23 seconds
Started May 21 02:38:54 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 260528 kb
Host smart-0c68658f-2583-470c-87fd-41fd969834dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454456852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3454456852
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.416534215
Short name T1241
Test name
Test status
Simulation time 169088800 ps
CPU time 17.26 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:39:48 PM PDT 24
Peak memory 264188 kb
Host smart-c67e3965-ab2e-465a-a4dd-aebab6a2c5c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416534215 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.416534215
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3099423555
Short name T1128
Test name
Test status
Simulation time 103738900 ps
CPU time 16.65 seconds
Started May 21 02:38:54 PM PDT 24
Finished May 21 02:39:48 PM PDT 24
Peak memory 260640 kb
Host smart-35675241-c840-4e6c-9b48-48e1f7523cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099423555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.3099423555
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1743272462
Short name T312
Test name
Test status
Simulation time 39456000 ps
CPU time 13.63 seconds
Started May 21 02:38:54 PM PDT 24
Finished May 21 02:39:45 PM PDT 24
Peak memory 261592 kb
Host smart-a7ef8aac-9b9a-424f-b2ba-349d08127a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743272462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
743272462
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1483926869
Short name T247
Test name
Test status
Simulation time 17037300 ps
CPU time 13.16 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:39:44 PM PDT 24
Peak memory 264132 kb
Host smart-43eb800d-02ea-4a09-8cd1-68d3b498f04a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483926869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1483926869
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.115245443
Short name T1191
Test name
Test status
Simulation time 207372100 ps
CPU time 13.12 seconds
Started May 21 02:38:54 PM PDT 24
Finished May 21 02:39:45 PM PDT 24
Peak memory 262712 kb
Host smart-7ebfb14d-f836-4019-86b0-390eaa5e9782
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115245443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.115245443
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.864709099
Short name T1211
Test name
Test status
Simulation time 62044100 ps
CPU time 19.8 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:39:50 PM PDT 24
Peak memory 260576 kb
Host smart-6c56c0a2-5708-4bec-8164-3823fded33d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864709099 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.864709099
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.962051560
Short name T1206
Test name
Test status
Simulation time 44561800 ps
CPU time 15.63 seconds
Started May 21 02:38:51 PM PDT 24
Finished May 21 02:39:46 PM PDT 24
Peak memory 260460 kb
Host smart-dbc9d409-964b-4ddc-a9a7-0cab83d5fe8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962051560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.962051560
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3890975665
Short name T1154
Test name
Test status
Simulation time 21534700 ps
CPU time 15.61 seconds
Started May 21 02:38:51 PM PDT 24
Finished May 21 02:39:46 PM PDT 24
Peak memory 260564 kb
Host smart-7a121ccc-b5d2-4c17-b0e8-1c39113509b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890975665 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3890975665
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1380929951
Short name T1199
Test name
Test status
Simulation time 395341900 ps
CPU time 447.71 seconds
Started May 21 02:38:53 PM PDT 24
Finished May 21 02:46:58 PM PDT 24
Peak memory 264192 kb
Host smart-e87f93fb-7f50-4b7c-90b6-cdb7ebc244b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380929951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1380929951
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1831929312
Short name T1120
Test name
Test status
Simulation time 18311700 ps
CPU time 13.25 seconds
Started May 21 02:39:34 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262944 kb
Host smart-606c0fb1-48e7-4a7c-a37b-e43537d1c587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831929312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1831929312
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2369107530
Short name T1196
Test name
Test status
Simulation time 31719800 ps
CPU time 13.12 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262776 kb
Host smart-b6b42e58-a320-4d0a-90d1-3f652f200846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369107530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
2369107530
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2189980974
Short name T1181
Test name
Test status
Simulation time 21789100 ps
CPU time 13.27 seconds
Started May 21 02:39:35 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262680 kb
Host smart-00025823-487e-4198-a387-2bbbcfe778d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189980974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2189980974
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3606065863
Short name T1180
Test name
Test status
Simulation time 31690500 ps
CPU time 13.59 seconds
Started May 21 02:39:34 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262668 kb
Host smart-6bd2dc34-a2a6-4b3c-977f-6e203117a7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606065863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3606065863
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3873876247
Short name T1201
Test name
Test status
Simulation time 16737800 ps
CPU time 13.39 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262984 kb
Host smart-d53f8178-8183-47b3-b84d-3d8419b6edc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873876247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3873876247
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2244718383
Short name T1237
Test name
Test status
Simulation time 16000600 ps
CPU time 13.55 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 261528 kb
Host smart-94867d4b-707f-4026-a5b2-344a5e9e5ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244718383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
2244718383
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1450414815
Short name T339
Test name
Test status
Simulation time 54517800 ps
CPU time 13.12 seconds
Started May 21 02:39:34 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262552 kb
Host smart-b1113ba2-8083-4bd4-86de-09dae3182a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450414815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1450414815
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2947181743
Short name T1207
Test name
Test status
Simulation time 25771900 ps
CPU time 13.57 seconds
Started May 21 02:39:35 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262664 kb
Host smart-0757098c-eaff-4c7a-8a9c-ee66b1d03bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947181743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2947181743
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2788594259
Short name T1175
Test name
Test status
Simulation time 30037500 ps
CPU time 13.2 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:40:16 PM PDT 24
Peak memory 262648 kb
Host smart-9611f522-2030-41c3-9880-b4dacc00cca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788594259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2788594259
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2722649891
Short name T1164
Test name
Test status
Simulation time 58922000 ps
CPU time 13.56 seconds
Started May 21 02:39:40 PM PDT 24
Finished May 21 02:40:13 PM PDT 24
Peak memory 262632 kb
Host smart-84b0a78a-def4-430b-8d1d-52b093981a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722649891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2722649891
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4142449069
Short name T298
Test name
Test status
Simulation time 850946900 ps
CPU time 41.77 seconds
Started May 21 02:38:59 PM PDT 24
Finished May 21 02:40:19 PM PDT 24
Peak memory 260724 kb
Host smart-9cdd98dc-fa90-4e37-9246-d59358241952
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142449069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.4142449069
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3827810539
Short name T62
Test name
Test status
Simulation time 1203101500 ps
CPU time 46.28 seconds
Started May 21 02:38:58 PM PDT 24
Finished May 21 02:40:22 PM PDT 24
Peak memory 260472 kb
Host smart-7581e21a-b020-4133-b420-e953400406c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827810539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3827810539
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2192034519
Short name T1222
Test name
Test status
Simulation time 50719700 ps
CPU time 30.24 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 260504 kb
Host smart-5e08e351-c797-4ecf-adc9-159ef91872d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192034519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.2192034519
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3594598064
Short name T297
Test name
Test status
Simulation time 135090600 ps
CPU time 19.24 seconds
Started May 21 02:39:00 PM PDT 24
Finished May 21 02:39:56 PM PDT 24
Peak memory 272392 kb
Host smart-7055f630-2b31-46c0-80ca-c6513588d869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594598064 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3594598064
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.206490410
Short name T292
Test name
Test status
Simulation time 271786900 ps
CPU time 17.57 seconds
Started May 21 02:38:59 PM PDT 24
Finished May 21 02:39:54 PM PDT 24
Peak memory 260444 kb
Host smart-9fa26b70-b9a7-4194-a60f-6daa2f982263
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206490410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.206490410
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1508703677
Short name T261
Test name
Test status
Simulation time 15823700 ps
CPU time 13.78 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 262556 kb
Host smart-759f62b6-67e2-421d-aeee-a99535ca8b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508703677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
508703677
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1881956614
Short name T250
Test name
Test status
Simulation time 33739500 ps
CPU time 13.4 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 264072 kb
Host smart-d234cb5a-04e7-4f99-9ee0-8a56a7a8874d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881956614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1881956614
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2297819228
Short name T1216
Test name
Test status
Simulation time 15443100 ps
CPU time 13.2 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 262536 kb
Host smart-19cdee23-dc39-4dd8-87f6-ecdbe2445c03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297819228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2297819228
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3629075889
Short name T1124
Test name
Test status
Simulation time 39103800 ps
CPU time 17.74 seconds
Started May 21 02:39:03 PM PDT 24
Finished May 21 02:39:56 PM PDT 24
Peak memory 260620 kb
Host smart-5604c4cf-5b97-4f77-ba20-dfc002144e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629075889 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3629075889
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3052235699
Short name T1157
Test name
Test status
Simulation time 13340900 ps
CPU time 12.93 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 260512 kb
Host smart-e418a614-b49e-4028-b559-25e40db9f3ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052235699 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3052235699
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4283983977
Short name T1109
Test name
Test status
Simulation time 15286300 ps
CPU time 15.59 seconds
Started May 21 02:39:01 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260340 kb
Host smart-2ee2dfbb-624a-4756-b3d8-cec00373a505
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283983977 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.4283983977
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1618855997
Short name T1169
Test name
Test status
Simulation time 35630800 ps
CPU time 15.79 seconds
Started May 21 02:38:54 PM PDT 24
Finished May 21 02:39:48 PM PDT 24
Peak memory 264224 kb
Host smart-86dcc118-6c6a-4ad3-85f9-a1f170a7c754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618855997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
618855997
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.570038867
Short name T343
Test name
Test status
Simulation time 1374016200 ps
CPU time 451.86 seconds
Started May 21 02:38:58 PM PDT 24
Finished May 21 02:47:08 PM PDT 24
Peak memory 264152 kb
Host smart-3f3ad101-2f10-4116-938e-0fdd959840df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570038867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
tl_intg_err.570038867
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.444231410
Short name T1119
Test name
Test status
Simulation time 90310700 ps
CPU time 13.23 seconds
Started May 21 02:39:34 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 262496 kb
Host smart-1dc5dd4d-befd-4132-afc6-f52fc10ca8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444231410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.444231410
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.949483541
Short name T1209
Test name
Test status
Simulation time 45056000 ps
CPU time 13.2 seconds
Started May 21 02:41:06 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 262616 kb
Host smart-402d0935-85fc-4634-99c5-b644b2e5fe89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949483541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.949483541
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2681535382
Short name T1134
Test name
Test status
Simulation time 16585300 ps
CPU time 13.2 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 262800 kb
Host smart-b505599c-1c55-44ac-aa89-774c0be315a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681535382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
2681535382
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.115349100
Short name T1155
Test name
Test status
Simulation time 27616500 ps
CPU time 13.2 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:41:35 PM PDT 24
Peak memory 262604 kb
Host smart-e56d997a-922e-4933-a3b8-51208885a51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115349100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.115349100
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3761119874
Short name T311
Test name
Test status
Simulation time 23648600 ps
CPU time 13.56 seconds
Started May 21 02:39:35 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262896 kb
Host smart-f7241298-1396-4aa6-830f-cd86adcd8a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761119874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3761119874
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3557327365
Short name T1121
Test name
Test status
Simulation time 20994600 ps
CPU time 13.35 seconds
Started May 21 02:39:35 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262644 kb
Host smart-d07a1731-2e47-4c9e-8c24-5a02fbfa9a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557327365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3557327365
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1763199132
Short name T340
Test name
Test status
Simulation time 32010800 ps
CPU time 13.41 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 262900 kb
Host smart-4aa354de-f754-4782-b5cd-338faaa87c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763199132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1763199132
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.422978441
Short name T1220
Test name
Test status
Simulation time 27743800 ps
CPU time 13.25 seconds
Started May 21 02:39:36 PM PDT 24
Finished May 21 02:40:10 PM PDT 24
Peak memory 262804 kb
Host smart-5c101947-2006-49d6-8afd-648a38614475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422978441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.422978441
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.66240539
Short name T1182
Test name
Test status
Simulation time 26965000 ps
CPU time 13.49 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:40:16 PM PDT 24
Peak memory 261828 kb
Host smart-67b27230-f943-450e-9505-8ae04b42045d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66240539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.66240539
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3087843514
Short name T1146
Test name
Test status
Simulation time 19171500 ps
CPU time 13.38 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:15 PM PDT 24
Peak memory 262800 kb
Host smart-4e8b31a9-f0cc-4589-a1c9-362cc245fc2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087843514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3087843514
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2303050930
Short name T1172
Test name
Test status
Simulation time 80431600 ps
CPU time 18.95 seconds
Started May 21 02:41:45 PM PDT 24
Finished May 21 02:42:07 PM PDT 24
Peak memory 272384 kb
Host smart-4d19a736-2e6a-406a-8d18-6efecf8a3914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303050930 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2303050930
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1426967151
Short name T1140
Test name
Test status
Simulation time 116601400 ps
CPU time 16.27 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:55 PM PDT 24
Peak memory 260508 kb
Host smart-e9f2bfa0-3b2a-48ea-913a-55550e7d211b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426967151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1426967151
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.216909152
Short name T317
Test name
Test status
Simulation time 17544600 ps
CPU time 13.31 seconds
Started May 21 02:39:00 PM PDT 24
Finished May 21 02:39:51 PM PDT 24
Peak memory 262600 kb
Host smart-769a4a0e-08f7-412e-94ac-3230399c8a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216909152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.216909152
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.899863472
Short name T1117
Test name
Test status
Simulation time 82519200 ps
CPU time 33.67 seconds
Started May 21 02:39:00 PM PDT 24
Finished May 21 02:40:11 PM PDT 24
Peak memory 263656 kb
Host smart-92f48dc3-f670-4b1b-b720-07c1a035587d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899863472 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.899863472
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.431737338
Short name T1198
Test name
Test status
Simulation time 14928600 ps
CPU time 15.31 seconds
Started May 21 02:39:01 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260552 kb
Host smart-8bb03a43-932c-4df6-a791-07278b6c9298
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431737338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.431737338
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.749228399
Short name T1225
Test name
Test status
Simulation time 23423700 ps
CPU time 15.46 seconds
Started May 21 02:39:00 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260464 kb
Host smart-72bca246-756a-4bc2-967e-9d6278636b28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749228399 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.749228399
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3148093735
Short name T240
Test name
Test status
Simulation time 84445400 ps
CPU time 15.65 seconds
Started May 21 02:39:00 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 264184 kb
Host smart-615ba6a2-839f-42a4-81d7-294c7c11a53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148093735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3
148093735
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2417135477
Short name T1167
Test name
Test status
Simulation time 889650400 ps
CPU time 744.87 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:52:03 PM PDT 24
Peak memory 262032 kb
Host smart-ba2560d5-1cae-48f0-8ffc-4ade2f05c7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417135477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2417135477
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3721062697
Short name T1148
Test name
Test status
Simulation time 37039100 ps
CPU time 18.88 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:57 PM PDT 24
Peak memory 271436 kb
Host smart-c7ad14ab-3760-4562-95bb-08391d5e9925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721062697 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3721062697
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3841753368
Short name T1176
Test name
Test status
Simulation time 38541100 ps
CPU time 14.3 seconds
Started May 21 02:39:26 PM PDT 24
Finished May 21 02:40:05 PM PDT 24
Peak memory 260504 kb
Host smart-4fe8ed26-e71b-4b50-a530-874e05772d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841753368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3841753368
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4118492348
Short name T1236
Test name
Test status
Simulation time 190233500 ps
CPU time 13.25 seconds
Started May 21 02:39:01 PM PDT 24
Finished May 21 02:39:51 PM PDT 24
Peak memory 262548 kb
Host smart-72c69803-9aad-42f3-b551-a0f33491cbef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118492348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.4
118492348
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.34985822
Short name T1245
Test name
Test status
Simulation time 291572100 ps
CPU time 20.44 seconds
Started May 21 02:41:04 PM PDT 24
Finished May 21 02:41:39 PM PDT 24
Peak memory 260556 kb
Host smart-0759de95-a46b-4b57-bc7f-681ffbbe0901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34985822 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.34985822
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2444172412
Short name T1136
Test name
Test status
Simulation time 44167200 ps
CPU time 15.42 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:54 PM PDT 24
Peak memory 260340 kb
Host smart-28349e68-946c-4459-8719-2de02383f9b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444172412 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2444172412
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3216608789
Short name T1123
Test name
Test status
Simulation time 11650100 ps
CPU time 15.19 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260524 kb
Host smart-ccf492b0-0d55-4d44-80f6-9b08c6847288
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216608789 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3216608789
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1661555461
Short name T243
Test name
Test status
Simulation time 201613700 ps
CPU time 18.33 seconds
Started May 21 02:41:00 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 264192 kb
Host smart-da835bca-961a-400e-91c3-9c79777900c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661555461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
661555461
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4177503081
Short name T350
Test name
Test status
Simulation time 694912000 ps
CPU time 448.97 seconds
Started May 21 02:39:01 PM PDT 24
Finished May 21 02:47:07 PM PDT 24
Peak memory 264196 kb
Host smart-03876d3d-6fd5-40a1-9941-bda967a77a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177503081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.4177503081
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4064620324
Short name T300
Test name
Test status
Simulation time 117777300 ps
CPU time 18.53 seconds
Started May 21 02:39:09 PM PDT 24
Finished May 21 02:40:01 PM PDT 24
Peak memory 272396 kb
Host smart-5e673d49-7485-45ff-8e07-7ff1218ad812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064620324 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.4064620324
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3546883231
Short name T299
Test name
Test status
Simulation time 136944900 ps
CPU time 14.48 seconds
Started May 21 02:41:01 PM PDT 24
Finished May 21 02:41:31 PM PDT 24
Peak memory 260516 kb
Host smart-be2ac8c8-1053-4a3c-85b5-4e8fecd83c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546883231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.3546883231
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3381711441
Short name T1183
Test name
Test status
Simulation time 57785000 ps
CPU time 13.36 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:52 PM PDT 24
Peak memory 261808 kb
Host smart-b111668c-ff53-4f65-898e-5e1ab85eb720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381711441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
381711441
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1355558178
Short name T1195
Test name
Test status
Simulation time 117267800 ps
CPU time 28.51 seconds
Started May 21 02:39:07 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 260456 kb
Host smart-5d41f5c0-baec-4617-a803-7690b3919f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355558178 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1355558178
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.443287186
Short name T1244
Test name
Test status
Simulation time 25108600 ps
CPU time 15.52 seconds
Started May 21 02:39:01 PM PDT 24
Finished May 21 02:39:53 PM PDT 24
Peak memory 260512 kb
Host smart-1968e2da-5e7b-4082-9331-b7574e25e283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443287186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.443287186
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4236274821
Short name T1179
Test name
Test status
Simulation time 94291700 ps
CPU time 13 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:51 PM PDT 24
Peak memory 260528 kb
Host smart-80abb9ad-d585-4937-a94f-8fab5d895c9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236274821 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.4236274821
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2819175902
Short name T264
Test name
Test status
Simulation time 111417100 ps
CPU time 18.56 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:39:57 PM PDT 24
Peak memory 264204 kb
Host smart-9262be29-e5ea-427b-adf4-1c10feaec9ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819175902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
819175902
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1636069014
Short name T348
Test name
Test status
Simulation time 379871300 ps
CPU time 449.76 seconds
Started May 21 02:39:02 PM PDT 24
Finished May 21 02:47:08 PM PDT 24
Peak memory 264224 kb
Host smart-383e91a9-a098-4273-8a0b-18b840794c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636069014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1636069014
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1684333450
Short name T1165
Test name
Test status
Simulation time 39107300 ps
CPU time 14.79 seconds
Started May 21 02:39:06 PM PDT 24
Finished May 21 02:39:56 PM PDT 24
Peak memory 264168 kb
Host smart-a3216747-c722-4965-87a7-145ecf4df20d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684333450 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1684333450
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.537138362
Short name T1218
Test name
Test status
Simulation time 67193300 ps
CPU time 17.22 seconds
Started May 21 02:39:37 PM PDT 24
Finished May 21 02:40:15 PM PDT 24
Peak memory 260528 kb
Host smart-9852ea51-23e1-40a6-a33a-a6b938406f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537138362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_csr_rw.537138362
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1703665745
Short name T341
Test name
Test status
Simulation time 22005000 ps
CPU time 13.44 seconds
Started May 21 02:39:07 PM PDT 24
Finished May 21 02:39:55 PM PDT 24
Peak memory 262528 kb
Host smart-91c10647-2340-4ea0-b5e5-b6c865d867e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703665745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1
703665745
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2129238614
Short name T1122
Test name
Test status
Simulation time 68534600 ps
CPU time 34.63 seconds
Started May 21 02:39:07 PM PDT 24
Finished May 21 02:40:16 PM PDT 24
Peak memory 262180 kb
Host smart-11b90921-c7fc-4149-a37a-4e012e6ac5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129238614 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2129238614
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2006673117
Short name T1151
Test name
Test status
Simulation time 82958600 ps
CPU time 13.1 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:41:31 PM PDT 24
Peak memory 260540 kb
Host smart-187315b2-9d7d-4684-b2a1-efee89c98600
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006673117 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2006673117
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1501212607
Short name T1132
Test name
Test status
Simulation time 14507600 ps
CPU time 15.69 seconds
Started May 21 02:39:06 PM PDT 24
Finished May 21 02:39:57 PM PDT 24
Peak memory 260296 kb
Host smart-eb9072ad-7168-4a31-9f45-b72b45745cb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501212607 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1501212607
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3434674523
Short name T269
Test name
Test status
Simulation time 127646700 ps
CPU time 16.01 seconds
Started May 21 02:39:08 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 264232 kb
Host smart-5ae13166-a5ce-4fee-9061-f0c5a8cf721f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434674523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
434674523
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2728689385
Short name T1227
Test name
Test status
Simulation time 1290453600 ps
CPU time 881.16 seconds
Started May 21 02:39:08 PM PDT 24
Finished May 21 02:54:23 PM PDT 24
Peak memory 261788 kb
Host smart-d2f08b47-dad6-4e78-a779-c1b771fee150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728689385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2728689385
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1408237709
Short name T296
Test name
Test status
Simulation time 586949000 ps
CPU time 14.51 seconds
Started May 21 02:39:09 PM PDT 24
Finished May 21 02:39:57 PM PDT 24
Peak memory 261424 kb
Host smart-83e62d6a-ca6a-4062-89e6-5c4855af2a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408237709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1408237709
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4140661168
Short name T1152
Test name
Test status
Simulation time 72279400 ps
CPU time 13.3 seconds
Started May 21 02:39:09 PM PDT 24
Finished May 21 02:39:56 PM PDT 24
Peak memory 262572 kb
Host smart-b282ca7a-9901-4979-a726-61e316ce4142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140661168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.4
140661168
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1888051141
Short name T1194
Test name
Test status
Simulation time 173320500 ps
CPU time 18.06 seconds
Started May 21 02:39:08 PM PDT 24
Finished May 21 02:40:00 PM PDT 24
Peak memory 260676 kb
Host smart-cfaab0b9-eea9-4c32-8bd9-15c4ecbb032b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888051141 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.1888051141
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2474531533
Short name T1158
Test name
Test status
Simulation time 14706300 ps
CPU time 12.95 seconds
Started May 21 02:39:06 PM PDT 24
Finished May 21 02:39:54 PM PDT 24
Peak memory 260428 kb
Host smart-0f42d4b6-2582-4704-bc0a-0526bde77a28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474531533 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2474531533
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1557462584
Short name T1229
Test name
Test status
Simulation time 22692300 ps
CPU time 15.57 seconds
Started May 21 02:39:09 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 260516 kb
Host smart-185e0786-8599-4437-b76a-a1534b5acfff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557462584 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1557462584
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2004313594
Short name T194
Test name
Test status
Simulation time 74848600 ps
CPU time 16.78 seconds
Started May 21 02:39:08 PM PDT 24
Finished May 21 02:39:58 PM PDT 24
Peak memory 264192 kb
Host smart-31d54336-c1b6-45bd-bf16-819274053a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004313594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
004313594
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.767673009
Short name T8
Test name
Test status
Simulation time 13906700 ps
CPU time 13.77 seconds
Started May 21 03:12:55 PM PDT 24
Finished May 21 03:13:09 PM PDT 24
Peak memory 265320 kb
Host smart-34f5016d-9858-4260-a20c-998d66c15c46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767673009 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.767673009
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3946985741
Short name T945
Test name
Test status
Simulation time 183496900 ps
CPU time 14.13 seconds
Started May 21 03:13:11 PM PDT 24
Finished May 21 03:13:26 PM PDT 24
Peak memory 264664 kb
Host smart-ca98b52b-da0b-4636-bc09-c3124d81b764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946985741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
946985741
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.4169810868
Short name T226
Test name
Test status
Simulation time 14325800 ps
CPU time 15.61 seconds
Started May 21 03:12:52 PM PDT 24
Finished May 21 03:13:08 PM PDT 24
Peak memory 275612 kb
Host smart-62d9518b-ced6-42be-855a-ce9ccf857069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169810868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.4169810868
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.3016114175
Short name T393
Test name
Test status
Simulation time 117898500 ps
CPU time 103.38 seconds
Started May 21 03:12:34 PM PDT 24
Finished May 21 03:14:18 PM PDT 24
Peak memory 272500 kb
Host smart-3326c3f5-6319-4326-ab3d-e51b983d18c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016114175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.3016114175
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1884876051
Short name T178
Test name
Test status
Simulation time 758447600 ps
CPU time 981.86 seconds
Started May 21 03:12:06 PM PDT 24
Finished May 21 03:28:28 PM PDT 24
Peak memory 273300 kb
Host smart-82b2432c-4a22-487b-a561-6e1640f881b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884876051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1884876051
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2515013836
Short name T46
Test name
Test status
Simulation time 232591200 ps
CPU time 22.22 seconds
Started May 21 03:12:12 PM PDT 24
Finished May 21 03:12:35 PM PDT 24
Peak memory 265252 kb
Host smart-c6a1155e-f55c-471e-b413-b59bf78f1ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515013836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2515013836
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.2830260640
Short name T181
Test name
Test status
Simulation time 710159100 ps
CPU time 45.52 seconds
Started May 21 03:12:55 PM PDT 24
Finished May 21 03:13:42 PM PDT 24
Peak memory 265212 kb
Host smart-3d0bcddf-ea71-40b6-a07e-b27edabc2d9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830260640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.2830260640
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1645642827
Short name T157
Test name
Test status
Simulation time 253266749500 ps
CPU time 2301.62 seconds
Started May 21 03:12:07 PM PDT 24
Finished May 21 03:50:30 PM PDT 24
Peak memory 265296 kb
Host smart-7624ff13-7f6e-4998-a619-48d5eacbe4dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645642827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1645642827
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2815686424
Short name T931
Test name
Test status
Simulation time 10033366800 ps
CPU time 104.33 seconds
Started May 21 03:13:04 PM PDT 24
Finished May 21 03:14:50 PM PDT 24
Peak memory 274120 kb
Host smart-c6393710-f79b-40f2-9445-3c84af3c7f6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815686424 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2815686424
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3709716606
Short name T932
Test name
Test status
Simulation time 260263653500 ps
CPU time 942.6 seconds
Started May 21 03:12:02 PM PDT 24
Finished May 21 03:27:45 PM PDT 24
Peak memory 264280 kb
Host smart-c22f2bdf-bc15-4c8d-8394-eddb79aa4ae5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709716606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3709716606
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2859952055
Short name T456
Test name
Test status
Simulation time 3181848000 ps
CPU time 218.03 seconds
Started May 21 03:12:14 PM PDT 24
Finished May 21 03:15:53 PM PDT 24
Peak memory 262644 kb
Host smart-97afa6f7-03a5-4237-946d-7d40df032396
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859952055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2859952055
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.2552064648
Short name T528
Test name
Test status
Simulation time 1504876900 ps
CPU time 192.25 seconds
Started May 21 03:12:37 PM PDT 24
Finished May 21 03:15:50 PM PDT 24
Peak memory 289920 kb
Host smart-54dfefba-d1b3-4aa8-9799-9ef0855bdbaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552064648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.2552064648
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.530736646
Short name T936
Test name
Test status
Simulation time 12782247700 ps
CPU time 289.99 seconds
Started May 21 03:12:37 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 284364 kb
Host smart-0111c62c-18e1-4bdf-a7b0-adfcd4519f36
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530736646 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.530736646
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.573438165
Short name T796
Test name
Test status
Simulation time 4643913400 ps
CPU time 72.63 seconds
Started May 21 03:12:38 PM PDT 24
Finished May 21 03:13:51 PM PDT 24
Peak memory 260232 kb
Host smart-993a462a-b9fb-40d2-ad5e-8c6d9bc0da2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573438165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_intr_wr.573438165
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.525254076
Short name T683
Test name
Test status
Simulation time 37866647700 ps
CPU time 194.92 seconds
Started May 21 03:12:37 PM PDT 24
Finished May 21 03:15:53 PM PDT 24
Peak memory 259720 kb
Host smart-bde88174-2766-44d1-a419-8e02b556ba7e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525
254076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.525254076
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.4036362058
Short name T685
Test name
Test status
Simulation time 8912284200 ps
CPU time 113.11 seconds
Started May 21 03:12:12 PM PDT 24
Finished May 21 03:14:06 PM PDT 24
Peak memory 260692 kb
Host smart-c5083965-03ad-44af-bf10-e051bd4f0194
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036362058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4036362058
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.406736923
Short name T118
Test name
Test status
Simulation time 3801588400 ps
CPU time 70.84 seconds
Started May 21 03:12:13 PM PDT 24
Finished May 21 03:13:25 PM PDT 24
Peak memory 259760 kb
Host smart-e0b4c55e-2ca0-4eb4-b6b6-0c48a92d6dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406736923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.406736923
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1610524273
Short name T78
Test name
Test status
Simulation time 49591937700 ps
CPU time 318.76 seconds
Started May 21 03:12:07 PM PDT 24
Finished May 21 03:17:27 PM PDT 24
Peak memory 273648 kb
Host smart-ecb6ef0a-bb6b-410d-b0cb-8bcd4e3c6a02
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610524273 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1610524273
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1341209627
Short name T899
Test name
Test status
Simulation time 36293500 ps
CPU time 131.12 seconds
Started May 21 03:12:02 PM PDT 24
Finished May 21 03:14:14 PM PDT 24
Peak memory 259888 kb
Host smart-c762d0f5-7f2a-4e8a-bc7a-c671ac0a1cf3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341209627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1341209627
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.1441483136
Short name T1008
Test name
Test status
Simulation time 5096112000 ps
CPU time 237.19 seconds
Started May 21 03:12:33 PM PDT 24
Finished May 21 03:16:31 PM PDT 24
Peak memory 294736 kb
Host smart-11dd7bd4-fa4e-47d4-a2b2-44636ec860ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441483136 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.1441483136
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4195082914
Short name T55
Test name
Test status
Simulation time 43625600 ps
CPU time 14.04 seconds
Started May 21 03:13:00 PM PDT 24
Finished May 21 03:13:15 PM PDT 24
Peak memory 276680 kb
Host smart-f5b707fa-93fc-42e9-b602-00528e84475e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4195082914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4195082914
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.2598413343
Short name T1092
Test name
Test status
Simulation time 53769962700 ps
CPU time 709.39 seconds
Started May 21 03:12:00 PM PDT 24
Finished May 21 03:23:51 PM PDT 24
Peak memory 261664 kb
Host smart-74ffaf6d-f539-46ff-89ec-6ecf3f246d9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598413343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2598413343
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.338273091
Short name T603
Test name
Test status
Simulation time 45191200 ps
CPU time 13.62 seconds
Started May 21 03:12:43 PM PDT 24
Finished May 21 03:12:57 PM PDT 24
Peak memory 264700 kb
Host smart-83e58aff-7103-425e-82e4-3b15c0f10bc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338273091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_rese
t.338273091
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.705139360
Short name T419
Test name
Test status
Simulation time 2266934900 ps
CPU time 1323.56 seconds
Started May 21 03:11:52 PM PDT 24
Finished May 21 03:33:56 PM PDT 24
Peak memory 287912 kb
Host smart-749871f6-b6f9-4311-b569-e08ba5146d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705139360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.705139360
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.869022537
Short name T903
Test name
Test status
Simulation time 208421400 ps
CPU time 100.68 seconds
Started May 21 03:12:01 PM PDT 24
Finished May 21 03:13:43 PM PDT 24
Peak memory 265228 kb
Host smart-e21e6e0d-5b6a-411e-9b75-4b6deff2111a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=869022537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.869022537
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.189348107
Short name T1095
Test name
Test status
Simulation time 235049100 ps
CPU time 32.19 seconds
Started May 21 03:12:49 PM PDT 24
Finished May 21 03:13:22 PM PDT 24
Peak memory 274572 kb
Host smart-1e18d966-dea0-4ab1-a6c8-850e1e64ac98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189348107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rd_intg.189348107
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1011164817
Short name T275
Test name
Test status
Simulation time 243611800 ps
CPU time 49.49 seconds
Started May 21 03:13:06 PM PDT 24
Finished May 21 03:13:56 PM PDT 24
Peak memory 274624 kb
Host smart-b0fecbd7-c553-4c09-9edf-5af80a86dfe4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011164817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1011164817
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2333494073
Short name T648
Test name
Test status
Simulation time 271549200 ps
CPU time 38.02 seconds
Started May 21 03:12:42 PM PDT 24
Finished May 21 03:13:21 PM PDT 24
Peak memory 273564 kb
Host smart-c947b995-3ff2-400b-96c0-40b1bf87f088
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333494073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2333494073
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3256859847
Short name T412
Test name
Test status
Simulation time 23763600 ps
CPU time 13.91 seconds
Started May 21 03:12:13 PM PDT 24
Finished May 21 03:12:27 PM PDT 24
Peak memory 265092 kb
Host smart-a26795fc-db1e-4360-b45e-245e7bf935cb
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3256859847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3256859847
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.617423394
Short name T604
Test name
Test status
Simulation time 33637900 ps
CPU time 21.82 seconds
Started May 21 03:12:35 PM PDT 24
Finished May 21 03:12:57 PM PDT 24
Peak memory 265228 kb
Host smart-8758a8fb-1cfb-4e6a-92ef-cb313d0ff327
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617423394 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.617423394
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2385456981
Short name T649
Test name
Test status
Simulation time 651569600 ps
CPU time 149.6 seconds
Started May 21 03:12:11 PM PDT 24
Finished May 21 03:14:42 PM PDT 24
Peak memory 281724 kb
Host smart-3684dc71-ab9c-4cf7-b815-db9f5ec9c5bc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385456981 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.2385456981
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.1521647990
Short name T223
Test name
Test status
Simulation time 2476859100 ps
CPU time 158.95 seconds
Started May 21 03:12:25 PM PDT 24
Finished May 21 03:15:05 PM PDT 24
Peak memory 281740 kb
Host smart-1cfec1b6-e7c0-492d-aa45-eb91c84c58fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1521647990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1521647990
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3850320933
Short name T415
Test name
Test status
Simulation time 1311808900 ps
CPU time 165.91 seconds
Started May 21 03:12:22 PM PDT 24
Finished May 21 03:15:08 PM PDT 24
Peak memory 281800 kb
Host smart-6ba533c5-f999-417b-a804-3575c9cb5c8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850320933 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3850320933
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.4071419132
Short name T982
Test name
Test status
Simulation time 3815478200 ps
CPU time 599.78 seconds
Started May 21 03:12:14 PM PDT 24
Finished May 21 03:22:14 PM PDT 24
Peak memory 313516 kb
Host smart-3821fdde-adca-47d1-a066-3dd377fd1067
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071419132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.4071419132
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.3322895781
Short name T207
Test name
Test status
Simulation time 3954916500 ps
CPU time 654.33 seconds
Started May 21 03:12:34 PM PDT 24
Finished May 21 03:23:29 PM PDT 24
Peak memory 323672 kb
Host smart-86a0aed2-1735-4d0f-a316-50a284b2af6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322895781 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.3322895781
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3260821220
Short name T437
Test name
Test status
Simulation time 56369800 ps
CPU time 29.01 seconds
Started May 21 03:12:42 PM PDT 24
Finished May 21 03:13:11 PM PDT 24
Peak memory 267416 kb
Host smart-827080a3-0a68-496d-b759-037e59356278
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260821220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3260821220
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3789342041
Short name T324
Test name
Test status
Simulation time 26967800 ps
CPU time 31.71 seconds
Started May 21 03:12:43 PM PDT 24
Finished May 21 03:13:16 PM PDT 24
Peak memory 274816 kb
Host smart-92eccdb4-0650-480b-9d24-039bce390b09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789342041 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.3789342041
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.1409569989
Short name T16
Test name
Test status
Simulation time 1119384500 ps
CPU time 4910.09 seconds
Started May 21 03:12:44 PM PDT 24
Finished May 21 04:34:35 PM PDT 24
Peak memory 282328 kb
Host smart-4fe6a91a-3da3-4818-a363-5178cad72e7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409569989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1409569989
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3672155447
Short name T823
Test name
Test status
Simulation time 4720547500 ps
CPU time 74.66 seconds
Started May 21 03:12:44 PM PDT 24
Finished May 21 03:14:00 PM PDT 24
Peak memory 263200 kb
Host smart-5113c253-f825-40ef-b87c-c1a30e946e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672155447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3672155447
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.675306884
Short name T729
Test name
Test status
Simulation time 689741100 ps
CPU time 74.7 seconds
Started May 21 03:12:27 PM PDT 24
Finished May 21 03:13:42 PM PDT 24
Peak memory 265248 kb
Host smart-dba98ae1-ca6c-4798-895f-d35895f58f37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675306884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.675306884
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.2510379144
Short name T406
Test name
Test status
Simulation time 1173373000 ps
CPU time 125.57 seconds
Started May 21 03:12:37 PM PDT 24
Finished May 21 03:14:43 PM PDT 24
Peak memory 265312 kb
Host smart-68c1359b-862e-4041-a895-b70ad55e93e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510379144 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.2510379144
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.1966665315
Short name T40
Test name
Test status
Simulation time 40994100 ps
CPU time 122.03 seconds
Started May 21 03:11:44 PM PDT 24
Finished May 21 03:13:47 PM PDT 24
Peak memory 275704 kb
Host smart-0b85b69d-a481-490a-997e-ad100b737c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966665315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1966665315
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.893590838
Short name T640
Test name
Test status
Simulation time 71728100 ps
CPU time 23.7 seconds
Started May 21 03:11:55 PM PDT 24
Finished May 21 03:12:19 PM PDT 24
Peak memory 258972 kb
Host smart-f4af79b9-f6aa-4629-bab7-683585d67223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893590838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.893590838
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.4167464588
Short name T1104
Test name
Test status
Simulation time 263074700 ps
CPU time 1229.91 seconds
Started May 21 03:12:43 PM PDT 24
Finished May 21 03:33:14 PM PDT 24
Peak memory 287212 kb
Host smart-98bedc96-97d3-4415-a9a9-a6ff160a5b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167464588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.4167464588
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.343565200
Short name T481
Test name
Test status
Simulation time 19800900 ps
CPU time 26.49 seconds
Started May 21 03:11:50 PM PDT 24
Finished May 21 03:12:17 PM PDT 24
Peak memory 261880 kb
Host smart-dec18b5c-1445-4570-98c2-a1ab318be6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343565200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.343565200
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.504209759
Short name T716
Test name
Test status
Simulation time 77971000 ps
CPU time 15.55 seconds
Started May 21 03:12:13 PM PDT 24
Finished May 21 03:12:29 PM PDT 24
Peak memory 265232 kb
Host smart-08917697-c05b-4aed-b7bd-3a32719e0d26
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=504209759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee
p.504209759
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3908630367
Short name T188
Test name
Test status
Simulation time 39185600 ps
CPU time 13.47 seconds
Started May 21 03:14:14 PM PDT 24
Finished May 21 03:14:30 PM PDT 24
Peak memory 265196 kb
Host smart-2d23b5fd-ad63-4c1d-aaf4-20217d22c51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908630367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
908630367
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1756890122
Short name T820
Test name
Test status
Simulation time 53711300 ps
CPU time 14.21 seconds
Started May 21 03:14:04 PM PDT 24
Finished May 21 03:14:20 PM PDT 24
Peak memory 275576 kb
Host smart-15bd2227-3510-4893-a4c9-6706eeeecca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756890122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1756890122
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3058343267
Short name T944
Test name
Test status
Simulation time 121869600 ps
CPU time 105.16 seconds
Started May 21 03:14:21 PM PDT 24
Finished May 21 03:16:07 PM PDT 24
Peak memory 280888 kb
Host smart-c8138d43-ddbb-4e2c-9e0e-538f8dcd87b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058343267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3058343267
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1088491076
Short name T1063
Test name
Test status
Simulation time 1112388300 ps
CPU time 293.82 seconds
Started May 21 03:13:25 PM PDT 24
Finished May 21 03:18:20 PM PDT 24
Peak memory 261400 kb
Host smart-57072399-cf22-43fe-93f6-2887580b9936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088491076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1088491076
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.1910976181
Short name T601
Test name
Test status
Simulation time 8922441200 ps
CPU time 2492.91 seconds
Started May 21 03:13:35 PM PDT 24
Finished May 21 03:55:09 PM PDT 24
Peak memory 262660 kb
Host smart-5ea938e4-d9ca-4328-9aae-c0bb58627760
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910976181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.1910976181
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.892251454
Short name T182
Test name
Test status
Simulation time 753859000 ps
CPU time 1962.28 seconds
Started May 21 03:13:43 PM PDT 24
Finished May 21 03:46:26 PM PDT 24
Peak memory 264216 kb
Host smart-571fbbf1-3cf3-4a32-a9c7-b4252c852be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892251454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.892251454
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2009507096
Short name T230
Test name
Test status
Simulation time 442187200 ps
CPU time 917.46 seconds
Started May 21 03:13:38 PM PDT 24
Finished May 21 03:28:57 PM PDT 24
Peak memory 270324 kb
Host smart-b57f1f61-acc6-4a6f-80da-890343c6d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009507096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2009507096
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1391082446
Short name T51
Test name
Test status
Simulation time 216891300 ps
CPU time 22.71 seconds
Started May 21 03:13:30 PM PDT 24
Finished May 21 03:13:53 PM PDT 24
Peak memory 265208 kb
Host smart-d9e735f8-e228-4e48-8938-2159fca813cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391082446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1391082446
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.2925584249
Short name T103
Test name
Test status
Simulation time 583064128600 ps
CPU time 3273.81 seconds
Started May 21 03:13:29 PM PDT 24
Finished May 21 04:08:03 PM PDT 24
Peak memory 265280 kb
Host smart-ae0e1767-d738-47d5-8040-74438b6cc4a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925584249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.2925584249
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.986274382
Short name T924
Test name
Test status
Simulation time 531411200 ps
CPU time 123.6 seconds
Started May 21 03:13:21 PM PDT 24
Finished May 21 03:15:26 PM PDT 24
Peak memory 262592 kb
Host smart-abc1bf93-8c43-4c8a-94c0-2bc2d659ab90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986274382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.986274382
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3549545999
Short name T1012
Test name
Test status
Simulation time 48556100 ps
CPU time 13.21 seconds
Started May 21 03:14:13 PM PDT 24
Finished May 21 03:14:28 PM PDT 24
Peak memory 265184 kb
Host smart-de3ee91b-9ca7-4992-a9e2-10a3d2c8bc7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549545999 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3549545999
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1722772951
Short name T727
Test name
Test status
Simulation time 91110138700 ps
CPU time 1931.05 seconds
Started May 21 03:13:24 PM PDT 24
Finished May 21 03:45:36 PM PDT 24
Peak memory 264012 kb
Host smart-7008c333-e74c-443c-a37b-cbab5f6d94b4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722772951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1722772951
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2135371894
Short name T988
Test name
Test status
Simulation time 60137049000 ps
CPU time 849.1 seconds
Started May 21 03:13:33 PM PDT 24
Finished May 21 03:27:43 PM PDT 24
Peak memory 263420 kb
Host smart-4d5d3c32-e00c-43f9-bddd-ae0e93b6e3da
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135371894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2135371894
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.891960301
Short name T964
Test name
Test status
Simulation time 5957706400 ps
CPU time 235.73 seconds
Started May 21 03:13:17 PM PDT 24
Finished May 21 03:17:13 PM PDT 24
Peak memory 262548 kb
Host smart-955eff30-80c1-4bcd-85c5-84f845409cf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891960301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.891960301
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.3781170445
Short name T254
Test name
Test status
Simulation time 16357328600 ps
CPU time 541.95 seconds
Started May 21 03:13:57 PM PDT 24
Finished May 21 03:23:01 PM PDT 24
Peak memory 334660 kb
Host smart-1c126d80-32e6-40c5-b922-fb129db5a518
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781170445 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.3781170445
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.114127507
Short name T725
Test name
Test status
Simulation time 2485983800 ps
CPU time 194.39 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:17:13 PM PDT 24
Peak memory 289936 kb
Host smart-98e80ed1-357f-4048-8785-ec797efce30c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114127507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_intr_rd.114127507
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.706531028
Short name T916
Test name
Test status
Simulation time 53606110200 ps
CPU time 296.69 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:18:55 PM PDT 24
Peak memory 284796 kb
Host smart-a4ca44e5-77e1-4599-8a81-7305d9570666
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706531028 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.706531028
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.4078211166
Short name T1074
Test name
Test status
Simulation time 3197510800 ps
CPU time 68.27 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:15:07 PM PDT 24
Peak memory 265268 kb
Host smart-16facd8a-58d9-421f-8174-3a8ef8a8cd28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078211166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.4078211166
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1132643236
Short name T494
Test name
Test status
Simulation time 8785682900 ps
CPU time 96.28 seconds
Started May 21 03:13:34 PM PDT 24
Finished May 21 03:15:11 PM PDT 24
Peak memory 259708 kb
Host smart-0761d1ef-3c04-4b7b-b1ab-86361d295ff2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132643236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1132643236
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1562667391
Short name T879
Test name
Test status
Simulation time 62453000 ps
CPU time 13.58 seconds
Started May 21 03:14:24 PM PDT 24
Finished May 21 03:14:39 PM PDT 24
Peak memory 265184 kb
Host smart-c2121f8f-aa00-4787-a644-915afc22adcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562667391 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1562667391
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.975330695
Short name T1049
Test name
Test status
Simulation time 2791082500 ps
CPU time 70.63 seconds
Started May 21 03:13:42 PM PDT 24
Finished May 21 03:14:54 PM PDT 24
Peak memory 259772 kb
Host smart-48a40b81-b73e-47dd-9425-b66ef34b1186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975330695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.975330695
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3256349611
Short name T622
Test name
Test status
Simulation time 1732271300 ps
CPU time 255.68 seconds
Started May 21 03:13:51 PM PDT 24
Finished May 21 03:18:07 PM PDT 24
Peak memory 295624 kb
Host smart-3fbef74f-5ea6-42f1-9787-eded395ca271
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256349611 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3256349611
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3429359325
Short name T60
Test name
Test status
Simulation time 53940800 ps
CPU time 14.16 seconds
Started May 21 03:14:02 PM PDT 24
Finished May 21 03:14:18 PM PDT 24
Peak memory 276932 kb
Host smart-9254d98e-86c5-4b12-8818-11d85f050176
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3429359325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3429359325
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3030373617
Short name T480
Test name
Test status
Simulation time 77458500 ps
CPU time 150.7 seconds
Started May 21 03:13:17 PM PDT 24
Finished May 21 03:15:48 PM PDT 24
Peak memory 261536 kb
Host smart-4bb05d8a-cbf9-4feb-9d09-cc9e592856aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030373617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3030373617
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3316468941
Short name T233
Test name
Test status
Simulation time 24771000 ps
CPU time 13.76 seconds
Started May 21 03:14:04 PM PDT 24
Finished May 21 03:14:19 PM PDT 24
Peak memory 265384 kb
Host smart-33e5e9a3-e0df-472d-a75b-7256a82b6c13
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316468941 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3316468941
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.944734300
Short name T457
Test name
Test status
Simulation time 67986500 ps
CPU time 13.2 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:14:12 PM PDT 24
Peak memory 265248 kb
Host smart-5475d47b-4ad3-4555-b7ba-fb2b18ce671f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944734300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_rese
t.944734300
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3475734317
Short name T112
Test name
Test status
Simulation time 386925000 ps
CPU time 1546.08 seconds
Started May 21 03:13:12 PM PDT 24
Finished May 21 03:38:59 PM PDT 24
Peak memory 287796 kb
Host smart-4bd605d4-2827-449c-b7c4-c0e2a26d63ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475734317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3475734317
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2768874657
Short name T830
Test name
Test status
Simulation time 77236400 ps
CPU time 98.94 seconds
Started May 21 03:13:22 PM PDT 24
Finished May 21 03:15:02 PM PDT 24
Peak memory 265140 kb
Host smart-8bdb622d-deb9-49bd-9b39-5ea55775578e
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768874657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2768874657
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2783151122
Short name T277
Test name
Test status
Simulation time 215819600 ps
CPU time 31.49 seconds
Started May 21 03:14:21 PM PDT 24
Finished May 21 03:14:54 PM PDT 24
Peak memory 276216 kb
Host smart-8005ce4d-47bf-4334-83e9-522dfdaac2df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783151122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2783151122
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3929112801
Short name T957
Test name
Test status
Simulation time 88350900 ps
CPU time 32.4 seconds
Started May 21 03:13:57 PM PDT 24
Finished May 21 03:14:32 PM PDT 24
Peak memory 273596 kb
Host smart-0bcbeec4-4f75-43f0-b2ec-46cda925e73c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929112801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3929112801
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1744541926
Short name T451
Test name
Test status
Simulation time 33048600 ps
CPU time 22.6 seconds
Started May 21 03:13:49 PM PDT 24
Finished May 21 03:14:12 PM PDT 24
Peak memory 265264 kb
Host smart-97356180-d963-4dac-bc3d-30c2b5fa5742
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744541926 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1744541926
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3500293803
Short name T574
Test name
Test status
Simulation time 23359800 ps
CPU time 21.48 seconds
Started May 21 03:13:39 PM PDT 24
Finished May 21 03:14:01 PM PDT 24
Peak memory 264476 kb
Host smart-8a16cc75-373f-46f0-9596-de18a3c60f9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500293803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.3500293803
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.3054113917
Short name T159
Test name
Test status
Simulation time 79899886100 ps
CPU time 883.43 seconds
Started May 21 03:14:15 PM PDT 24
Finished May 21 03:29:00 PM PDT 24
Peak memory 259352 kb
Host smart-1800e9d1-8271-42dc-b6d5-52b81d109bf1
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054113917 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.3054113917
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3699580187
Short name T552
Test name
Test status
Simulation time 1308017000 ps
CPU time 145.25 seconds
Started May 21 03:14:14 PM PDT 24
Finished May 21 03:16:40 PM PDT 24
Peak memory 281868 kb
Host smart-45b831a7-8ff8-473a-b963-6826083ddedb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699580187 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.3699580187
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.3743120445
Short name T813
Test name
Test status
Simulation time 809273200 ps
CPU time 170.38 seconds
Started May 21 03:13:51 PM PDT 24
Finished May 21 03:16:42 PM PDT 24
Peak memory 281756 kb
Host smart-eb0ab2b3-1810-418a-936e-c43cd3501b7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3743120445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3743120445
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2049351216
Short name T773
Test name
Test status
Simulation time 1397437100 ps
CPU time 141.98 seconds
Started May 21 03:13:46 PM PDT 24
Finished May 21 03:16:09 PM PDT 24
Peak memory 289940 kb
Host smart-b16f311f-ffc9-497e-b167-10171683ba7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049351216 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2049351216
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2404227435
Short name T914
Test name
Test status
Simulation time 4465841800 ps
CPU time 680.51 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:25:19 PM PDT 24
Peak memory 309564 kb
Host smart-c3acf423-1b67-48bf-95c8-8ad00386ade5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404227435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2404227435
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.4069875865
Short name T620
Test name
Test status
Simulation time 14978319100 ps
CPU time 673.66 seconds
Started May 21 03:13:52 PM PDT 24
Finished May 21 03:25:06 PM PDT 24
Peak memory 336124 kb
Host smart-8213a8e8-dccf-42e1-b75e-4a7ab8553a02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069875865 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.4069875865
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3057803526
Short name T329
Test name
Test status
Simulation time 95248100 ps
CPU time 28.98 seconds
Started May 21 03:13:57 PM PDT 24
Finished May 21 03:14:28 PM PDT 24
Peak memory 275624 kb
Host smart-e81278de-212e-4c7e-ab12-1036d57dc916
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057803526 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3057803526
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2280058953
Short name T983
Test name
Test status
Simulation time 563112300 ps
CPU time 62.22 seconds
Started May 21 03:13:56 PM PDT 24
Finished May 21 03:15:00 PM PDT 24
Peak memory 263312 kb
Host smart-5d5beeee-c0bb-4cbe-82a7-d056aa967623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280058953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2280058953
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2652772890
Short name T938
Test name
Test status
Simulation time 1451865300 ps
CPU time 79.81 seconds
Started May 21 03:13:47 PM PDT 24
Finished May 21 03:15:08 PM PDT 24
Peak memory 273532 kb
Host smart-63f0350e-0c66-4dba-a662-fc1be6525fdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652772890 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2652772890
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.77860503
Short name T1082
Test name
Test status
Simulation time 2989463000 ps
CPU time 90.29 seconds
Started May 21 03:13:46 PM PDT 24
Finished May 21 03:15:18 PM PDT 24
Peak memory 273616 kb
Host smart-48dd1f4b-4074-4715-a2c4-1f0f58fbae12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77860503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_counter.77860503
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3154721639
Short name T826
Test name
Test status
Simulation time 103038600 ps
CPU time 72 seconds
Started May 21 03:13:33 PM PDT 24
Finished May 21 03:14:46 PM PDT 24
Peak memory 274960 kb
Host smart-eb005432-802d-4a2a-988a-5f18ad84ce59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154721639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3154721639
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.729058257
Short name T525
Test name
Test status
Simulation time 25938700 ps
CPU time 23.45 seconds
Started May 21 03:13:12 PM PDT 24
Finished May 21 03:13:36 PM PDT 24
Peak memory 258984 kb
Host smart-72d51ec1-e6d5-40d1-961f-634726325478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729058257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.729058257
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2498509524
Short name T891
Test name
Test status
Simulation time 87856300 ps
CPU time 27.36 seconds
Started May 21 03:13:12 PM PDT 24
Finished May 21 03:13:40 PM PDT 24
Peak memory 261440 kb
Host smart-700fab79-cedf-46a0-9758-98a16534bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498509524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2498509524
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.284064409
Short name T728
Test name
Test status
Simulation time 7396100800 ps
CPU time 122.37 seconds
Started May 21 03:13:44 PM PDT 24
Finished May 21 03:15:48 PM PDT 24
Peak memory 265216 kb
Host smart-32384f97-bf0b-4b1e-91a8-c43ca419ca11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284064409 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_wo.284064409
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3919191891
Short name T7
Test name
Test status
Simulation time 44356500 ps
CPU time 15.13 seconds
Started May 21 03:14:02 PM PDT 24
Finished May 21 03:14:19 PM PDT 24
Peak memory 264776 kb
Host smart-524f528a-52d1-43d9-a9f4-288b923cb389
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919191891 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3919191891
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.694003486
Short name T702
Test name
Test status
Simulation time 130175700 ps
CPU time 13.67 seconds
Started May 21 03:20:30 PM PDT 24
Finished May 21 03:20:45 PM PDT 24
Peak memory 265176 kb
Host smart-e5bb6088-b3dd-461e-859c-d2e8df83af6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694003486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.694003486
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.2173911570
Short name T546
Test name
Test status
Simulation time 161596600 ps
CPU time 15.43 seconds
Started May 21 03:20:30 PM PDT 24
Finished May 21 03:20:47 PM PDT 24
Peak memory 275884 kb
Host smart-377c198a-568f-437d-bfd9-3af224e7c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173911570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2173911570
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.1998721606
Short name T361
Test name
Test status
Simulation time 27535600 ps
CPU time 22.44 seconds
Started May 21 03:20:30 PM PDT 24
Finished May 21 03:20:54 PM PDT 24
Peak memory 265228 kb
Host smart-9dd4e736-370f-4edf-afcb-7e6d9ac56662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998721606 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.1998721606
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.172222465
Short name T542
Test name
Test status
Simulation time 10012036000 ps
CPU time 126.9 seconds
Started May 21 03:20:30 PM PDT 24
Finished May 21 03:22:39 PM PDT 24
Peak memory 304044 kb
Host smart-e999118d-2a9d-40b9-bb9f-6f7ee0930903
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172222465 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.172222465
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1232663651
Short name T545
Test name
Test status
Simulation time 40124135400 ps
CPU time 897.42 seconds
Started May 21 03:20:14 PM PDT 24
Finished May 21 03:35:12 PM PDT 24
Peak memory 263860 kb
Host smart-a2e4db09-33e6-43c6-a7d1-a3c36d87c8c1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232663651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.1232663651
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2249007843
Short name T955
Test name
Test status
Simulation time 12420349900 ps
CPU time 244.6 seconds
Started May 21 03:20:19 PM PDT 24
Finished May 21 03:24:24 PM PDT 24
Peak memory 289924 kb
Host smart-41295322-05e3-47a7-9d5f-94f7b52a1bb0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249007843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2249007843
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.396819004
Short name T657
Test name
Test status
Simulation time 5952602500 ps
CPU time 147.61 seconds
Started May 21 03:20:17 PM PDT 24
Finished May 21 03:22:45 PM PDT 24
Peak memory 291980 kb
Host smart-8fd1d392-c806-4dca-a095-f92f02140230
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396819004 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.396819004
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.1681550568
Short name T337
Test name
Test status
Simulation time 6761442800 ps
CPU time 64.04 seconds
Started May 21 03:20:22 PM PDT 24
Finished May 21 03:21:27 PM PDT 24
Peak memory 262800 kb
Host smart-3d4ee5c3-0e21-43cc-b47d-e3cfc75cd177
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681550568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1
681550568
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2192827637
Short name T1041
Test name
Test status
Simulation time 15635300 ps
CPU time 13.8 seconds
Started May 21 03:20:28 PM PDT 24
Finished May 21 03:20:43 PM PDT 24
Peak memory 265188 kb
Host smart-6f9a63bf-7957-400e-b85e-47983d37daee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192827637 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2192827637
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.869448323
Short name T737
Test name
Test status
Simulation time 65181824200 ps
CPU time 255.36 seconds
Started May 21 03:20:18 PM PDT 24
Finished May 21 03:24:34 PM PDT 24
Peak memory 262732 kb
Host smart-f9bf62fe-b430-4741-96ae-b13b082afa58
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869448323 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_mp_regions.869448323
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2766613788
Short name T762
Test name
Test status
Simulation time 42707100 ps
CPU time 112.59 seconds
Started May 21 03:20:21 PM PDT 24
Finished May 21 03:22:14 PM PDT 24
Peak memory 259984 kb
Host smart-219d2cb5-1fc4-42af-ba21-716d12b601ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766613788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2766613788
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.689517485
Short name T89
Test name
Test status
Simulation time 2823581400 ps
CPU time 580.6 seconds
Started May 21 03:20:12 PM PDT 24
Finished May 21 03:29:53 PM PDT 24
Peak memory 262584 kb
Host smart-c961d61e-2fe6-415f-9ba0-034f58aaecba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689517485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.689517485
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2711753411
Short name T379
Test name
Test status
Simulation time 21870800 ps
CPU time 13.5 seconds
Started May 21 03:20:23 PM PDT 24
Finished May 21 03:20:37 PM PDT 24
Peak memory 265184 kb
Host smart-ed12f0fe-fa31-45af-aa14-508f68c6deec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711753411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2711753411
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.744638813
Short name T822
Test name
Test status
Simulation time 221199000 ps
CPU time 34.4 seconds
Started May 21 03:20:30 PM PDT 24
Finished May 21 03:21:06 PM PDT 24
Peak memory 273540 kb
Host smart-c3337d69-1ada-4637-b00b-0e0ef373d170
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744638813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_re_evict.744638813
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1149809988
Short name T476
Test name
Test status
Simulation time 559680600 ps
CPU time 138.18 seconds
Started May 21 03:20:18 PM PDT 24
Finished May 21 03:22:37 PM PDT 24
Peak memory 280980 kb
Host smart-355e6b06-0469-4c86-9fdf-e3d09230c612
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149809988 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.1149809988
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2715733137
Short name T206
Test name
Test status
Simulation time 9380976500 ps
CPU time 499.44 seconds
Started May 21 03:20:16 PM PDT 24
Finished May 21 03:28:36 PM PDT 24
Peak memory 309768 kb
Host smart-40357385-8940-49d0-9263-406c3bcb74b9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715733137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.2715733137
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2586006888
Short name T514
Test name
Test status
Simulation time 28156700 ps
CPU time 32.26 seconds
Started May 21 03:20:24 PM PDT 24
Finished May 21 03:20:57 PM PDT 24
Peak memory 273576 kb
Host smart-93c354ad-39aa-4d10-b000-9244e6a9f0fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586006888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2586006888
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3574750813
Short name T877
Test name
Test status
Simulation time 103144000 ps
CPU time 31.85 seconds
Started May 21 03:20:28 PM PDT 24
Finished May 21 03:21:01 PM PDT 24
Peak memory 269652 kb
Host smart-1980de54-816c-46fd-971d-8643dee90dfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574750813 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3574750813
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.4087650535
Short name T848
Test name
Test status
Simulation time 1251806600 ps
CPU time 51.99 seconds
Started May 21 03:20:29 PM PDT 24
Finished May 21 03:21:23 PM PDT 24
Peak memory 262192 kb
Host smart-4fc4f088-d7aa-4ecd-99b6-ad896a9dca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087650535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.4087650535
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.2246732922
Short name T487
Test name
Test status
Simulation time 71355800 ps
CPU time 52.05 seconds
Started May 21 03:20:20 PM PDT 24
Finished May 21 03:21:12 PM PDT 24
Peak memory 270736 kb
Host smart-17b28560-376a-4212-b52b-8c6ce6017f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246732922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2246732922
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.3486932727
Short name T595
Test name
Test status
Simulation time 7988402900 ps
CPU time 171.67 seconds
Started May 21 03:20:18 PM PDT 24
Finished May 21 03:23:10 PM PDT 24
Peak memory 265232 kb
Host smart-5b2be25f-620a-4f7f-a9ef-57be8e747369
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486932727 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.3486932727
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.462253788
Short name T634
Test name
Test status
Simulation time 72008300 ps
CPU time 14.09 seconds
Started May 21 03:20:55 PM PDT 24
Finished May 21 03:21:10 PM PDT 24
Peak memory 265168 kb
Host smart-9555b44e-6882-4ffe-a993-d084101b0bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462253788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.462253788
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.4137989603
Short name T1091
Test name
Test status
Simulation time 16028400 ps
CPU time 13.73 seconds
Started May 21 03:20:52 PM PDT 24
Finished May 21 03:21:06 PM PDT 24
Peak memory 276084 kb
Host smart-ccd28717-e60a-4128-9bb0-b5a7d8b323c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137989603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.4137989603
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2909991783
Short name T923
Test name
Test status
Simulation time 10105843300 ps
CPU time 36.88 seconds
Started May 21 03:20:53 PM PDT 24
Finished May 21 03:21:30 PM PDT 24
Peak memory 265304 kb
Host smart-1513f1f3-671c-43d2-95b4-1ae5afb7b83d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909991783 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2909991783
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1575704493
Short name T1100
Test name
Test status
Simulation time 15301200 ps
CPU time 13.47 seconds
Started May 21 03:20:55 PM PDT 24
Finished May 21 03:21:10 PM PDT 24
Peak memory 265352 kb
Host smart-25f9ebd5-158c-4cbf-8802-ef200d73d391
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575704493 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1575704493
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3763744968
Short name T170
Test name
Test status
Simulation time 80135820600 ps
CPU time 839.9 seconds
Started May 21 03:20:35 PM PDT 24
Finished May 21 03:34:37 PM PDT 24
Peak memory 263908 kb
Host smart-0ca0c10d-c896-4905-9722-2f56c3f29542
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763744968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3763744968
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1362608290
Short name T897
Test name
Test status
Simulation time 1824036100 ps
CPU time 79.33 seconds
Started May 21 03:20:35 PM PDT 24
Finished May 21 03:21:56 PM PDT 24
Peak memory 262504 kb
Host smart-bd4dfb05-0b3a-42c2-ace2-aae69161717b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362608290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1362608290
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.4256184809
Short name T767
Test name
Test status
Simulation time 6160949900 ps
CPU time 71.92 seconds
Started May 21 03:20:41 PM PDT 24
Finished May 21 03:21:54 PM PDT 24
Peak memory 260536 kb
Host smart-7e675538-bd12-42eb-8526-4510ec603f01
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256184809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.4
256184809
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3662822778
Short name T1084
Test name
Test status
Simulation time 15555200 ps
CPU time 13.6 seconds
Started May 21 03:20:52 PM PDT 24
Finished May 21 03:21:06 PM PDT 24
Peak memory 264400 kb
Host smart-15afa3f7-9c17-4fd9-bcdc-f39e56404ce4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662822778 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3662822778
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1157052185
Short name T536
Test name
Test status
Simulation time 3611929200 ps
CPU time 198.91 seconds
Started May 21 03:20:35 PM PDT 24
Finished May 21 03:23:55 PM PDT 24
Peak memory 262716 kb
Host smart-37ea6360-022e-41c3-8c64-dfb2de56239c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157052185 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.1157052185
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.2112177383
Short name T136
Test name
Test status
Simulation time 50657100 ps
CPU time 134.65 seconds
Started May 21 03:20:37 PM PDT 24
Finished May 21 03:22:53 PM PDT 24
Peak memory 259924 kb
Host smart-08fbfdc0-b777-4ac4-84b5-adc58dce34ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112177383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.2112177383
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2058838846
Short name T570
Test name
Test status
Simulation time 23481400 ps
CPU time 67.56 seconds
Started May 21 03:20:37 PM PDT 24
Finished May 21 03:21:46 PM PDT 24
Peak memory 262360 kb
Host smart-31c2b5f8-d326-4ebd-b23e-fb1721f144ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058838846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2058838846
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3748790834
Short name T576
Test name
Test status
Simulation time 20658092100 ps
CPU time 191.94 seconds
Started May 21 03:20:48 PM PDT 24
Finished May 21 03:24:01 PM PDT 24
Peak memory 264676 kb
Host smart-7a943fe2-33ec-4b6c-a179-9f7832468816
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748790834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.3748790834
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.3851037890
Short name T690
Test name
Test status
Simulation time 1627421400 ps
CPU time 416.98 seconds
Started May 21 03:20:37 PM PDT 24
Finished May 21 03:27:35 PM PDT 24
Peak memory 282624 kb
Host smart-d8c58b15-e6cb-4033-8a8d-a8a65495431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851037890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3851037890
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.62518956
Short name T840
Test name
Test status
Simulation time 375124500 ps
CPU time 36.55 seconds
Started May 21 03:20:53 PM PDT 24
Finished May 21 03:21:30 PM PDT 24
Peak memory 273584 kb
Host smart-0f0f1d9a-d5fb-4df5-ba97-4685ef8b3b59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62518956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas
h_ctrl_re_evict.62518956
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.921262705
Short name T1065
Test name
Test status
Simulation time 503913800 ps
CPU time 140.91 seconds
Started May 21 03:20:42 PM PDT 24
Finished May 21 03:23:03 PM PDT 24
Peak memory 281604 kb
Host smart-57839ec4-46f8-407f-a737-051c536f3ad1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921262705 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.921262705
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2318598056
Short name T975
Test name
Test status
Simulation time 11509993500 ps
CPU time 590.9 seconds
Started May 21 03:20:42 PM PDT 24
Finished May 21 03:30:33 PM PDT 24
Peak memory 314536 kb
Host smart-5e4573c5-af0c-4af8-9429-8cc8056d1274
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318598056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2318598056
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.1856474690
Short name T331
Test name
Test status
Simulation time 26774800 ps
CPU time 29.22 seconds
Started May 21 03:20:53 PM PDT 24
Finished May 21 03:21:23 PM PDT 24
Peak memory 267412 kb
Host smart-463efb9c-7d38-4328-bc5a-cd199b22fed9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856474690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.1856474690
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1816842006
Short name T669
Test name
Test status
Simulation time 78045200 ps
CPU time 31.76 seconds
Started May 21 03:20:56 PM PDT 24
Finished May 21 03:21:28 PM PDT 24
Peak memory 269308 kb
Host smart-57fd2a1a-25e8-44ea-9b97-247d9de86c14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816842006 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1816842006
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.419227709
Short name T1094
Test name
Test status
Simulation time 31881300 ps
CPU time 96.71 seconds
Started May 21 03:20:37 PM PDT 24
Finished May 21 03:22:15 PM PDT 24
Peak memory 275544 kb
Host smart-c7c851e8-c60c-47b9-952c-2a0a4833529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419227709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.419227709
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.1602698789
Short name T991
Test name
Test status
Simulation time 9718607700 ps
CPU time 190.29 seconds
Started May 21 03:20:40 PM PDT 24
Finished May 21 03:23:51 PM PDT 24
Peak memory 265184 kb
Host smart-11acf020-4e24-42ab-ba61-d4d73fc65693
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602698789 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.1602698789
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.19349286
Short name T420
Test name
Test status
Simulation time 403287900 ps
CPU time 13.97 seconds
Started May 21 03:21:16 PM PDT 24
Finished May 21 03:21:31 PM PDT 24
Peak memory 265216 kb
Host smart-d3c9ad4f-036b-452d-954c-0f6e41b86afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.19349286
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.3948926615
Short name T985
Test name
Test status
Simulation time 26674900 ps
CPU time 15.45 seconds
Started May 21 03:21:17 PM PDT 24
Finished May 21 03:21:33 PM PDT 24
Peak memory 275532 kb
Host smart-514f1926-5461-46f4-a622-ea9c08258458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948926615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3948926615
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.2907527740
Short name T128
Test name
Test status
Simulation time 13748800 ps
CPU time 21.84 seconds
Started May 21 03:21:16 PM PDT 24
Finished May 21 03:21:39 PM PDT 24
Peak memory 265376 kb
Host smart-3fa28f1c-e9d6-483e-872f-8ddbcc62b6ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907527740 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.2907527740
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2582172505
Short name T616
Test name
Test status
Simulation time 10036058100 ps
CPU time 55.79 seconds
Started May 21 03:21:17 PM PDT 24
Finished May 21 03:22:13 PM PDT 24
Peak memory 286404 kb
Host smart-35dc876c-ca35-49cc-91cb-03277800d02b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582172505 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2582172505
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1307723952
Short name T958
Test name
Test status
Simulation time 30558800 ps
CPU time 13.34 seconds
Started May 21 03:21:16 PM PDT 24
Finished May 21 03:21:31 PM PDT 24
Peak memory 265260 kb
Host smart-cd4f6fa6-5a1c-43d7-b483-2671a616db68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307723952 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1307723952
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3285310602
Short name T167
Test name
Test status
Simulation time 160195467200 ps
CPU time 911.82 seconds
Started May 21 03:21:00 PM PDT 24
Finished May 21 03:36:12 PM PDT 24
Peak memory 263928 kb
Host smart-3b49ff33-cec4-41f1-aea0-2977e4fccde1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285310602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3285310602
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.215183002
Short name T304
Test name
Test status
Simulation time 10143435900 ps
CPU time 228.99 seconds
Started May 21 03:21:00 PM PDT 24
Finished May 21 03:24:49 PM PDT 24
Peak memory 262580 kb
Host smart-3b6755a8-94e6-4a26-ab54-0310fb5b1f41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215183002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.215183002
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1086276275
Short name T322
Test name
Test status
Simulation time 3971340800 ps
CPU time 220.16 seconds
Started May 21 03:21:10 PM PDT 24
Finished May 21 03:24:51 PM PDT 24
Peak memory 289872 kb
Host smart-8dcbc4a7-3bec-447b-abac-b13b76272b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086276275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1086276275
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.784591574
Short name T815
Test name
Test status
Simulation time 5710592900 ps
CPU time 124.23 seconds
Started May 21 03:21:08 PM PDT 24
Finished May 21 03:23:13 PM PDT 24
Peak memory 292092 kb
Host smart-04f130be-56b3-43ec-822c-f3610b3ba588
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784591574 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.784591574
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.1287328394
Short name T904
Test name
Test status
Simulation time 7969835600 ps
CPU time 73.27 seconds
Started May 21 03:21:05 PM PDT 24
Finished May 21 03:22:19 PM PDT 24
Peak memory 260636 kb
Host smart-72570e7e-949a-4f46-98e1-3a13f3ec8081
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287328394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1
287328394
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.792541700
Short name T133
Test name
Test status
Simulation time 47299500 ps
CPU time 13.35 seconds
Started May 21 03:21:17 PM PDT 24
Finished May 21 03:21:31 PM PDT 24
Peak memory 265196 kb
Host smart-d5f46e3a-40bb-467d-9781-a8c30d25d0cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792541700 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.792541700
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1724300312
Short name T1034
Test name
Test status
Simulation time 40313000 ps
CPU time 134.47 seconds
Started May 21 03:21:06 PM PDT 24
Finished May 21 03:23:21 PM PDT 24
Peak memory 260068 kb
Host smart-e553a2e7-7c91-4a8e-aec8-7900c767ed22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724300312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1724300312
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.3677382906
Short name T65
Test name
Test status
Simulation time 4015089600 ps
CPU time 382.51 seconds
Started May 21 03:20:58 PM PDT 24
Finished May 21 03:27:21 PM PDT 24
Peak memory 261680 kb
Host smart-52162a26-8f9a-49fb-9670-0ec3f725d4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677382906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3677382906
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.2103129715
Short name T375
Test name
Test status
Simulation time 47477000 ps
CPU time 13.51 seconds
Started May 21 03:21:09 PM PDT 24
Finished May 21 03:21:23 PM PDT 24
Peak memory 258732 kb
Host smart-6b71441b-56df-4cc6-be03-227026718000
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103129715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.2103129715
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.4110767828
Short name T940
Test name
Test status
Simulation time 405202000 ps
CPU time 975.59 seconds
Started May 21 03:20:57 PM PDT 24
Finished May 21 03:37:14 PM PDT 24
Peak memory 283456 kb
Host smart-5d7ae626-b782-4924-8307-f1dfb0fe2a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110767828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.4110767828
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.61483065
Short name T1080
Test name
Test status
Simulation time 371871400 ps
CPU time 33.57 seconds
Started May 21 03:21:09 PM PDT 24
Finished May 21 03:21:43 PM PDT 24
Peak memory 274640 kb
Host smart-11758bd3-e20d-4c23-893f-f409c5225020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61483065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_re_evict.61483065
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.4195528924
Short name T855
Test name
Test status
Simulation time 1103306900 ps
CPU time 111.41 seconds
Started May 21 03:21:09 PM PDT 24
Finished May 21 03:23:01 PM PDT 24
Peak memory 281680 kb
Host smart-0b5a9a7b-f0a3-40f2-a7f7-94515650c614
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195528924 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.4195528924
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3512081518
Short name T852
Test name
Test status
Simulation time 7101807000 ps
CPU time 530.22 seconds
Started May 21 03:21:09 PM PDT 24
Finished May 21 03:30:00 PM PDT 24
Peak memory 313988 kb
Host smart-7fb8a3e9-a779-43fc-9323-f2254ac15963
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512081518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.3512081518
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2089632726
Short name T994
Test name
Test status
Simulation time 43370100 ps
CPU time 29.89 seconds
Started May 21 03:21:11 PM PDT 24
Finished May 21 03:21:41 PM PDT 24
Peak memory 275652 kb
Host smart-9159d017-ac30-404b-8809-16af505ac8ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089632726 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2089632726
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2402526413
Short name T888
Test name
Test status
Simulation time 94077800 ps
CPU time 73.73 seconds
Started May 21 03:20:59 PM PDT 24
Finished May 21 03:22:13 PM PDT 24
Peak memory 276140 kb
Host smart-84898170-2802-4458-b1a8-3e2f342d585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402526413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2402526413
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3661277718
Short name T793
Test name
Test status
Simulation time 4096990100 ps
CPU time 167.2 seconds
Started May 21 03:21:10 PM PDT 24
Finished May 21 03:23:58 PM PDT 24
Peak memory 265196 kb
Host smart-fca4fc0f-ff48-42f0-ace3-a091beb3f77e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661277718 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.3661277718
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2161174548
Short name T629
Test name
Test status
Simulation time 103383600 ps
CPU time 14.17 seconds
Started May 21 03:21:38 PM PDT 24
Finished May 21 03:21:53 PM PDT 24
Peak memory 264252 kb
Host smart-44a71364-aba3-41c2-bb72-4c017f53cc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161174548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2161174548
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3731096296
Short name T108
Test name
Test status
Simulation time 13342200 ps
CPU time 15.7 seconds
Started May 21 03:21:32 PM PDT 24
Finished May 21 03:21:48 PM PDT 24
Peak memory 275128 kb
Host smart-82383cd1-8700-413f-9ecc-df64f2ce7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731096296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3731096296
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.2618721548
Short name T1086
Test name
Test status
Simulation time 47395000 ps
CPU time 22.96 seconds
Started May 21 03:21:26 PM PDT 24
Finished May 21 03:21:49 PM PDT 24
Peak memory 265240 kb
Host smart-65f64b57-f03e-44f3-9832-7200e2fcb390
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618721548 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.2618721548
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3515941688
Short name T175
Test name
Test status
Simulation time 10019057900 ps
CPU time 94.74 seconds
Started May 21 03:21:35 PM PDT 24
Finished May 21 03:23:11 PM PDT 24
Peak memory 330760 kb
Host smart-d6f44027-df48-4da3-afa2-a21b0a014eed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515941688 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3515941688
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3565332322
Short name T588
Test name
Test status
Simulation time 26211400 ps
CPU time 13.56 seconds
Started May 21 03:21:34 PM PDT 24
Finished May 21 03:21:48 PM PDT 24
Peak memory 265160 kb
Host smart-0c369e0c-59c9-40fc-af2b-cc354e0e63f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565332322 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3565332322
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.231658844
Short name T142
Test name
Test status
Simulation time 180197126600 ps
CPU time 983.46 seconds
Started May 21 03:21:30 PM PDT 24
Finished May 21 03:37:54 PM PDT 24
Peak memory 263228 kb
Host smart-b35215a9-df6d-4765-9511-125ba1008f50
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231658844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.231658844
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.880188311
Short name T1047
Test name
Test status
Simulation time 3071876700 ps
CPU time 66.89 seconds
Started May 21 03:21:20 PM PDT 24
Finished May 21 03:22:27 PM PDT 24
Peak memory 262516 kb
Host smart-131df7ee-5af4-461c-8cc5-1aa3b99ae672
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880188311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h
w_sec_otp.880188311
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3215691785
Short name T887
Test name
Test status
Simulation time 1066239500 ps
CPU time 152.87 seconds
Started May 21 03:21:28 PM PDT 24
Finished May 21 03:24:02 PM PDT 24
Peak memory 293472 kb
Host smart-9627bf05-60bb-4d6a-8c31-8b9a1d5212bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215691785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3215691785
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1892168059
Short name T999
Test name
Test status
Simulation time 7267310400 ps
CPU time 186.21 seconds
Started May 21 03:21:24 PM PDT 24
Finished May 21 03:24:31 PM PDT 24
Peak memory 292412 kb
Host smart-36e86821-3f98-4675-931b-3c2558463658
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892168059 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.1892168059
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.1792540960
Short name T501
Test name
Test status
Simulation time 3910549100 ps
CPU time 67.2 seconds
Started May 21 03:21:27 PM PDT 24
Finished May 21 03:22:36 PM PDT 24
Peak memory 259980 kb
Host smart-8e5c020d-eef9-41df-9dfa-22be156a019d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792540960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1
792540960
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3915639006
Short name T930
Test name
Test status
Simulation time 15930800 ps
CPU time 13.46 seconds
Started May 21 03:21:29 PM PDT 24
Finished May 21 03:21:44 PM PDT 24
Peak memory 265196 kb
Host smart-5ac5bf21-e400-4db7-af90-a11d99aae6b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915639006 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3915639006
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.1390157105
Short name T102
Test name
Test status
Simulation time 23450368600 ps
CPU time 595.74 seconds
Started May 21 03:21:20 PM PDT 24
Finished May 21 03:31:17 PM PDT 24
Peak memory 274492 kb
Host smart-b3477c20-e61d-485c-84ad-436cfb196ff0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390157105 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.1390157105
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.1193296912
Short name T709
Test name
Test status
Simulation time 81155900 ps
CPU time 131.08 seconds
Started May 21 03:21:30 PM PDT 24
Finished May 21 03:23:42 PM PDT 24
Peak memory 261208 kb
Host smart-e6885892-5027-48cd-be4a-74aa1511fbea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193296912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.1193296912
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.4208825909
Short name T872
Test name
Test status
Simulation time 111933400 ps
CPU time 69.27 seconds
Started May 21 03:21:22 PM PDT 24
Finished May 21 03:22:32 PM PDT 24
Peak memory 261796 kb
Host smart-25ae6029-ae9a-4cc5-b992-8d6b60987c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208825909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.4208825909
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.632346358
Short name T881
Test name
Test status
Simulation time 20833900 ps
CPU time 13.32 seconds
Started May 21 03:21:21 PM PDT 24
Finished May 21 03:21:35 PM PDT 24
Peak memory 265184 kb
Host smart-470105a5-6654-45b0-bbca-2268cb9ca277
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632346358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_res
et.632346358
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1906866610
Short name T959
Test name
Test status
Simulation time 147715400 ps
CPU time 144.55 seconds
Started May 21 03:21:22 PM PDT 24
Finished May 21 03:23:47 PM PDT 24
Peak memory 268772 kb
Host smart-90610c24-9717-417e-92f3-47aabc3874a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906866610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1906866610
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3337418566
Short name T718
Test name
Test status
Simulation time 245090200 ps
CPU time 40.09 seconds
Started May 21 03:21:30 PM PDT 24
Finished May 21 03:22:11 PM PDT 24
Peak memory 273572 kb
Host smart-bd935af2-bf5c-4a3b-b59d-29af2f574068
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337418566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3337418566
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.370599524
Short name T986
Test name
Test status
Simulation time 1881204100 ps
CPU time 130.63 seconds
Started May 21 03:21:29 PM PDT 24
Finished May 21 03:23:41 PM PDT 24
Peak memory 281708 kb
Host smart-3bf143a4-e50b-4676-9f88-94adba202875
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370599524 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.flash_ctrl_ro.370599524
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3620873669
Short name T871
Test name
Test status
Simulation time 5061268900 ps
CPU time 651.13 seconds
Started May 21 03:21:21 PM PDT 24
Finished May 21 03:32:13 PM PDT 24
Peak memory 314464 kb
Host smart-ca84622c-c75a-4a66-bb10-431d9ec55dd3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620873669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.3620873669
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.2668780089
Short name T582
Test name
Test status
Simulation time 50960400 ps
CPU time 32.12 seconds
Started May 21 03:21:29 PM PDT 24
Finished May 21 03:22:02 PM PDT 24
Peak memory 267424 kb
Host smart-f56c56b9-a2ff-4692-b8bc-a89dd5cb59dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668780089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.2668780089
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4038267883
Short name T984
Test name
Test status
Simulation time 38434200 ps
CPU time 31.46 seconds
Started May 21 03:21:31 PM PDT 24
Finished May 21 03:22:03 PM PDT 24
Peak memory 274872 kb
Host smart-e69cd5ff-c0fd-4a15-b32a-a878d3112812
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038267883 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4038267883
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.630895428
Short name T896
Test name
Test status
Simulation time 61002500 ps
CPU time 146.06 seconds
Started May 21 03:21:20 PM PDT 24
Finished May 21 03:23:47 PM PDT 24
Peak memory 278728 kb
Host smart-338d20f5-fc9e-48c5-9eeb-0d03340f68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630895428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.630895428
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3537066109
Short name T706
Test name
Test status
Simulation time 1683848400 ps
CPU time 147.5 seconds
Started May 21 03:21:22 PM PDT 24
Finished May 21 03:23:51 PM PDT 24
Peak memory 259524 kb
Host smart-abc65027-5ff4-4467-b358-ebe86aa52e77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537066109 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.3537066109
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.1667167196
Short name T768
Test name
Test status
Simulation time 83978700 ps
CPU time 14.13 seconds
Started May 21 03:21:49 PM PDT 24
Finished May 21 03:22:04 PM PDT 24
Peak memory 265248 kb
Host smart-b010f528-4369-440e-8af8-a5672bb2ada0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667167196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
1667167196
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.769744140
Short name T739
Test name
Test status
Simulation time 15604900 ps
CPU time 13.38 seconds
Started May 21 03:21:52 PM PDT 24
Finished May 21 03:22:06 PM PDT 24
Peak memory 275700 kb
Host smart-54f81fff-655b-4220-aec2-3c58dab20585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769744140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.769744140
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1789891089
Short name T751
Test name
Test status
Simulation time 13821000 ps
CPU time 22.45 seconds
Started May 21 03:21:56 PM PDT 24
Finished May 21 03:22:20 PM PDT 24
Peak memory 265300 kb
Host smart-3110be3f-6daf-4b85-9954-d0638096b492
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789891089 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1789891089
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1900878530
Short name T807
Test name
Test status
Simulation time 15500600 ps
CPU time 13.72 seconds
Started May 21 03:21:52 PM PDT 24
Finished May 21 03:22:07 PM PDT 24
Peak memory 265192 kb
Host smart-d78f4ac4-89e5-4aa4-b8cc-f6cf4ce52000
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900878530 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1900878530
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3598507670
Short name T123
Test name
Test status
Simulation time 50127299500 ps
CPU time 914.65 seconds
Started May 21 03:21:38 PM PDT 24
Finished May 21 03:36:53 PM PDT 24
Peak memory 263292 kb
Host smart-8998320a-59db-4d81-be4f-163ff7b67d95
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598507670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.3598507670
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1398009909
Short name T1061
Test name
Test status
Simulation time 4794912300 ps
CPU time 79.81 seconds
Started May 21 03:21:39 PM PDT 24
Finished May 21 03:22:59 PM PDT 24
Peak memory 262596 kb
Host smart-748f763f-32a3-4edf-ad51-2c6e882827eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398009909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.1398009909
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.4026406284
Short name T659
Test name
Test status
Simulation time 1511270700 ps
CPU time 187.63 seconds
Started May 21 03:21:44 PM PDT 24
Finished May 21 03:24:53 PM PDT 24
Peak memory 289916 kb
Host smart-c7816ff2-e5ec-4aff-9fed-a3771dffb7e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026406284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.4026406284
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4272600697
Short name T320
Test name
Test status
Simulation time 31425150400 ps
CPU time 297.68 seconds
Started May 21 03:21:46 PM PDT 24
Finished May 21 03:26:45 PM PDT 24
Peak memory 284352 kb
Host smart-b35a1b99-539e-4431-89a5-032b87ee78be
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272600697 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.4272600697
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.2579242272
Short name T2
Test name
Test status
Simulation time 2132808300 ps
CPU time 70.18 seconds
Started May 21 03:21:45 PM PDT 24
Finished May 21 03:22:57 PM PDT 24
Peak memory 260760 kb
Host smart-d2ff98cb-62af-48b3-8dac-cb572a70c648
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579242272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2
579242272
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2011302943
Short name T515
Test name
Test status
Simulation time 69066000 ps
CPU time 13.58 seconds
Started May 21 03:21:52 PM PDT 24
Finished May 21 03:22:07 PM PDT 24
Peak memory 265224 kb
Host smart-560812c8-ea2c-4359-b0b4-f9b36a8163c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011302943 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2011302943
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1569281599
Short name T77
Test name
Test status
Simulation time 14900048800 ps
CPU time 377.71 seconds
Started May 21 03:21:44 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 275008 kb
Host smart-faed9382-b291-4ece-bc5e-465843bc8fe1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569281599 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1569281599
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.1365485525
Short name T138
Test name
Test status
Simulation time 199049500 ps
CPU time 110.43 seconds
Started May 21 03:21:45 PM PDT 24
Finished May 21 03:23:37 PM PDT 24
Peak memory 264364 kb
Host smart-9ba747dc-461c-4433-a5b0-9ab7ba777ecd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365485525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.1365485525
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.148178899
Short name T873
Test name
Test status
Simulation time 33419900 ps
CPU time 152.48 seconds
Started May 21 03:21:40 PM PDT 24
Finished May 21 03:24:13 PM PDT 24
Peak memory 261796 kb
Host smart-2a77928c-ba3e-4ee7-88c2-b4e0c26e55c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148178899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.148178899
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.4227515278
Short name T398
Test name
Test status
Simulation time 128639500 ps
CPU time 13.52 seconds
Started May 21 03:21:52 PM PDT 24
Finished May 21 03:22:06 PM PDT 24
Peak memory 265228 kb
Host smart-39ed845d-b7d2-42cf-9bb8-5f975d40ddf9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227515278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.4227515278
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.4202627948
Short name T630
Test name
Test status
Simulation time 162822800 ps
CPU time 432.54 seconds
Started May 21 03:21:39 PM PDT 24
Finished May 21 03:28:52 PM PDT 24
Peak memory 276844 kb
Host smart-9b7f7a95-152f-44d1-9990-66bdf7375393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202627948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.4202627948
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.1250452070
Short name T816
Test name
Test status
Simulation time 119141200 ps
CPU time 35.1 seconds
Started May 21 03:21:50 PM PDT 24
Finished May 21 03:22:26 PM PDT 24
Peak memory 274740 kb
Host smart-7e95c111-aedc-44f1-9ccf-003fa2d65172
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250452070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.1250452070
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.4216930225
Short name T126
Test name
Test status
Simulation time 14906895300 ps
CPU time 544.67 seconds
Started May 21 03:21:44 PM PDT 24
Finished May 21 03:30:49 PM PDT 24
Peak memory 313576 kb
Host smart-b0d5b7d0-e278-4751-acd3-bc1d65c4fda3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216930225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.4216930225
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.2657632559
Short name T1087
Test name
Test status
Simulation time 64485100 ps
CPU time 32.35 seconds
Started May 21 03:21:50 PM PDT 24
Finished May 21 03:22:23 PM PDT 24
Peak memory 274592 kb
Host smart-5ac45027-b2a9-4de6-83b9-10fda6c2f0d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657632559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.2657632559
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1352628171
Short name T93
Test name
Test status
Simulation time 71307900 ps
CPU time 31.38 seconds
Started May 21 03:21:56 PM PDT 24
Finished May 21 03:22:29 PM PDT 24
Peak memory 274820 kb
Host smart-80a48f2e-9720-4137-b378-27230caadef8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352628171 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1352628171
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.2528065812
Short name T866
Test name
Test status
Simulation time 2885087600 ps
CPU time 69.93 seconds
Started May 21 03:21:56 PM PDT 24
Finished May 21 03:23:08 PM PDT 24
Peak memory 262696 kb
Host smart-386a28c3-c138-4648-b499-dc3a73c94ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528065812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.2528065812
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.2148537392
Short name T710
Test name
Test status
Simulation time 117013500 ps
CPU time 119.74 seconds
Started May 21 03:21:39 PM PDT 24
Finished May 21 03:23:39 PM PDT 24
Peak memory 275996 kb
Host smart-8e6881e2-3498-4159-8695-457632731db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148537392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2148537392
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3205605396
Short name T84
Test name
Test status
Simulation time 1657517200 ps
CPU time 122.19 seconds
Started May 21 03:21:44 PM PDT 24
Finished May 21 03:23:47 PM PDT 24
Peak memory 265220 kb
Host smart-473a1a0a-82aa-4136-ba98-263b279bb9bc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205605396 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3205605396
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1985576151
Short name T187
Test name
Test status
Simulation time 104787600 ps
CPU time 13.75 seconds
Started May 21 03:22:15 PM PDT 24
Finished May 21 03:22:31 PM PDT 24
Peak memory 265180 kb
Host smart-6f5fc4d2-d07f-45e7-b20f-305a6611bb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985576151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1985576151
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.771862713
Short name T995
Test name
Test status
Simulation time 14936600 ps
CPU time 13.32 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:22:24 PM PDT 24
Peak memory 275680 kb
Host smart-489eea4a-21fa-4fda-b8be-c599787b3fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771862713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.771862713
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3736072758
Short name T581
Test name
Test status
Simulation time 10012840000 ps
CPU time 140.37 seconds
Started May 21 03:22:07 PM PDT 24
Finished May 21 03:24:31 PM PDT 24
Peak memory 373072 kb
Host smart-27508ecc-fdd7-4cfc-b841-559611e340a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736072758 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3736072758
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1114827645
Short name T129
Test name
Test status
Simulation time 25692300 ps
CPU time 13.51 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:22:24 PM PDT 24
Peak memory 265312 kb
Host smart-fe2609e7-13b1-4e8c-b49f-7924f65fcc4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114827645 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1114827645
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.4056854677
Short name T169
Test name
Test status
Simulation time 80151245000 ps
CPU time 974.81 seconds
Started May 21 03:21:58 PM PDT 24
Finished May 21 03:38:14 PM PDT 24
Peak memory 263548 kb
Host smart-527eba0a-03fe-4270-96d3-eb604e7bb94c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056854677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.4056854677
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1205821603
Short name T307
Test name
Test status
Simulation time 1531352600 ps
CPU time 71.89 seconds
Started May 21 03:21:56 PM PDT 24
Finished May 21 03:23:10 PM PDT 24
Peak memory 262728 kb
Host smart-a6951b91-461e-449f-90cf-18df0fb5b695
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205821603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1205821603
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.110469261
Short name T1077
Test name
Test status
Simulation time 1921475400 ps
CPU time 232.96 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:26:04 PM PDT 24
Peak memory 284084 kb
Host smart-96fdfa58-18fc-47c5-9eb3-c6214c842c0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110469261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas
h_ctrl_intr_rd.110469261
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2225642121
Short name T3
Test name
Test status
Simulation time 5877185800 ps
CPU time 136.34 seconds
Started May 21 03:22:13 PM PDT 24
Finished May 21 03:24:32 PM PDT 24
Peak memory 292456 kb
Host smart-062ff482-c936-4ebc-a4d1-889bbec249d6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225642121 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2225642121
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1457905790
Short name T472
Test name
Test status
Simulation time 9029785300 ps
CPU time 88.15 seconds
Started May 21 03:21:56 PM PDT 24
Finished May 21 03:23:25 PM PDT 24
Peak memory 259928 kb
Host smart-f7cb8202-a047-4dbc-a412-985914ea20c7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457905790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
457905790
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2680472016
Short name T786
Test name
Test status
Simulation time 45929100 ps
CPU time 13.47 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:22:24 PM PDT 24
Peak memory 265208 kb
Host smart-65a3850d-dde9-4626-9538-da7a2b34e51f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680472016 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2680472016
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.4217346477
Short name T83
Test name
Test status
Simulation time 113772458500 ps
CPU time 732.33 seconds
Started May 21 03:22:00 PM PDT 24
Finished May 21 03:34:13 PM PDT 24
Peak memory 274108 kb
Host smart-0c496115-991e-487c-a9fa-4be1b5f1093e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217346477 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.4217346477
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.1935238278
Short name T1096
Test name
Test status
Simulation time 44571100 ps
CPU time 132.42 seconds
Started May 21 03:21:54 PM PDT 24
Finished May 21 03:24:07 PM PDT 24
Peak memory 259984 kb
Host smart-26ca46e3-2aa0-4d6a-91b5-9bc2213d85fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935238278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.1935238278
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2307840070
Short name T1030
Test name
Test status
Simulation time 32503700 ps
CPU time 68.28 seconds
Started May 21 03:21:59 PM PDT 24
Finished May 21 03:23:08 PM PDT 24
Peak memory 262804 kb
Host smart-d29b6bbf-b695-4181-80dc-4b009761994e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307840070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2307840070
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2434694826
Short name T609
Test name
Test status
Simulation time 69596300 ps
CPU time 13.53 seconds
Started May 21 03:22:06 PM PDT 24
Finished May 21 03:22:23 PM PDT 24
Peak memory 265268 kb
Host smart-d8fc4078-2783-4ebc-8ee2-009d7a178cb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434694826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2434694826
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.1350286561
Short name T92
Test name
Test status
Simulation time 301408300 ps
CPU time 303.31 seconds
Started May 21 03:21:55 PM PDT 24
Finished May 21 03:27:00 PM PDT 24
Peak memory 278960 kb
Host smart-708fda36-ee3f-457b-8094-debf383c2e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350286561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1350286561
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1810021403
Short name T326
Test name
Test status
Simulation time 137348500 ps
CPU time 40.04 seconds
Started May 21 03:22:07 PM PDT 24
Finished May 21 03:22:50 PM PDT 24
Peak memory 273576 kb
Host smart-81c49e99-c37a-476c-8b3b-2367535d2c00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810021403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1810021403
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1130411758
Short name T216
Test name
Test status
Simulation time 922153800 ps
CPU time 112.42 seconds
Started May 21 03:22:02 PM PDT 24
Finished May 21 03:23:55 PM PDT 24
Peak memory 297152 kb
Host smart-9980bedf-f92b-4095-8ef9-3b778e33aae6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130411758 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.1130411758
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.3524863205
Short name T688
Test name
Test status
Simulation time 92959200 ps
CPU time 29.32 seconds
Started May 21 03:22:12 PM PDT 24
Finished May 21 03:22:43 PM PDT 24
Peak memory 273788 kb
Host smart-39e3cec8-1ffa-47a3-a074-7454e998fdeb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524863205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.3524863205
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1965474251
Short name T973
Test name
Test status
Simulation time 136558300 ps
CPU time 31.69 seconds
Started May 21 03:22:12 PM PDT 24
Finished May 21 03:22:45 PM PDT 24
Peak memory 274952 kb
Host smart-7b21e07c-88a5-4aaf-9dc1-48e815d54e71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965474251 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1965474251
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2983784495
Short name T928
Test name
Test status
Simulation time 1273739800 ps
CPU time 70.68 seconds
Started May 21 03:22:08 PM PDT 24
Finished May 21 03:23:21 PM PDT 24
Peak memory 262400 kb
Host smart-41abf0c1-684b-4afd-b413-fe2b83685743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983784495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2983784495
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1506542964
Short name T602
Test name
Test status
Simulation time 38478200 ps
CPU time 52.19 seconds
Started May 21 03:21:51 PM PDT 24
Finished May 21 03:22:44 PM PDT 24
Peak memory 270752 kb
Host smart-dd84660e-418a-4e63-925f-a2da27438482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506542964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1506542964
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.1445863012
Short name T1099
Test name
Test status
Simulation time 2424153900 ps
CPU time 189.19 seconds
Started May 21 03:22:01 PM PDT 24
Finished May 21 03:25:12 PM PDT 24
Peak memory 265204 kb
Host smart-e3c8b390-8927-42bf-9466-c0680c0cec8a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445863012 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.1445863012
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.562842291
Short name T485
Test name
Test status
Simulation time 56136600 ps
CPU time 14.02 seconds
Started May 21 03:22:32 PM PDT 24
Finished May 21 03:22:47 PM PDT 24
Peak memory 265200 kb
Host smart-ad285c64-4bd2-4906-8444-dd92dd145764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562842291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.562842291
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.1547970977
Short name T499
Test name
Test status
Simulation time 47912400 ps
CPU time 15.79 seconds
Started May 21 03:22:24 PM PDT 24
Finished May 21 03:22:41 PM PDT 24
Peak memory 275668 kb
Host smart-c694248d-bb47-42f1-bd3e-a6f8d9305b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547970977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1547970977
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.1530963331
Short name T742
Test name
Test status
Simulation time 12396100 ps
CPU time 21.61 seconds
Started May 21 03:22:31 PM PDT 24
Finished May 21 03:22:53 PM PDT 24
Peak memory 265380 kb
Host smart-b5c38679-d80e-49b5-b88c-a29addd7c714
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530963331 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.1530963331
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.610160244
Short name T566
Test name
Test status
Simulation time 10043009700 ps
CPU time 53.97 seconds
Started May 21 03:22:33 PM PDT 24
Finished May 21 03:23:28 PM PDT 24
Peak memory 281988 kb
Host smart-552962d2-80b0-49de-9a1b-b2941d44c5cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610160244 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.610160244
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2582564591
Short name T447
Test name
Test status
Simulation time 23034900 ps
CPU time 13.31 seconds
Started May 21 03:22:33 PM PDT 24
Finished May 21 03:22:48 PM PDT 24
Peak memory 265136 kb
Host smart-62f38c31-1303-47f3-90ec-14220bd309ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582564591 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2582564591
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.772854664
Short name T140
Test name
Test status
Simulation time 60132610400 ps
CPU time 920.53 seconds
Started May 21 03:22:12 PM PDT 24
Finished May 21 03:37:35 PM PDT 24
Peak memory 264408 kb
Host smart-c6329d67-f9ea-4eda-9b86-bcac76562504
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772854664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.flash_ctrl_hw_rma_reset.772854664
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2661480097
Short name T837
Test name
Test status
Simulation time 5159238400 ps
CPU time 84.09 seconds
Started May 21 03:22:14 PM PDT 24
Finished May 21 03:23:41 PM PDT 24
Peak memory 262424 kb
Host smart-0880e9e3-cb74-4d2d-be7e-33f93ea39237
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661480097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2661480097
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.2862846574
Short name T880
Test name
Test status
Simulation time 14240862500 ps
CPU time 185.89 seconds
Started May 21 03:22:20 PM PDT 24
Finished May 21 03:25:27 PM PDT 24
Peak memory 289884 kb
Host smart-32f443c2-62b0-48cb-90ca-6779b4115b0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862846574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.2862846574
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.4172515542
Short name T745
Test name
Test status
Simulation time 23892659500 ps
CPU time 140.13 seconds
Started May 21 03:22:25 PM PDT 24
Finished May 21 03:24:45 PM PDT 24
Peak memory 292048 kb
Host smart-7101e271-4b73-47e8-9755-5a24daef40d7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172515542 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.4172515542
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.1858401158
Short name T400
Test name
Test status
Simulation time 1609802800 ps
CPU time 65.4 seconds
Started May 21 03:22:19 PM PDT 24
Finished May 21 03:23:26 PM PDT 24
Peak memory 260624 kb
Host smart-dd1bf608-9467-43d9-b415-df8f9d710732
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858401158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1
858401158
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2477842265
Short name T701
Test name
Test status
Simulation time 47296800 ps
CPU time 13.19 seconds
Started May 21 03:22:27 PM PDT 24
Finished May 21 03:22:41 PM PDT 24
Peak memory 265184 kb
Host smart-411fce98-58b8-4424-85ea-8c5135a321f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477842265 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2477842265
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.3293062127
Short name T1000
Test name
Test status
Simulation time 15376162400 ps
CPU time 137.04 seconds
Started May 21 03:22:19 PM PDT 24
Finished May 21 03:24:38 PM PDT 24
Peak memory 262916 kb
Host smart-fd10fd90-04b8-4770-a05e-84e8e81198ac
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293062127 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.3293062127
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.763989178
Short name T910
Test name
Test status
Simulation time 38549300 ps
CPU time 132.03 seconds
Started May 21 03:22:18 PM PDT 24
Finished May 21 03:24:33 PM PDT 24
Peak memory 260008 kb
Host smart-c87a5079-7716-4553-8597-b174b4d34685
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763989178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.763989178
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.1358533551
Short name T782
Test name
Test status
Simulation time 73383100 ps
CPU time 238.05 seconds
Started May 21 03:22:14 PM PDT 24
Finished May 21 03:26:14 PM PDT 24
Peak memory 262532 kb
Host smart-798f9e4e-2342-496b-839d-e7d50e724e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358533551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1358533551
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.1073680648
Short name T1068
Test name
Test status
Simulation time 1722893600 ps
CPU time 126.78 seconds
Started May 21 03:22:30 PM PDT 24
Finished May 21 03:24:38 PM PDT 24
Peak memory 259172 kb
Host smart-6f8d67d8-962b-47f6-ac1f-e5c8e4f75ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073680648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.1073680648
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1591942610
Short name T772
Test name
Test status
Simulation time 196474200 ps
CPU time 528.49 seconds
Started May 21 03:22:14 PM PDT 24
Finished May 21 03:31:05 PM PDT 24
Peak memory 283212 kb
Host smart-226d23f7-92b8-4b70-a5e2-b8342cea81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591942610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1591942610
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2264179503
Short name T883
Test name
Test status
Simulation time 140489900 ps
CPU time 33.15 seconds
Started May 21 03:22:27 PM PDT 24
Finished May 21 03:23:01 PM PDT 24
Peak memory 273524 kb
Host smart-ce9b81ff-d690-4c37-b2ca-85a62bb416ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264179503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2264179503
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1302669173
Short name T656
Test name
Test status
Simulation time 1860229700 ps
CPU time 145.7 seconds
Started May 21 03:22:20 PM PDT 24
Finished May 21 03:24:47 PM PDT 24
Peak memory 281112 kb
Host smart-2bc30fdd-886b-4b9a-b04c-2c207bf7fa1e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302669173 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.1302669173
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2663631652
Short name T645
Test name
Test status
Simulation time 8323221300 ps
CPU time 624.47 seconds
Started May 21 03:22:20 PM PDT 24
Finished May 21 03:32:46 PM PDT 24
Peak memory 309608 kb
Host smart-7bec0a46-90e1-46a7-89f3-604aaa0d355b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663631652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2663631652
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.1211011320
Short name T219
Test name
Test status
Simulation time 47699500 ps
CPU time 31.83 seconds
Started May 21 03:22:24 PM PDT 24
Finished May 21 03:22:56 PM PDT 24
Peak memory 273508 kb
Host smart-f4ceff75-d727-4319-af61-1f70f25829c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211011320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.1211011320
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.871375417
Short name T734
Test name
Test status
Simulation time 44621600 ps
CPU time 31.52 seconds
Started May 21 03:22:26 PM PDT 24
Finished May 21 03:22:58 PM PDT 24
Peak memory 274864 kb
Host smart-f20f9a11-b1bf-4922-a1f9-bf3a78c5eee8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871375417 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.871375417
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.2879946997
Short name T943
Test name
Test status
Simulation time 574781000 ps
CPU time 60.94 seconds
Started May 21 03:22:24 PM PDT 24
Finished May 21 03:23:26 PM PDT 24
Peak memory 263308 kb
Host smart-e7c981d5-b376-4b31-b17b-a682196c5c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879946997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2879946997
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3472335437
Short name T860
Test name
Test status
Simulation time 83225200 ps
CPU time 122.65 seconds
Started May 21 03:22:12 PM PDT 24
Finished May 21 03:24:17 PM PDT 24
Peak memory 275752 kb
Host smart-de9db9df-24ea-42be-a1b5-d369bdbe370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472335437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3472335437
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1274683535
Short name T575
Test name
Test status
Simulation time 2233260800 ps
CPU time 185 seconds
Started May 21 03:22:20 PM PDT 24
Finished May 21 03:25:26 PM PDT 24
Peak memory 258948 kb
Host smart-cc8d86d5-f6ba-496e-8e0b-86266c653acd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274683535 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.1274683535
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.3516355561
Short name T439
Test name
Test status
Simulation time 128597700 ps
CPU time 13.77 seconds
Started May 21 03:22:50 PM PDT 24
Finished May 21 03:23:05 PM PDT 24
Peak memory 265188 kb
Host smart-37ed2579-80da-427f-9658-61340bc88fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516355561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
3516355561
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1513417715
Short name T776
Test name
Test status
Simulation time 39548000 ps
CPU time 16.1 seconds
Started May 21 03:22:43 PM PDT 24
Finished May 21 03:23:00 PM PDT 24
Peak memory 276060 kb
Host smart-3f9c5bfd-4121-4c77-88be-755d3ee00a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513417715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1513417715
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4294436807
Short name T237
Test name
Test status
Simulation time 10028499600 ps
CPU time 59.78 seconds
Started May 21 03:22:48 PM PDT 24
Finished May 21 03:23:49 PM PDT 24
Peak memory 294232 kb
Host smart-3d3ffde8-0675-4d7f-b496-78704f585060
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294436807 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.4294436807
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1693796526
Short name T284
Test name
Test status
Simulation time 49877700 ps
CPU time 13.81 seconds
Started May 21 03:22:49 PM PDT 24
Finished May 21 03:23:04 PM PDT 24
Peak memory 265344 kb
Host smart-04654ce2-bcff-4bed-9e81-85a3a43ac9af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693796526 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1693796526
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.252187381
Short name T627
Test name
Test status
Simulation time 40126030900 ps
CPU time 870.09 seconds
Started May 21 03:22:35 PM PDT 24
Finished May 21 03:37:05 PM PDT 24
Peak memory 263320 kb
Host smart-c4f178f6-c8ff-4e67-b94d-71fae4292f3c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252187381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_hw_rma_reset.252187381
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3770262187
Short name T1
Test name
Test status
Simulation time 3809909900 ps
CPU time 44.72 seconds
Started May 21 03:22:32 PM PDT 24
Finished May 21 03:23:18 PM PDT 24
Peak memory 262616 kb
Host smart-eb1b3082-f8a9-4116-987a-372f2f835978
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770262187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3770262187
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2477669874
Short name T801
Test name
Test status
Simulation time 1558081900 ps
CPU time 131.6 seconds
Started May 21 03:22:41 PM PDT 24
Finished May 21 03:24:54 PM PDT 24
Peak memory 292996 kb
Host smart-15f7648f-0be8-45a8-a257-fd249e22ef2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477669874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2477669874
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2033055978
Short name T965
Test name
Test status
Simulation time 146520367500 ps
CPU time 312.28 seconds
Started May 21 03:22:42 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 292416 kb
Host smart-0a437684-e67c-48ef-b3c5-29ca5de24ab5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033055978 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2033055978
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.2504165581
Short name T1089
Test name
Test status
Simulation time 1706582600 ps
CPU time 72.36 seconds
Started May 21 03:22:37 PM PDT 24
Finished May 21 03:23:50 PM PDT 24
Peak memory 260720 kb
Host smart-80f26712-0283-43ba-919d-8786026a558f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504165581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2
504165581
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.3698834894
Short name T811
Test name
Test status
Simulation time 26502100 ps
CPU time 13.21 seconds
Started May 21 03:22:43 PM PDT 24
Finished May 21 03:22:58 PM PDT 24
Peak memory 265192 kb
Host smart-984c48cb-9b1e-4bbe-8b89-b973c777d013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698834894 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.3698834894
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2175125622
Short name T1009
Test name
Test status
Simulation time 9373643500 ps
CPU time 311.11 seconds
Started May 21 03:22:32 PM PDT 24
Finished May 21 03:27:44 PM PDT 24
Peak memory 273184 kb
Host smart-dfd80c2a-20d0-4b4e-b940-f5f8706ee3b9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175125622 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2175125622
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.2925977443
Short name T674
Test name
Test status
Simulation time 156807400 ps
CPU time 111.97 seconds
Started May 21 03:22:30 PM PDT 24
Finished May 21 03:24:23 PM PDT 24
Peak memory 259880 kb
Host smart-bac3c401-ed1f-4e82-b892-596fe35d3e69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925977443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.2925977443
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.2373214372
Short name T628
Test name
Test status
Simulation time 7317962900 ps
CPU time 566.08 seconds
Started May 21 03:22:31 PM PDT 24
Finished May 21 03:31:59 PM PDT 24
Peak memory 262640 kb
Host smart-aa321c57-e2af-4a3f-acd0-c86b5589ccd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373214372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2373214372
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.268185021
Short name T705
Test name
Test status
Simulation time 67565500 ps
CPU time 13.3 seconds
Started May 21 03:22:45 PM PDT 24
Finished May 21 03:22:59 PM PDT 24
Peak memory 258660 kb
Host smart-a3616a28-9aea-45dc-907c-5b6d3790c121
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268185021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_res
et.268185021
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.3141729357
Short name T1083
Test name
Test status
Simulation time 744034300 ps
CPU time 708.44 seconds
Started May 21 03:22:34 PM PDT 24
Finished May 21 03:34:23 PM PDT 24
Peak memory 283568 kb
Host smart-d18624bd-354b-4886-b95b-bdbd48c20637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141729357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3141729357
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2553979970
Short name T276
Test name
Test status
Simulation time 273549000 ps
CPU time 35.53 seconds
Started May 21 03:22:44 PM PDT 24
Finished May 21 03:23:21 PM PDT 24
Peak memory 273636 kb
Host smart-717b6cc3-9e03-432a-8822-44868a4b3649
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553979970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2553979970
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3180287072
Short name T1043
Test name
Test status
Simulation time 1211123100 ps
CPU time 111.09 seconds
Started May 21 03:22:37 PM PDT 24
Finished May 21 03:24:29 PM PDT 24
Peak memory 280988 kb
Host smart-e782361f-ffb3-400b-92b1-172643bb317e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180287072 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.3180287072
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1413000239
Short name T520
Test name
Test status
Simulation time 3624659900 ps
CPU time 638.25 seconds
Started May 21 03:22:37 PM PDT 24
Finished May 21 03:33:15 PM PDT 24
Peak memory 309672 kb
Host smart-0cab33ac-7452-4f99-a593-d5bdb08cfc2f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413000239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.1413000239
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.298769762
Short name T527
Test name
Test status
Simulation time 176283000 ps
CPU time 31.39 seconds
Started May 21 03:22:42 PM PDT 24
Finished May 21 03:23:14 PM PDT 24
Peak memory 274612 kb
Host smart-9b3c2666-2274-4890-a1c6-d53c3a183e9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298769762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.298769762
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2748138870
Short name T927
Test name
Test status
Simulation time 79525600 ps
CPU time 31.89 seconds
Started May 21 03:22:45 PM PDT 24
Finished May 21 03:23:18 PM PDT 24
Peak memory 276428 kb
Host smart-78d69c88-28d6-43e5-a6fb-4b7ed0e60e3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748138870 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2748138870
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.3458068465
Short name T926
Test name
Test status
Simulation time 73265000 ps
CPU time 121.04 seconds
Started May 21 03:22:32 PM PDT 24
Finished May 21 03:24:34 PM PDT 24
Peak memory 275848 kb
Host smart-c207aecf-a502-4b9b-b5ce-b6991d728e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458068465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3458068465
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.8716048
Short name T171
Test name
Test status
Simulation time 1871397600 ps
CPU time 159.72 seconds
Started May 21 03:22:35 PM PDT 24
Finished May 21 03:25:15 PM PDT 24
Peak memory 258788 kb
Host smart-5ee9023c-00cf-408a-a8fc-d399736ac6cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8716048 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_wo.8716048
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.1592032256
Short name T1028
Test name
Test status
Simulation time 126657100 ps
CPU time 13.42 seconds
Started May 21 03:23:06 PM PDT 24
Finished May 21 03:23:21 PM PDT 24
Peak memory 265160 kb
Host smart-61d1ac68-8db4-4ac9-98e1-ddcbd2370618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592032256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
1592032256
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.731257049
Short name T956
Test name
Test status
Simulation time 35223800 ps
CPU time 15.81 seconds
Started May 21 03:23:07 PM PDT 24
Finished May 21 03:23:24 PM PDT 24
Peak memory 275104 kb
Host smart-6dfa6b70-610e-4a04-8839-6677c3ba1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731257049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.731257049
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2921040218
Short name T1103
Test name
Test status
Simulation time 10020223900 ps
CPU time 71.48 seconds
Started May 21 03:23:00 PM PDT 24
Finished May 21 03:24:14 PM PDT 24
Peak memory 280596 kb
Host smart-efe1c9d8-a9ac-4ab6-97fa-10a06f38a7b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921040218 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2921040218
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.959878032
Short name T214
Test name
Test status
Simulation time 20403000 ps
CPU time 13.47 seconds
Started May 21 03:23:02 PM PDT 24
Finished May 21 03:23:18 PM PDT 24
Peak memory 265140 kb
Host smart-0a324305-1b4b-493a-9fa0-659c0428735b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959878032 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.959878032
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3772729925
Short name T571
Test name
Test status
Simulation time 160168090200 ps
CPU time 844.16 seconds
Started May 21 03:22:49 PM PDT 24
Finished May 21 03:36:55 PM PDT 24
Peak memory 263920 kb
Host smart-07690994-1435-492b-a1b7-07efa87967cb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772729925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.3772729925
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.747550073
Short name T522
Test name
Test status
Simulation time 12162213400 ps
CPU time 110.7 seconds
Started May 21 03:22:48 PM PDT 24
Finished May 21 03:24:40 PM PDT 24
Peak memory 262604 kb
Host smart-c455852d-7122-4dc3-a5e3-4e3820b966ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747550073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h
w_sec_otp.747550073
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.40870658
Short name T34
Test name
Test status
Simulation time 1668363000 ps
CPU time 129.96 seconds
Started May 21 03:22:57 PM PDT 24
Finished May 21 03:25:09 PM PDT 24
Peak memory 293272 kb
Host smart-86ce51c8-7d45-4408-9864-026a0584ee01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash
_ctrl_intr_rd.40870658
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.41483681
Short name T422
Test name
Test status
Simulation time 5904987600 ps
CPU time 153.06 seconds
Started May 21 03:22:58 PM PDT 24
Finished May 21 03:25:33 PM PDT 24
Peak memory 292004 kb
Host smart-b0b4cf22-91f5-4c23-b101-ac0c5101ee24
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41483681 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.41483681
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.2023784137
Short name T1055
Test name
Test status
Simulation time 3340520700 ps
CPU time 73.81 seconds
Started May 21 03:22:57 PM PDT 24
Finished May 21 03:24:13 PM PDT 24
Peak memory 259832 kb
Host smart-b1d00540-9e3a-473a-bfe6-e23f8f9b4457
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023784137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2
023784137
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.1281557529
Short name T80
Test name
Test status
Simulation time 119308638900 ps
CPU time 1061.02 seconds
Started May 21 03:22:58 PM PDT 24
Finished May 21 03:40:41 PM PDT 24
Peak memory 273476 kb
Host smart-52bcbb11-0486-4039-af3f-83237c3e4ced
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281557529 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.1281557529
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1868942998
Short name T151
Test name
Test status
Simulation time 43379000 ps
CPU time 130.95 seconds
Started May 21 03:22:48 PM PDT 24
Finished May 21 03:25:01 PM PDT 24
Peak memory 260972 kb
Host smart-d5f6852c-d0a6-4d0a-bc73-38155c283c9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868942998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1868942998
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2652333474
Short name T467
Test name
Test status
Simulation time 48494700 ps
CPU time 107.65 seconds
Started May 21 03:22:48 PM PDT 24
Finished May 21 03:24:37 PM PDT 24
Peak memory 261820 kb
Host smart-d58a3dbf-6fa6-4c6d-819f-3648a2252e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652333474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2652333474
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.709667501
Short name T765
Test name
Test status
Simulation time 1925710000 ps
CPU time 164.82 seconds
Started May 21 03:23:01 PM PDT 24
Finished May 21 03:25:48 PM PDT 24
Peak memory 264688 kb
Host smart-d8b7ca0a-8938-4978-b692-0b6fe5dca51c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709667501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_res
et.709667501
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3940920027
Short name T74
Test name
Test status
Simulation time 535061200 ps
CPU time 1073.77 seconds
Started May 21 03:22:50 PM PDT 24
Finished May 21 03:40:45 PM PDT 24
Peak memory 288072 kb
Host smart-47d98c6a-ff39-4754-bf6f-5f2ef554348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940920027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3940920027
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.1326265113
Short name T760
Test name
Test status
Simulation time 264839000 ps
CPU time 38.78 seconds
Started May 21 03:23:01 PM PDT 24
Finished May 21 03:23:42 PM PDT 24
Peak memory 275576 kb
Host smart-accd6d8a-5efd-4ddd-870e-f66810e77851
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326265113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.1326265113
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.4007922520
Short name T900
Test name
Test status
Simulation time 7496879400 ps
CPU time 125.77 seconds
Started May 21 03:22:58 PM PDT 24
Finished May 21 03:25:06 PM PDT 24
Peak memory 296928 kb
Host smart-1c027315-e547-4088-b262-30d71fae7274
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007922520 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.4007922520
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1112078233
Short name T617
Test name
Test status
Simulation time 3950246800 ps
CPU time 577.05 seconds
Started May 21 03:22:57 PM PDT 24
Finished May 21 03:32:37 PM PDT 24
Peak memory 309572 kb
Host smart-98df724d-6c3a-465b-8164-27d35bec9176
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112078233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.1112078233
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.530268522
Short name T836
Test name
Test status
Simulation time 50119700 ps
CPU time 32.44 seconds
Started May 21 03:23:01 PM PDT 24
Finished May 21 03:23:35 PM PDT 24
Peak memory 273528 kb
Host smart-a5fbe0b8-42ff-44fa-ac5d-5b2f313ec3ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530268522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.530268522
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.4120349020
Short name T24
Test name
Test status
Simulation time 46657300 ps
CPU time 31.7 seconds
Started May 21 03:23:00 PM PDT 24
Finished May 21 03:23:34 PM PDT 24
Peak memory 274880 kb
Host smart-11a16e62-ce34-4671-bd8b-aef22c7e3342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120349020 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.4120349020
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2370576733
Short name T862
Test name
Test status
Simulation time 556339900 ps
CPU time 62.42 seconds
Started May 21 03:23:01 PM PDT 24
Finished May 21 03:24:06 PM PDT 24
Peak memory 263360 kb
Host smart-1b8f78e8-e828-4903-9523-4b93347e05c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370576733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2370576733
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.265933873
Short name T827
Test name
Test status
Simulation time 27581500 ps
CPU time 76.79 seconds
Started May 21 03:22:49 PM PDT 24
Finished May 21 03:24:07 PM PDT 24
Peak memory 276056 kb
Host smart-522a7274-c402-423a-9c32-d7194d78c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265933873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.265933873
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.4074756059
Short name T376
Test name
Test status
Simulation time 3238895600 ps
CPU time 222.6 seconds
Started May 21 03:22:58 PM PDT 24
Finished May 21 03:26:43 PM PDT 24
Peak memory 265184 kb
Host smart-a3dffc8b-7980-41ee-b059-00bef094676f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074756059 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.4074756059
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1930458211
Short name T594
Test name
Test status
Simulation time 145224900 ps
CPU time 13.69 seconds
Started May 21 03:23:24 PM PDT 24
Finished May 21 03:23:40 PM PDT 24
Peak memory 265156 kb
Host smart-b12f81e1-09dd-4f64-9a91-f565bf4fce12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930458211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1930458211
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.3023512120
Short name T357
Test name
Test status
Simulation time 10778800 ps
CPU time 22.67 seconds
Started May 21 03:23:18 PM PDT 24
Finished May 21 03:23:43 PM PDT 24
Peak memory 265192 kb
Host smart-56290ce5-4578-4115-9590-f6078c0cbf82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023512120 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.3023512120
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2327766794
Short name T712
Test name
Test status
Simulation time 10019742500 ps
CPU time 161.86 seconds
Started May 21 03:23:26 PM PDT 24
Finished May 21 03:26:10 PM PDT 24
Peak memory 288920 kb
Host smart-71e0c4ba-f1a8-41b5-80ab-54143a1b2b7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327766794 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2327766794
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1171603769
Short name T335
Test name
Test status
Simulation time 96597400 ps
CPU time 13.52 seconds
Started May 21 03:23:26 PM PDT 24
Finished May 21 03:23:41 PM PDT 24
Peak memory 265176 kb
Host smart-05f3d421-06d6-4505-b562-f30ba49b555c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171603769 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1171603769
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2999531889
Short name T825
Test name
Test status
Simulation time 80155188700 ps
CPU time 909.3 seconds
Started May 21 03:23:06 PM PDT 24
Finished May 21 03:38:17 PM PDT 24
Peak memory 264540 kb
Host smart-8eb45222-fd8a-4e01-9090-f8f03ecb49c0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999531889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2999531889
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.701133245
Short name T744
Test name
Test status
Simulation time 3038655000 ps
CPU time 38.24 seconds
Started May 21 03:23:07 PM PDT 24
Finished May 21 03:23:48 PM PDT 24
Peak memory 262484 kb
Host smart-b6b38fdc-4596-40a8-bd52-2c92b3e2d261
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701133245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.701133245
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.814333114
Short name T323
Test name
Test status
Simulation time 3242622200 ps
CPU time 196.49 seconds
Started May 21 03:23:11 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 289876 kb
Host smart-8c20fc5f-eb6e-4020-8c64-50baccd49742
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814333114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.814333114
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.195239133
Short name T185
Test name
Test status
Simulation time 13528631000 ps
CPU time 259.41 seconds
Started May 21 03:23:13 PM PDT 24
Finished May 21 03:27:35 PM PDT 24
Peak memory 293564 kb
Host smart-0f9d3318-4afb-49d8-b398-fb10a163aae7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195239133 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.195239133
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2653696737
Short name T812
Test name
Test status
Simulation time 1662540600 ps
CPU time 63.57 seconds
Started May 21 03:23:13 PM PDT 24
Finished May 21 03:24:19 PM PDT 24
Peak memory 263664 kb
Host smart-d7228277-e204-474f-996c-57309416b07d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653696737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
653696737
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2701224659
Short name T901
Test name
Test status
Simulation time 46316500 ps
CPU time 13.46 seconds
Started May 21 03:23:27 PM PDT 24
Finished May 21 03:23:42 PM PDT 24
Peak memory 265256 kb
Host smart-5e1c1452-3bd5-4cf8-a59e-bf9b6f1f0294
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701224659 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2701224659
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.4261192616
Short name T894
Test name
Test status
Simulation time 46849330700 ps
CPU time 408.38 seconds
Started May 21 03:23:12 PM PDT 24
Finished May 21 03:30:04 PM PDT 24
Peak memory 274508 kb
Host smart-ecfc109e-7ce7-42fa-aba9-2a97c5554b61
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261192616 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.4261192616
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.3368983831
Short name T908
Test name
Test status
Simulation time 43831100 ps
CPU time 130.34 seconds
Started May 21 03:23:13 PM PDT 24
Finished May 21 03:25:26 PM PDT 24
Peak memory 261108 kb
Host smart-e692ebe9-3520-418b-b5fe-b5ecd1f0d780
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368983831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.3368983831
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2352849383
Short name T239
Test name
Test status
Simulation time 5762491500 ps
CPU time 515.97 seconds
Started May 21 03:23:05 PM PDT 24
Finished May 21 03:31:43 PM PDT 24
Peak memory 261744 kb
Host smart-dd04a551-b472-442f-b7c1-6ad6c20828f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352849383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2352849383
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2170196108
Short name T875
Test name
Test status
Simulation time 53957900 ps
CPU time 13.32 seconds
Started May 21 03:23:11 PM PDT 24
Finished May 21 03:23:25 PM PDT 24
Peak memory 258864 kb
Host smart-406a3436-5208-4528-80b2-bd857a0e484d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170196108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2170196108
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.4284039810
Short name T97
Test name
Test status
Simulation time 167414700 ps
CPU time 645.4 seconds
Started May 21 03:23:07 PM PDT 24
Finished May 21 03:33:55 PM PDT 24
Peak memory 283800 kb
Host smart-38c92cb0-a99c-42ee-b098-a874616a1689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284039810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.4284039810
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2583454692
Short name T466
Test name
Test status
Simulation time 132296800 ps
CPU time 38.84 seconds
Started May 21 03:23:18 PM PDT 24
Finished May 21 03:23:59 PM PDT 24
Peak memory 273548 kb
Host smart-afd58e82-c8e0-4f40-8b43-960459df0187
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583454692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2583454692
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.191654412
Short name T591
Test name
Test status
Simulation time 1892446900 ps
CPU time 135.94 seconds
Started May 21 03:23:12 PM PDT 24
Finished May 21 03:25:29 PM PDT 24
Peak memory 281712 kb
Host smart-b69e5439-f9de-4259-8820-e8aeb18e857d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191654412 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.flash_ctrl_ro.191654412
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1545713142
Short name T512
Test name
Test status
Simulation time 270642700 ps
CPU time 32.32 seconds
Started May 21 03:23:16 PM PDT 24
Finished May 21 03:23:50 PM PDT 24
Peak memory 269368 kb
Host smart-3a356d2d-e42b-4e93-93bb-a7fb9d5e903e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545713142 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1545713142
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1823372706
Short name T785
Test name
Test status
Simulation time 2921706800 ps
CPU time 76.57 seconds
Started May 21 03:23:17 PM PDT 24
Finished May 21 03:24:36 PM PDT 24
Peak memory 262972 kb
Host smart-284e3762-caef-4825-9390-87a66a562e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823372706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1823372706
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2787051293
Short name T421
Test name
Test status
Simulation time 16235200 ps
CPU time 75.02 seconds
Started May 21 03:23:06 PM PDT 24
Finished May 21 03:24:22 PM PDT 24
Peak memory 276120 kb
Host smart-23911d74-86ff-4517-b49b-e0db92c85762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787051293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2787051293
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.830279267
Short name T556
Test name
Test status
Simulation time 1749222600 ps
CPU time 131.06 seconds
Started May 21 03:23:13 PM PDT 24
Finished May 21 03:25:26 PM PDT 24
Peak memory 265220 kb
Host smart-682a2b9d-26b2-454e-a03b-e9a7638c8657
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830279267 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.flash_ctrl_wo.830279267
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.2820869706
Short name T22
Test name
Test status
Simulation time 11917500 ps
CPU time 13.72 seconds
Started May 21 03:15:31 PM PDT 24
Finished May 21 03:15:45 PM PDT 24
Peak memory 265248 kb
Host smart-12cc61db-25c7-4648-be54-9f137d89df26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820869706 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2820869706
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2884060903
Short name T1032
Test name
Test status
Simulation time 103914300 ps
CPU time 13.55 seconds
Started May 21 03:15:59 PM PDT 24
Finished May 21 03:16:14 PM PDT 24
Peak memory 265180 kb
Host smart-c2895772-fb34-4d77-9607-3bba1537709f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884060903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
884060903
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.4098299866
Short name T790
Test name
Test status
Simulation time 20187500 ps
CPU time 13.69 seconds
Started May 21 03:15:39 PM PDT 24
Finished May 21 03:15:54 PM PDT 24
Peak memory 261580 kb
Host smart-1f5e428d-73e2-49d2-a5e2-5bd959e03a59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098299866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.4098299866
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.2547585655
Short name T892
Test name
Test status
Simulation time 49754600 ps
CPU time 15.61 seconds
Started May 21 03:15:16 PM PDT 24
Finished May 21 03:15:32 PM PDT 24
Peak memory 275660 kb
Host smart-98e49e07-ad7e-4fb1-8ccc-3916f5cc30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547585655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2547585655
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2516734994
Short name T909
Test name
Test status
Simulation time 115174300 ps
CPU time 102.36 seconds
Started May 21 03:14:55 PM PDT 24
Finished May 21 03:16:38 PM PDT 24
Peak memory 273504 kb
Host smart-529243ce-1a5c-45a6-ac79-aff263d80114
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516734994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2516734994
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.864129490
Short name T592
Test name
Test status
Simulation time 12598000 ps
CPU time 22.01 seconds
Started May 21 03:15:05 PM PDT 24
Finished May 21 03:15:28 PM PDT 24
Peak memory 265244 kb
Host smart-df1a0d23-2c9b-49d7-a424-81ffdaa4f562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864129490 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.864129490
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.100118091
Short name T121
Test name
Test status
Simulation time 2090100400 ps
CPU time 387.55 seconds
Started May 21 03:14:48 PM PDT 24
Finished May 21 03:21:16 PM PDT 24
Peak memory 261428 kb
Host smart-88e74fee-db7e-4147-81fc-e6d476896139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100118091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.100118091
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.2111135470
Short name T869
Test name
Test status
Simulation time 5505703300 ps
CPU time 2329 seconds
Started May 21 03:14:47 PM PDT 24
Finished May 21 03:53:36 PM PDT 24
Peak memory 265200 kb
Host smart-3c0f5c93-145e-4ec3-80a0-a44434a29df9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111135470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.2111135470
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1852610226
Short name T770
Test name
Test status
Simulation time 1367659400 ps
CPU time 2956.77 seconds
Started May 21 03:14:42 PM PDT 24
Finished May 21 04:03:59 PM PDT 24
Peak memory 265156 kb
Host smart-f4b890c2-8bde-4514-aada-dbc9b34ac7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852610226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1852610226
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2729435622
Short name T1040
Test name
Test status
Simulation time 1079931500 ps
CPU time 767.75 seconds
Started May 21 03:14:35 PM PDT 24
Finished May 21 03:27:24 PM PDT 24
Peak memory 273400 kb
Host smart-36f6dd99-c7f4-4932-a345-d369dfbda827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729435622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2729435622
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.203193032
Short name T48
Test name
Test status
Simulation time 514715200 ps
CPU time 23.81 seconds
Started May 21 03:14:51 PM PDT 24
Finished May 21 03:15:16 PM PDT 24
Peak memory 265196 kb
Host smart-f095c22d-f986-4cf8-a18c-1fa852c8f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203193032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.203193032
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2704321669
Short name T59
Test name
Test status
Simulation time 88191638100 ps
CPU time 2633.81 seconds
Started May 21 03:14:36 PM PDT 24
Finished May 21 03:58:32 PM PDT 24
Peak memory 265184 kb
Host smart-2480c6d0-391f-4724-8143-5e3b01a83203
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704321669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2704321669
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.1074526567
Short name T568
Test name
Test status
Simulation time 86068200 ps
CPU time 80.25 seconds
Started May 21 03:14:20 PM PDT 24
Finished May 21 03:15:41 PM PDT 24
Peak memory 262636 kb
Host smart-c37e745c-c52f-4fa7-a417-8529d77f0aeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074526567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1074526567
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3797518490
Short name T974
Test name
Test status
Simulation time 10019141500 ps
CPU time 180.84 seconds
Started May 21 03:15:28 PM PDT 24
Finished May 21 03:18:29 PM PDT 24
Peak memory 284440 kb
Host smart-ce3985ba-6bbc-4ef7-8250-4359702207d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797518490 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3797518490
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2962204339
Short name T655
Test name
Test status
Simulation time 51839100 ps
CPU time 13.33 seconds
Started May 21 03:15:29 PM PDT 24
Finished May 21 03:15:43 PM PDT 24
Peak memory 265088 kb
Host smart-19e50a88-cd5f-4552-8864-dd4b36bc4d79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962204339 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2962204339
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.1810279499
Short name T929
Test name
Test status
Simulation time 1152776778900 ps
CPU time 3103.82 seconds
Started May 21 03:14:40 PM PDT 24
Finished May 21 04:06:25 PM PDT 24
Peak memory 264184 kb
Host smart-38f22400-cd18-4ef8-8aa9-9e35523a5dae
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810279499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.1810279499
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2220492927
Short name T382
Test name
Test status
Simulation time 40127077300 ps
CPU time 905.92 seconds
Started May 21 03:14:31 PM PDT 24
Finished May 21 03:29:39 PM PDT 24
Peak memory 263364 kb
Host smart-2f7a89c0-a720-4d22-abfe-265d3cb78ff9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220492927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.2220492927
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2677123830
Short name T885
Test name
Test status
Simulation time 2614972900 ps
CPU time 69.36 seconds
Started May 21 03:14:30 PM PDT 24
Finished May 21 03:15:41 PM PDT 24
Peak memory 262700 kb
Host smart-f3ccdee7-6389-47aa-9b4a-d7b770ef7de7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677123830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2677123830
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.3297727403
Short name T949
Test name
Test status
Simulation time 13622045100 ps
CPU time 163.07 seconds
Started May 21 03:15:27 PM PDT 24
Finished May 21 03:18:11 PM PDT 24
Peak memory 289976 kb
Host smart-27296d71-edc5-4d7a-b2a0-daad0d7629d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297727403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.3297727403
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2977216529
Short name T925
Test name
Test status
Simulation time 6204908300 ps
CPU time 157.11 seconds
Started May 21 03:15:09 PM PDT 24
Finished May 21 03:17:47 PM PDT 24
Peak memory 293208 kb
Host smart-cb4046fb-fcc2-4727-b26d-2d5275a2bd09
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977216529 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2977216529
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3238959378
Short name T29
Test name
Test status
Simulation time 4623274200 ps
CPU time 73.37 seconds
Started May 21 03:14:59 PM PDT 24
Finished May 21 03:16:12 PM PDT 24
Peak memory 260160 kb
Host smart-495eb180-7f10-49d1-bb77-0cc376a0c455
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238959378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3238959378
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3799884972
Short name T27
Test name
Test status
Simulation time 66672000500 ps
CPU time 233.84 seconds
Started May 21 03:14:59 PM PDT 24
Finished May 21 03:18:54 PM PDT 24
Peak memory 265240 kb
Host smart-325a3083-8a07-4cac-aca6-46ebb0b35e32
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379
9884972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3799884972
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.685240449
Short name T504
Test name
Test status
Simulation time 8805640400 ps
CPU time 96.72 seconds
Started May 21 03:14:43 PM PDT 24
Finished May 21 03:16:20 PM PDT 24
Peak memory 262560 kb
Host smart-b012cd2b-d9b8-40b6-b4fc-b444652380b2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685240449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.685240449
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.469992754
Short name T752
Test name
Test status
Simulation time 15776100 ps
CPU time 13.41 seconds
Started May 21 03:15:28 PM PDT 24
Finished May 21 03:15:42 PM PDT 24
Peak memory 265216 kb
Host smart-0973533f-403d-463a-abe2-d2cc229256e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469992754 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.469992754
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.934710827
Short name T99
Test name
Test status
Simulation time 8680493500 ps
CPU time 640.16 seconds
Started May 21 03:14:40 PM PDT 24
Finished May 21 03:25:21 PM PDT 24
Peak memory 274212 kb
Host smart-bfc24f06-8e3d-46b2-ab76-ee5be06247d4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934710827 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_mp_regions.934710827
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.4071315946
Short name T41
Test name
Test status
Simulation time 1279168800 ps
CPU time 206.38 seconds
Started May 21 03:15:10 PM PDT 24
Finished May 21 03:18:37 PM PDT 24
Peak memory 294404 kb
Host smart-1a38f5dc-e586-4a38-ab49-c0e70ec6a8c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071315946 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4071315946
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2830696391
Short name T950
Test name
Test status
Simulation time 15851500 ps
CPU time 13.83 seconds
Started May 21 03:15:22 PM PDT 24
Finished May 21 03:15:37 PM PDT 24
Peak memory 276916 kb
Host smart-2aa67933-868f-4051-a5a8-4e480f9aec5e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2830696391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2830696391
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3052106430
Short name T886
Test name
Test status
Simulation time 85064000 ps
CPU time 396.28 seconds
Started May 21 03:14:31 PM PDT 24
Finished May 21 03:21:09 PM PDT 24
Peak memory 262652 kb
Host smart-5e9281f9-dd74-49cb-a3ca-6d80070725dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052106430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3052106430
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3820930159
Short name T114
Test name
Test status
Simulation time 786517600 ps
CPU time 24.58 seconds
Started May 21 03:15:22 PM PDT 24
Finished May 21 03:15:47 PM PDT 24
Peak memory 264864 kb
Host smart-615dc9ce-5464-4dde-bf58-caac9eb7e707
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820930159 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3820930159
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.4249565246
Short name T967
Test name
Test status
Simulation time 39816200 ps
CPU time 13.67 seconds
Started May 21 03:15:04 PM PDT 24
Finished May 21 03:15:19 PM PDT 24
Peak memory 265196 kb
Host smart-55287276-2559-43ac-a052-1d3bb8a6f85f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249565246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.4249565246
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1390905766
Short name T941
Test name
Test status
Simulation time 1558449700 ps
CPU time 819.74 seconds
Started May 21 03:14:21 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 283072 kb
Host smart-8792e0e3-f99d-45f9-bb9a-2e85cdccdcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390905766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1390905766
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.4199798927
Short name T548
Test name
Test status
Simulation time 53596600 ps
CPU time 100.27 seconds
Started May 21 03:14:24 PM PDT 24
Finished May 21 03:16:06 PM PDT 24
Peak memory 265180 kb
Host smart-6c7f8ff6-7052-4dbd-a78c-b1ee803e79d0
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4199798927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.4199798927
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.863291580
Short name T783
Test name
Test status
Simulation time 115880700 ps
CPU time 32.5 seconds
Started May 21 03:15:17 PM PDT 24
Finished May 21 03:15:50 PM PDT 24
Peak memory 273712 kb
Host smart-fa2f35a7-6ef1-4d59-9fe1-d50fa26831e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863291580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.863291580
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.821001868
Short name T635
Test name
Test status
Simulation time 135709500 ps
CPU time 35.06 seconds
Started May 21 03:15:36 PM PDT 24
Finished May 21 03:16:12 PM PDT 24
Peak memory 273592 kb
Host smart-b0835dd5-8bf6-432e-8524-752eb4b9d98e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821001868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_re_evict.821001868
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1542328195
Short name T433
Test name
Test status
Simulation time 18966100 ps
CPU time 23.12 seconds
Started May 21 03:15:05 PM PDT 24
Finished May 21 03:15:29 PM PDT 24
Peak memory 265228 kb
Host smart-89dc391c-e018-4dfa-bf77-707080358319
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542328195 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1542328195
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2065294368
Short name T86
Test name
Test status
Simulation time 46249100 ps
CPU time 21.46 seconds
Started May 21 03:15:08 PM PDT 24
Finished May 21 03:15:30 PM PDT 24
Peak memory 265296 kb
Host smart-b269d81f-4faa-4786-84b5-a2259cb8eb53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065294368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2065294368
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2026209991
Short name T158
Test name
Test status
Simulation time 52480935400 ps
CPU time 940.43 seconds
Started May 21 03:15:38 PM PDT 24
Finished May 21 03:31:20 PM PDT 24
Peak memory 290024 kb
Host smart-beb19c82-30a9-4a01-ae30-827cde58e051
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026209991 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2026209991
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.786883749
Short name T769
Test name
Test status
Simulation time 1974328100 ps
CPU time 153.88 seconds
Started May 21 03:14:49 PM PDT 24
Finished May 21 03:17:24 PM PDT 24
Peak memory 296948 kb
Host smart-d352611d-6405-47d0-9d10-cdd09f5f87aa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786883749 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_ro.786883749
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.842745028
Short name T474
Test name
Test status
Simulation time 487797300 ps
CPU time 178.25 seconds
Started May 21 03:14:54 PM PDT 24
Finished May 21 03:17:53 PM PDT 24
Peak memory 281756 kb
Host smart-cb730f21-23a5-4014-b1cc-dcc34a4d7aa8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
842745028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.842745028
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.711538152
Short name T845
Test name
Test status
Simulation time 1077408100 ps
CPU time 129.25 seconds
Started May 21 03:14:50 PM PDT 24
Finished May 21 03:17:00 PM PDT 24
Peak memory 294492 kb
Host smart-a9538883-6d8c-4494-9d60-3b1d744055ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711538152 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.711538152
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.72725795
Short name T221
Test name
Test status
Simulation time 3812235600 ps
CPU time 658.46 seconds
Started May 21 03:14:54 PM PDT 24
Finished May 21 03:25:53 PM PDT 24
Peak memory 333160 kb
Host smart-56e1f4c0-9c67-46e7-b704-f6b93cf2cb20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72725795 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.flash_ctrl_rw_derr.72725795
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.1723512740
Short name T330
Test name
Test status
Simulation time 81723300 ps
CPU time 31.38 seconds
Started May 21 03:15:04 PM PDT 24
Finished May 21 03:15:36 PM PDT 24
Peak memory 274576 kb
Host smart-a38124bb-8607-4c79-8269-9c08959e8310
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723512740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.1723512740
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2758445007
Short name T638
Test name
Test status
Simulation time 76591500 ps
CPU time 31.08 seconds
Started May 21 03:15:05 PM PDT 24
Finished May 21 03:15:37 PM PDT 24
Peak memory 274784 kb
Host smart-cc792646-e5ce-4af2-a0c6-605ed0770d48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758445007 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2758445007
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.647658045
Short name T180
Test name
Test status
Simulation time 2369047100 ps
CPU time 71.41 seconds
Started May 21 03:15:10 PM PDT 24
Finished May 21 03:16:22 PM PDT 24
Peak memory 262932 kb
Host smart-d7b34aa8-e344-4b9e-b785-d68f8c2de4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647658045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.647658045
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.2145519188
Short name T663
Test name
Test status
Simulation time 10784659300 ps
CPU time 80.18 seconds
Started May 21 03:14:55 PM PDT 24
Finished May 21 03:16:16 PM PDT 24
Peak memory 273472 kb
Host smart-0c7b8c12-452e-4f00-83e9-516ca08c6a7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145519188 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.2145519188
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.86927502
Short name T35
Test name
Test status
Simulation time 953686300 ps
CPU time 100.86 seconds
Started May 21 03:14:54 PM PDT 24
Finished May 21 03:16:36 PM PDT 24
Peak memory 273568 kb
Host smart-d700448e-aeb2-4070-9234-908df5c746d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86927502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_counter.86927502
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.55386388
Short name T882
Test name
Test status
Simulation time 1413437400 ps
CPU time 130.13 seconds
Started May 21 03:14:19 PM PDT 24
Finished May 21 03:16:31 PM PDT 24
Peak memory 281524 kb
Host smart-d3e9740c-616b-4ac8-a0f2-15098e12741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55386388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.55386388
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1566313796
Short name T1017
Test name
Test status
Simulation time 18152000 ps
CPU time 26.03 seconds
Started May 21 03:14:36 PM PDT 24
Finished May 21 03:15:04 PM PDT 24
Peak memory 259084 kb
Host smart-f5fba3e5-8fbf-4abd-a638-a0fd92397315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566313796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1566313796
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2235543114
Short name T38
Test name
Test status
Simulation time 210720000 ps
CPU time 1160.24 seconds
Started May 21 03:15:10 PM PDT 24
Finished May 21 03:34:31 PM PDT 24
Peak memory 285640 kb
Host smart-b36c3c06-bc4a-4b25-a648-4ffd0070c1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235543114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2235543114
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.4254965448
Short name T440
Test name
Test status
Simulation time 22394800 ps
CPU time 26.37 seconds
Started May 21 03:14:20 PM PDT 24
Finished May 21 03:14:48 PM PDT 24
Peak memory 261368 kb
Host smart-ea8d33f4-1109-44d0-8b32-7e6c57ab8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254965448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4254965448
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.1367439459
Short name T747
Test name
Test status
Simulation time 6699853000 ps
CPU time 150.61 seconds
Started May 21 03:14:52 PM PDT 24
Finished May 21 03:17:24 PM PDT 24
Peak memory 265140 kb
Host smart-11f9efd1-e4ce-497c-bf83-5ee9ef8a5276
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367439459 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.1367439459
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.3084135859
Short name T238
Test name
Test status
Simulation time 81713500 ps
CPU time 15.55 seconds
Started May 21 03:15:15 PM PDT 24
Finished May 21 03:15:31 PM PDT 24
Peak memory 265244 kb
Host smart-64d5e5ee-d79f-4108-9168-0eb793d6c1b1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084135859 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3084135859
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2055530206
Short name T920
Test name
Test status
Simulation time 29983200 ps
CPU time 13.46 seconds
Started May 21 03:23:37 PM PDT 24
Finished May 21 03:23:52 PM PDT 24
Peak memory 265248 kb
Host smart-37a5f900-8fcb-4f67-95ba-38d7fc5554f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055530206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2055530206
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.2011343023
Short name T1105
Test name
Test status
Simulation time 16849700 ps
CPU time 15.76 seconds
Started May 21 03:23:33 PM PDT 24
Finished May 21 03:23:50 PM PDT 24
Peak memory 275104 kb
Host smart-cbd66f9a-2c09-413b-a387-2966c3008826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011343023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2011343023
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2380631329
Short name T863
Test name
Test status
Simulation time 12828700 ps
CPU time 22.36 seconds
Started May 21 03:23:34 PM PDT 24
Finished May 21 03:23:58 PM PDT 24
Peak memory 265172 kb
Host smart-5fa9cd8f-25db-4d2f-a54d-898037788d9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380631329 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2380631329
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.453642771
Short name T980
Test name
Test status
Simulation time 47447860300 ps
CPU time 179.19 seconds
Started May 21 03:23:22 PM PDT 24
Finished May 21 03:26:23 PM PDT 24
Peak memory 262468 kb
Host smart-f7e99188-16d2-4cdc-8f77-e9375ab44544
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453642771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_h
w_sec_otp.453642771
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.204336203
Short name T809
Test name
Test status
Simulation time 6613453800 ps
CPU time 192.92 seconds
Started May 21 03:23:22 PM PDT 24
Finished May 21 03:26:36 PM PDT 24
Peak memory 289992 kb
Host smart-59359915-5c91-4cb1-b4d5-b041e5b5e86b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204336203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flas
h_ctrl_intr_rd.204336203
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1544917417
Short name T661
Test name
Test status
Simulation time 43833515400 ps
CPU time 166.53 seconds
Started May 21 03:23:23 PM PDT 24
Finished May 21 03:26:11 PM PDT 24
Peak memory 292448 kb
Host smart-823c97f7-69b9-4b98-ae0c-42620612d04d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544917417 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1544917417
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.575482659
Short name T383
Test name
Test status
Simulation time 42311300 ps
CPU time 131.58 seconds
Started May 21 03:23:26 PM PDT 24
Finished May 21 03:25:40 PM PDT 24
Peak memory 264336 kb
Host smart-baf45416-7ee1-4c8a-a7d5-81874e2a7a06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575482659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ot
p_reset.575482659
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.921442840
Short name T673
Test name
Test status
Simulation time 37153500 ps
CPU time 13.58 seconds
Started May 21 03:23:22 PM PDT 24
Finished May 21 03:23:37 PM PDT 24
Peak memory 258716 kb
Host smart-02697815-c092-4735-9488-b5ac773d828a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921442840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_res
et.921442840
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3424708620
Short name T1078
Test name
Test status
Simulation time 42177500 ps
CPU time 30.48 seconds
Started May 21 03:23:30 PM PDT 24
Finished May 21 03:24:02 PM PDT 24
Peak memory 273624 kb
Host smart-fe16a40e-9f7c-4ee0-bac6-f9892286b6eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424708620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3424708620
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.4284952835
Short name T220
Test name
Test status
Simulation time 40096400 ps
CPU time 29.13 seconds
Started May 21 03:23:28 PM PDT 24
Finished May 21 03:23:59 PM PDT 24
Peak memory 274840 kb
Host smart-be5d9127-201e-4408-a888-85dc2fc13a3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284952835 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.4284952835
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.4280053552
Short name T675
Test name
Test status
Simulation time 2807162300 ps
CPU time 68.59 seconds
Started May 21 03:23:34 PM PDT 24
Finished May 21 03:24:44 PM PDT 24
Peak memory 263036 kb
Host smart-b8c6e21a-7741-4a7e-95b1-e55e1308d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280053552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.4280053552
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.740216359
Short name T404
Test name
Test status
Simulation time 49377600 ps
CPU time 76.73 seconds
Started May 21 03:23:26 PM PDT 24
Finished May 21 03:24:45 PM PDT 24
Peak memory 276036 kb
Host smart-d5810560-79a7-4f3b-b784-613fa1f804eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740216359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.740216359
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2681443748
Short name T626
Test name
Test status
Simulation time 135557400 ps
CPU time 14.21 seconds
Started May 21 03:23:43 PM PDT 24
Finished May 21 03:23:58 PM PDT 24
Peak memory 265196 kb
Host smart-7a6f30d6-fa53-422c-b9b5-9d08b8485471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681443748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2681443748
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.389573737
Short name T722
Test name
Test status
Simulation time 16221600 ps
CPU time 16.14 seconds
Started May 21 03:23:40 PM PDT 24
Finished May 21 03:23:56 PM PDT 24
Peak memory 274908 kb
Host smart-d0bc841f-fd6c-4649-ab1b-c545af638558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389573737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.389573737
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.331275024
Short name T1024
Test name
Test status
Simulation time 117443200 ps
CPU time 22.71 seconds
Started May 21 03:23:41 PM PDT 24
Finished May 21 03:24:06 PM PDT 24
Peak memory 265212 kb
Host smart-400009c3-3eac-4cd4-be70-f89634928da6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331275024 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.331275024
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1376935673
Short name T463
Test name
Test status
Simulation time 1977937100 ps
CPU time 39.37 seconds
Started May 21 03:23:37 PM PDT 24
Finished May 21 03:24:17 PM PDT 24
Peak memory 262644 kb
Host smart-81f56820-9a3b-4600-a80a-0043e91127fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376935673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1376935673
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.357480449
Short name T968
Test name
Test status
Simulation time 6196473900 ps
CPU time 204.41 seconds
Started May 21 03:23:36 PM PDT 24
Finished May 21 03:27:01 PM PDT 24
Peak memory 289852 kb
Host smart-7aa95806-4272-4c02-9bdc-18892e9ad411
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357480449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_intr_rd.357480449
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.558335088
Short name T319
Test name
Test status
Simulation time 49069101300 ps
CPU time 307.32 seconds
Started May 21 03:23:33 PM PDT 24
Finished May 21 03:28:42 PM PDT 24
Peak memory 291768 kb
Host smart-75f2257b-e7fd-4b1c-964f-27e50cf75946
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558335088 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.558335088
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3832177279
Short name T529
Test name
Test status
Simulation time 18506700 ps
CPU time 13.6 seconds
Started May 21 03:23:35 PM PDT 24
Finished May 21 03:23:50 PM PDT 24
Peak memory 258864 kb
Host smart-a854767f-d5dc-4f53-87fc-964b2432ae26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832177279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3832177279
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2628875730
Short name T838
Test name
Test status
Simulation time 1675586900 ps
CPU time 79.65 seconds
Started May 21 03:23:41 PM PDT 24
Finished May 21 03:25:02 PM PDT 24
Peak memory 262884 kb
Host smart-55c019ae-137c-466c-8668-775d2d0e27d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628875730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2628875730
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.143989483
Short name T918
Test name
Test status
Simulation time 29841900 ps
CPU time 52.11 seconds
Started May 21 03:23:33 PM PDT 24
Finished May 21 03:24:26 PM PDT 24
Peak memory 270744 kb
Host smart-0005e5ab-3627-4c7d-aada-40109178b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143989483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.143989483
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.884337200
Short name T1081
Test name
Test status
Simulation time 139250100 ps
CPU time 13.85 seconds
Started May 21 03:23:48 PM PDT 24
Finished May 21 03:24:06 PM PDT 24
Peak memory 265368 kb
Host smart-2c20e99f-7801-4fa5-b69f-9fc8d959d91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884337200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.884337200
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3489643443
Short name T699
Test name
Test status
Simulation time 27500300 ps
CPU time 13.37 seconds
Started May 21 03:23:46 PM PDT 24
Finished May 21 03:24:02 PM PDT 24
Peak memory 275940 kb
Host smart-c2a7a542-313e-474c-b1d5-268d30320410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489643443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3489643443
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.4172780081
Short name T495
Test name
Test status
Simulation time 10288800 ps
CPU time 22.22 seconds
Started May 21 03:23:47 PM PDT 24
Finished May 21 03:24:13 PM PDT 24
Peak memory 273644 kb
Host smart-a97c170c-0841-4731-9aa0-0cca241f2ab5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172780081 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.4172780081
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.237035717
Short name T172
Test name
Test status
Simulation time 4952067200 ps
CPU time 94.46 seconds
Started May 21 03:23:40 PM PDT 24
Finished May 21 03:25:15 PM PDT 24
Peak memory 262656 kb
Host smart-001716df-3381-40e6-a9ea-ca4fe4879454
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237035717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_h
w_sec_otp.237035717
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.1471784510
Short name T33
Test name
Test status
Simulation time 2543572400 ps
CPU time 131.01 seconds
Started May 21 03:23:41 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 294100 kb
Host smart-0cab9192-bbba-4add-bbe2-eee7dc1a4413
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471784510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.1471784510
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.3068770140
Short name T555
Test name
Test status
Simulation time 6997029000 ps
CPU time 145.8 seconds
Started May 21 03:23:43 PM PDT 24
Finished May 21 03:26:10 PM PDT 24
Peak memory 292048 kb
Host smart-bd0ea369-5dae-48d4-a4fe-f6f8b712a90f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068770140 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.3068770140
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2231292834
Short name T833
Test name
Test status
Simulation time 147834500 ps
CPU time 129.78 seconds
Started May 21 03:23:40 PM PDT 24
Finished May 21 03:25:51 PM PDT 24
Peak memory 259992 kb
Host smart-4ecf0ca7-4b6c-4f8d-9fc9-0c3cd5234319
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231292834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2231292834
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2878406683
Short name T572
Test name
Test status
Simulation time 14029087900 ps
CPU time 203.65 seconds
Started May 21 03:23:41 PM PDT 24
Finished May 21 03:27:06 PM PDT 24
Peak memory 259616 kb
Host smart-2a23c462-1e09-492d-a035-bafb5fcddc4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878406683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2878406683
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2695624329
Short name T508
Test name
Test status
Simulation time 29919300 ps
CPU time 32.06 seconds
Started May 21 03:23:48 PM PDT 24
Finished May 21 03:24:24 PM PDT 24
Peak memory 275788 kb
Host smart-23b2be04-eb25-4a1b-9c0b-16f625bf5a47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695624329 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2695624329
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.305567370
Short name T547
Test name
Test status
Simulation time 1968828700 ps
CPU time 60.94 seconds
Started May 21 03:23:46 PM PDT 24
Finished May 21 03:24:50 PM PDT 24
Peak memory 263228 kb
Host smart-5dedfc85-6f64-4c35-a0e9-581d1d7b4168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305567370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.305567370
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3338142808
Short name T743
Test name
Test status
Simulation time 28490800 ps
CPU time 123.9 seconds
Started May 21 03:23:42 PM PDT 24
Finished May 21 03:25:47 PM PDT 24
Peak memory 275932 kb
Host smart-0ea9bd7e-a566-4b25-82b5-ac1b0d42a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338142808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3338142808
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.996614141
Short name T1023
Test name
Test status
Simulation time 22592300 ps
CPU time 13.96 seconds
Started May 21 03:23:59 PM PDT 24
Finished May 21 03:24:16 PM PDT 24
Peak memory 265188 kb
Host smart-55ba361a-ae5b-4703-9830-84ec811a8682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996614141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.996614141
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3446075385
Short name T763
Test name
Test status
Simulation time 69425100 ps
CPU time 13.24 seconds
Started May 21 03:23:59 PM PDT 24
Finished May 21 03:24:16 PM PDT 24
Peak memory 275872 kb
Host smart-808566b3-c9fa-4d7b-9378-2bda50e75e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446075385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3446075385
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.352922751
Short name T679
Test name
Test status
Simulation time 20276800 ps
CPU time 22.22 seconds
Started May 21 03:23:59 PM PDT 24
Finished May 21 03:24:25 PM PDT 24
Peak memory 265308 kb
Host smart-03cf183a-73c7-4e00-bbf4-b31cc33192e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352922751 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.352922751
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.157575523
Short name T1098
Test name
Test status
Simulation time 2322274100 ps
CPU time 51.48 seconds
Started May 21 03:23:52 PM PDT 24
Finished May 21 03:24:47 PM PDT 24
Peak memory 262560 kb
Host smart-f90df94f-63f6-4612-879c-a6f3920af8d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157575523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h
w_sec_otp.157575523
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.1318556429
Short name T282
Test name
Test status
Simulation time 2819063900 ps
CPU time 242.92 seconds
Started May 21 03:23:53 PM PDT 24
Finished May 21 03:27:59 PM PDT 24
Peak memory 284184 kb
Host smart-cad67ab7-f5cf-4454-bbed-09f97069bb8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318556429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.1318556429
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.694291726
Short name T741
Test name
Test status
Simulation time 29501650100 ps
CPU time 329.23 seconds
Started May 21 03:23:52 PM PDT 24
Finished May 21 03:29:24 PM PDT 24
Peak memory 291876 kb
Host smart-01420773-bab3-433b-bc3f-452b3cb2e29f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694291726 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.694291726
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.1691476156
Short name T538
Test name
Test status
Simulation time 164609400 ps
CPU time 129.87 seconds
Started May 21 03:23:51 PM PDT 24
Finished May 21 03:26:04 PM PDT 24
Peak memory 259920 kb
Host smart-6bccaf04-4361-413f-a11d-fc147e1c894d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691476156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.1691476156
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1944935341
Short name T380
Test name
Test status
Simulation time 3925367200 ps
CPU time 176.84 seconds
Started May 21 03:23:51 PM PDT 24
Finished May 21 03:26:51 PM PDT 24
Peak memory 264688 kb
Host smart-f4e02697-d29c-49ed-8365-7a54afc677ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944935341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1944935341
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1195702910
Short name T507
Test name
Test status
Simulation time 31433900 ps
CPU time 33.18 seconds
Started May 21 03:24:00 PM PDT 24
Finished May 21 03:24:36 PM PDT 24
Peak memory 272660 kb
Host smart-69be5d52-f47b-4009-b44e-0e20ebbf2bae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195702910 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1195702910
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.487601356
Short name T369
Test name
Test status
Simulation time 1557875000 ps
CPU time 74.98 seconds
Started May 21 03:23:57 PM PDT 24
Finished May 21 03:25:16 PM PDT 24
Peak memory 263012 kb
Host smart-feec3e98-8334-48bd-b72f-dadded29ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487601356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.487601356
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.2890398682
Short name T436
Test name
Test status
Simulation time 32201800 ps
CPU time 96.8 seconds
Started May 21 03:23:47 PM PDT 24
Finished May 21 03:25:27 PM PDT 24
Peak memory 277088 kb
Host smart-0af1f5ec-8c78-44b7-98ee-6a7b6b44d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890398682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2890398682
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3608268377
Short name T780
Test name
Test status
Simulation time 48298500 ps
CPU time 13.66 seconds
Started May 21 03:24:01 PM PDT 24
Finished May 21 03:24:18 PM PDT 24
Peak memory 265236 kb
Host smart-76cde02f-3d31-4627-82a2-8ef2af585049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608268377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3608268377
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3285336
Short name T1011
Test name
Test status
Simulation time 19691300 ps
CPU time 16.21 seconds
Started May 21 03:24:03 PM PDT 24
Finished May 21 03:24:22 PM PDT 24
Peak memory 275120 kb
Host smart-3bb31da1-c1da-409e-802a-ffb43568bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3285336
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.4010179379
Short name T711
Test name
Test status
Simulation time 90644900 ps
CPU time 21.8 seconds
Started May 21 03:24:03 PM PDT 24
Finished May 21 03:24:27 PM PDT 24
Peak memory 265328 kb
Host smart-aa11d1ca-8165-4249-a8d4-2b1c43d62fac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010179379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.4010179379
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1359487902
Short name T1027
Test name
Test status
Simulation time 1813455100 ps
CPU time 153.38 seconds
Started May 21 03:23:58 PM PDT 24
Finished May 21 03:26:35 PM PDT 24
Peak memory 262556 kb
Host smart-e308642a-62b1-4c11-ac4e-0f259f37bfed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359487902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1359487902
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1799332550
Short name T519
Test name
Test status
Simulation time 27590811300 ps
CPU time 131.27 seconds
Started May 21 03:24:03 PM PDT 24
Finished May 21 03:26:16 PM PDT 24
Peak memory 292032 kb
Host smart-2c953cf1-e3de-4b9f-954d-66e0a5b6f9ed
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799332550 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.1799332550
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.4124695987
Short name T1044
Test name
Test status
Simulation time 599304200 ps
CPU time 132.94 seconds
Started May 21 03:24:01 PM PDT 24
Finished May 21 03:26:17 PM PDT 24
Peak memory 259800 kb
Host smart-a9ea8ea0-d870-4c20-b5cc-29c85f1a5303
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124695987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.4124695987
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.1481102
Short name T756
Test name
Test status
Simulation time 76703000 ps
CPU time 13.92 seconds
Started May 21 03:24:02 PM PDT 24
Finished May 21 03:24:18 PM PDT 24
Peak memory 265256 kb
Host smart-f3f1b8de-f5bd-44a9-95c7-268b4fe643c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.1481102
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.3271880818
Short name T906
Test name
Test status
Simulation time 31609400 ps
CPU time 32 seconds
Started May 21 03:24:02 PM PDT 24
Finished May 21 03:24:37 PM PDT 24
Peak memory 274604 kb
Host smart-9f938d42-1230-4b46-b5ab-da0a5eecf72f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271880818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.3271880818
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2570774337
Short name T907
Test name
Test status
Simulation time 33633000 ps
CPU time 32.07 seconds
Started May 21 03:24:01 PM PDT 24
Finished May 21 03:24:36 PM PDT 24
Peak memory 274868 kb
Host smart-917fc1a5-9448-4321-a6ef-48b0d9eeeed0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570774337 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2570774337
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.592146573
Short name T32
Test name
Test status
Simulation time 6747016600 ps
CPU time 65.29 seconds
Started May 21 03:24:03 PM PDT 24
Finished May 21 03:25:10 PM PDT 24
Peak memory 264612 kb
Host smart-52e17c34-4f89-4e38-9c80-03624c7b9606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592146573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.592146573
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.4233636816
Short name T1001
Test name
Test status
Simulation time 55372100 ps
CPU time 121.24 seconds
Started May 21 03:23:58 PM PDT 24
Finished May 21 03:26:03 PM PDT 24
Peak memory 275828 kb
Host smart-c153d896-a9e5-4e3f-8160-d62559c16cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233636816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.4233636816
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.397996102
Short name T631
Test name
Test status
Simulation time 57328600 ps
CPU time 13.38 seconds
Started May 21 03:24:20 PM PDT 24
Finished May 21 03:24:35 PM PDT 24
Peak memory 265240 kb
Host smart-dac25033-9ae7-444c-ad5c-a0230351da3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397996102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.397996102
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.230479724
Short name T90
Test name
Test status
Simulation time 104375100 ps
CPU time 15.91 seconds
Started May 21 03:24:18 PM PDT 24
Finished May 21 03:24:35 PM PDT 24
Peak memory 275688 kb
Host smart-924e13c7-5b58-498a-a8e0-903344ac1940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230479724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.230479724
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.2893209786
Short name T274
Test name
Test status
Simulation time 29099100 ps
CPU time 21.55 seconds
Started May 21 03:24:16 PM PDT 24
Finished May 21 03:24:38 PM PDT 24
Peak memory 265252 kb
Host smart-8bef7238-ec0b-4c73-b83c-fb1217bad4fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893209786 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.2893209786
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1795963185
Short name T805
Test name
Test status
Simulation time 689923800 ps
CPU time 42.97 seconds
Started May 21 03:24:10 PM PDT 24
Finished May 21 03:24:53 PM PDT 24
Peak memory 262504 kb
Host smart-c5bd779c-dac7-44cc-b98f-cced78d3096c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795963185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1795963185
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.3279974496
Short name T1014
Test name
Test status
Simulation time 13617175900 ps
CPU time 205.03 seconds
Started May 21 03:24:07 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 289928 kb
Host smart-9cd65669-cb82-40cb-8937-31882be63256
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279974496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.3279974496
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.640473048
Short name T431
Test name
Test status
Simulation time 24306945900 ps
CPU time 259.35 seconds
Started May 21 03:24:13 PM PDT 24
Finished May 21 03:28:34 PM PDT 24
Peak memory 289864 kb
Host smart-5c247383-ba2d-4646-8d12-7b50fec80653
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640473048 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.640473048
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.601880685
Short name T148
Test name
Test status
Simulation time 36741400 ps
CPU time 113.54 seconds
Started May 21 03:24:07 PM PDT 24
Finished May 21 03:26:02 PM PDT 24
Peak memory 264784 kb
Host smart-fa9cd7d5-762a-44cc-ab0e-474637c73bc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601880685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ot
p_reset.601880685
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3962867910
Short name T403
Test name
Test status
Simulation time 233176300 ps
CPU time 21.93 seconds
Started May 21 03:24:14 PM PDT 24
Finished May 21 03:24:37 PM PDT 24
Peak memory 259780 kb
Host smart-302a39fc-0935-4db3-947b-e51101270962
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962867910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3962867910
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.1539293907
Short name T396
Test name
Test status
Simulation time 39411200 ps
CPU time 33.32 seconds
Started May 21 03:24:14 PM PDT 24
Finished May 21 03:24:48 PM PDT 24
Peak memory 275620 kb
Host smart-47cf2b2a-8f54-47b0-851a-933e6a0199b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539293907 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.1539293907
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.814391679
Short name T960
Test name
Test status
Simulation time 1743637300 ps
CPU time 63.61 seconds
Started May 21 03:24:14 PM PDT 24
Finished May 21 03:25:19 PM PDT 24
Peak memory 262968 kb
Host smart-dcb6d08b-c2ac-4384-a58c-f8870335a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814391679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.814391679
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.10670800
Short name T966
Test name
Test status
Simulation time 52116000 ps
CPU time 145.92 seconds
Started May 21 03:24:02 PM PDT 24
Finished May 21 03:26:31 PM PDT 24
Peak memory 276432 kb
Host smart-1c5c7547-f7e8-475b-a9c7-b916ba5ccbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10670800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.10670800
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.2574370199
Short name T714
Test name
Test status
Simulation time 73330600 ps
CPU time 14.11 seconds
Started May 21 03:24:26 PM PDT 24
Finished May 21 03:24:41 PM PDT 24
Peak memory 265156 kb
Host smart-ce242654-c893-4ee1-9008-9054e2a91b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574370199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
2574370199
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.2451865750
Short name T757
Test name
Test status
Simulation time 46729000 ps
CPU time 13.67 seconds
Started May 21 03:24:26 PM PDT 24
Finished May 21 03:24:41 PM PDT 24
Peak memory 275164 kb
Host smart-75c914ab-e92e-46f0-8c0b-bc70e8edaa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451865750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2451865750
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2940876312
Short name T1033
Test name
Test status
Simulation time 22696000 ps
CPU time 21.01 seconds
Started May 21 03:24:33 PM PDT 24
Finished May 21 03:24:55 PM PDT 24
Peak memory 265272 kb
Host smart-9365c542-2a71-4ce1-bd4f-7f3a04d754ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940876312 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2940876312
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3232903431
Short name T753
Test name
Test status
Simulation time 5971184900 ps
CPU time 62.84 seconds
Started May 21 03:24:20 PM PDT 24
Finished May 21 03:25:24 PM PDT 24
Peak memory 262480 kb
Host smart-673d2e15-6359-4f09-a970-7a2a9fc637f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232903431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3232903431
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.1091491081
Short name T279
Test name
Test status
Simulation time 1758098200 ps
CPU time 225.35 seconds
Started May 21 03:24:21 PM PDT 24
Finished May 21 03:28:08 PM PDT 24
Peak memory 289916 kb
Host smart-bfd364ca-217e-46ad-9c64-e712c558d306
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091491081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.1091491081
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.878362644
Short name T846
Test name
Test status
Simulation time 24997424600 ps
CPU time 359.75 seconds
Started May 21 03:24:19 PM PDT 24
Finished May 21 03:30:20 PM PDT 24
Peak memory 292172 kb
Host smart-dda8f681-6e30-45e5-8a47-5fdd5e4cf322
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878362644 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.878362644
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.866592251
Short name T137
Test name
Test status
Simulation time 35648400 ps
CPU time 110 seconds
Started May 21 03:24:20 PM PDT 24
Finished May 21 03:26:11 PM PDT 24
Peak memory 264924 kb
Host smart-e3118e67-740b-414b-aa2c-715bb2fdb43c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866592251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.866592251
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.4038563333
Short name T377
Test name
Test status
Simulation time 19974100 ps
CPU time 13.51 seconds
Started May 21 03:24:32 PM PDT 24
Finished May 21 03:24:46 PM PDT 24
Peak memory 258672 kb
Host smart-60091a06-97cd-4a18-a7a7-fa0c8e9f88af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038563333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.4038563333
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1003014415
Short name T733
Test name
Test status
Simulation time 70722000 ps
CPU time 28.99 seconds
Started May 21 03:24:34 PM PDT 24
Finished May 21 03:25:04 PM PDT 24
Peak memory 274916 kb
Host smart-523cce16-1973-49be-b5fe-94fb3c94dccc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003014415 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1003014415
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3375128548
Short name T644
Test name
Test status
Simulation time 391935600 ps
CPU time 54.68 seconds
Started May 21 03:24:28 PM PDT 24
Finished May 21 03:25:24 PM PDT 24
Peak memory 263224 kb
Host smart-557f8ddc-59f8-4233-ad9a-dc3fa6389bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375128548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3375128548
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.1830589173
Short name T106
Test name
Test status
Simulation time 31239000 ps
CPU time 97.06 seconds
Started May 21 03:24:20 PM PDT 24
Finished May 21 03:25:59 PM PDT 24
Peak memory 275524 kb
Host smart-a099857c-f3c9-45ef-ade8-d0cfc1c6752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830589173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1830589173
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.2465782729
Short name T781
Test name
Test status
Simulation time 40560600 ps
CPU time 13.79 seconds
Started May 21 03:24:32 PM PDT 24
Finished May 21 03:24:47 PM PDT 24
Peak memory 264636 kb
Host smart-beebc55e-dee9-4c33-9431-e26b91fb56ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465782729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
2465782729
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2536391622
Short name T450
Test name
Test status
Simulation time 20355300 ps
CPU time 15.74 seconds
Started May 21 03:24:30 PM PDT 24
Finished May 21 03:24:48 PM PDT 24
Peak memory 275688 kb
Host smart-dc9d9ab1-8ae0-4d05-9b4a-9949f13aef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536391622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2536391622
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2414360337
Short name T824
Test name
Test status
Simulation time 36457200 ps
CPU time 22.03 seconds
Started May 21 03:24:23 PM PDT 24
Finished May 21 03:24:47 PM PDT 24
Peak memory 265352 kb
Host smart-55e0b7ec-1089-4dfa-8ca3-03b2fc72e497
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414360337 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2414360337
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3738811677
Short name T484
Test name
Test status
Simulation time 12666146200 ps
CPU time 149.38 seconds
Started May 21 03:24:33 PM PDT 24
Finished May 21 03:27:03 PM PDT 24
Peak memory 262544 kb
Host smart-68c72b3a-d9af-4afa-a332-073f524ab78a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738811677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3738811677
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.622271135
Short name T1016
Test name
Test status
Simulation time 6147577700 ps
CPU time 213.44 seconds
Started May 21 03:24:23 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 284100 kb
Host smart-81734eb5-9719-4ed0-be19-0fdda35945c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622271135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flas
h_ctrl_intr_rd.622271135
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1674050702
Short name T174
Test name
Test status
Simulation time 18228316800 ps
CPU time 289.3 seconds
Started May 21 03:24:33 PM PDT 24
Finished May 21 03:29:23 PM PDT 24
Peak memory 292224 kb
Host smart-78845c64-84a7-4236-8890-c2ab84488f87
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674050702 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1674050702
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.3287315702
Short name T612
Test name
Test status
Simulation time 152432500 ps
CPU time 110.96 seconds
Started May 21 03:24:25 PM PDT 24
Finished May 21 03:26:17 PM PDT 24
Peak memory 261052 kb
Host smart-32a25a89-4c16-4219-8405-cc5b2ed1804d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287315702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.3287315702
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.244796649
Short name T771
Test name
Test status
Simulation time 62387900 ps
CPU time 13.44 seconds
Started May 21 03:24:34 PM PDT 24
Finished May 21 03:24:49 PM PDT 24
Peak memory 258764 kb
Host smart-95374b2e-c404-44a8-98b1-c60f3d501553
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244796649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.244796649
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.2789824079
Short name T962
Test name
Test status
Simulation time 430933100 ps
CPU time 54.57 seconds
Started May 21 03:24:26 PM PDT 24
Finished May 21 03:25:22 PM PDT 24
Peak memory 261672 kb
Host smart-b43bd209-eeb7-49b6-ac0a-a4f85e10cab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789824079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2789824079
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.906565166
Short name T969
Test name
Test status
Simulation time 56006800 ps
CPU time 51.65 seconds
Started May 21 03:24:25 PM PDT 24
Finished May 21 03:25:18 PM PDT 24
Peak memory 270704 kb
Host smart-1a3a2211-1c3a-4b45-9298-731e89c31cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906565166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.906565166
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.3710882103
Short name T724
Test name
Test status
Simulation time 65120500 ps
CPU time 15.53 seconds
Started May 21 03:24:36 PM PDT 24
Finished May 21 03:24:54 PM PDT 24
Peak memory 275688 kb
Host smart-e5497c10-3ffc-4ebe-bdff-603df68caa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710882103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3710882103
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.4168311807
Short name T364
Test name
Test status
Simulation time 22605800 ps
CPU time 22.28 seconds
Started May 21 03:24:38 PM PDT 24
Finished May 21 03:25:02 PM PDT 24
Peak memory 265400 kb
Host smart-c6f81504-62cd-4a1a-b7c3-af361f9d93e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168311807 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.4168311807
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3544944094
Short name T1015
Test name
Test status
Simulation time 4347028200 ps
CPU time 133.98 seconds
Started May 21 03:24:32 PM PDT 24
Finished May 21 03:26:47 PM PDT 24
Peak memory 262712 kb
Host smart-f09ed734-3b1b-4527-b3f1-738c4ef1e987
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544944094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3544944094
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1672522717
Short name T506
Test name
Test status
Simulation time 5955963300 ps
CPU time 135.67 seconds
Started May 21 03:24:36 PM PDT 24
Finished May 21 03:26:53 PM PDT 24
Peak memory 292084 kb
Host smart-2af6af6e-dc85-4929-9b2e-46602cb4985b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672522717 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1672522717
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.40551755
Short name T666
Test name
Test status
Simulation time 83110700 ps
CPU time 135.8 seconds
Started May 21 03:24:32 PM PDT 24
Finished May 21 03:26:49 PM PDT 24
Peak memory 263620 kb
Host smart-5dd59d39-0418-43c3-a182-a386967e6e7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40551755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp
_reset.40551755
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3250349329
Short name T917
Test name
Test status
Simulation time 45006800 ps
CPU time 14.08 seconds
Started May 21 03:24:37 PM PDT 24
Finished May 21 03:24:52 PM PDT 24
Peak memory 258536 kb
Host smart-dfb99541-a44a-4255-b082-4a4c24a16790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250349329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.3250349329
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1309411487
Short name T541
Test name
Test status
Simulation time 76206200 ps
CPU time 32.23 seconds
Started May 21 03:24:35 PM PDT 24
Finished May 21 03:25:09 PM PDT 24
Peak memory 275612 kb
Host smart-8582f167-17ef-4eae-a96b-c2c366304d7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309411487 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1309411487
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3189924792
Short name T372
Test name
Test status
Simulation time 620025100 ps
CPU time 73.52 seconds
Started May 21 03:24:39 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 263092 kb
Host smart-62fdb9eb-ff57-422c-af53-1860b72284e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189924792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3189924792
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.212700656
Short name T970
Test name
Test status
Simulation time 113351800 ps
CPU time 49.18 seconds
Started May 21 03:24:30 PM PDT 24
Finished May 21 03:25:21 PM PDT 24
Peak memory 270672 kb
Host smart-8297e0fa-3171-47af-a51b-765bee2096fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212700656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.212700656
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3076421952
Short name T600
Test name
Test status
Simulation time 32357500 ps
CPU time 13.91 seconds
Started May 21 03:24:42 PM PDT 24
Finished May 21 03:24:57 PM PDT 24
Peak memory 265172 kb
Host smart-fed1d844-54a6-4c21-85fb-c885f24d1b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076421952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3076421952
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.3685589009
Short name T681
Test name
Test status
Simulation time 14442200 ps
CPU time 15.63 seconds
Started May 21 03:24:40 PM PDT 24
Finished May 21 03:24:57 PM PDT 24
Peak memory 276088 kb
Host smart-48a7d275-d709-4776-8574-ab072bf5da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685589009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3685589009
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.1439626996
Short name T366
Test name
Test status
Simulation time 26259000 ps
CPU time 21.34 seconds
Started May 21 03:24:40 PM PDT 24
Finished May 21 03:25:02 PM PDT 24
Peak memory 265316 kb
Host smart-09aaf8ff-6ae4-4203-b889-bec0e6c3a724
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439626996 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.1439626996
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3966487312
Short name T465
Test name
Test status
Simulation time 12450403500 ps
CPU time 127.29 seconds
Started May 21 03:24:37 PM PDT 24
Finished May 21 03:26:46 PM PDT 24
Peak memory 262524 kb
Host smart-94e28dac-c651-4f1a-9d97-8078d12462e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966487312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3966487312
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2633342815
Short name T947
Test name
Test status
Simulation time 2911532700 ps
CPU time 191.61 seconds
Started May 21 03:24:42 PM PDT 24
Finished May 21 03:27:55 PM PDT 24
Peak memory 284128 kb
Host smart-abe3a37e-1747-436f-b943-423c1f353681
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633342815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2633342815
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.374840470
Short name T832
Test name
Test status
Simulation time 40908393100 ps
CPU time 133.11 seconds
Started May 21 03:24:41 PM PDT 24
Finished May 21 03:26:56 PM PDT 24
Peak memory 292580 kb
Host smart-d0b2b008-7bfa-4352-aed9-ba55bd82a234
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374840470 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.374840470
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3887929898
Short name T1064
Test name
Test status
Simulation time 2253274200 ps
CPU time 179.56 seconds
Started May 21 03:24:41 PM PDT 24
Finished May 21 03:27:42 PM PDT 24
Peak memory 259564 kb
Host smart-bec4a881-199f-4920-97bd-3d644832dc43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887929898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3887929898
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1860444251
Short name T998
Test name
Test status
Simulation time 29836600 ps
CPU time 31.45 seconds
Started May 21 03:24:42 PM PDT 24
Finished May 21 03:25:14 PM PDT 24
Peak memory 273580 kb
Host smart-812ae81c-0c56-465c-8bed-0b78ef5cf5f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860444251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1860444251
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3189756851
Short name T758
Test name
Test status
Simulation time 30179800 ps
CPU time 30.55 seconds
Started May 21 03:24:39 PM PDT 24
Finished May 21 03:25:11 PM PDT 24
Peak memory 275632 kb
Host smart-7999d14c-02f5-4b45-bb31-9a8e7478d73a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189756851 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3189756851
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.1085396190
Short name T697
Test name
Test status
Simulation time 69393800 ps
CPU time 51.47 seconds
Started May 21 03:24:34 PM PDT 24
Finished May 21 03:25:27 PM PDT 24
Peak memory 270704 kb
Host smart-b5632e8e-75fe-4511-a27d-c77aa9c433a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085396190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1085396190
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.3003594727
Short name T461
Test name
Test status
Simulation time 84305000 ps
CPU time 13.52 seconds
Started May 21 03:16:24 PM PDT 24
Finished May 21 03:16:39 PM PDT 24
Peak memory 265188 kb
Host smart-62b443bc-2c92-4505-87a5-d8e2957c5958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003594727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3
003594727
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.574003153
Short name T259
Test name
Test status
Simulation time 22059400 ps
CPU time 14.01 seconds
Started May 21 03:16:24 PM PDT 24
Finished May 21 03:16:39 PM PDT 24
Peak memory 261672 kb
Host smart-9418f78a-943c-4be1-94fd-e7ec5b1f590c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574003153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.574003153
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.1276990260
Short name T563
Test name
Test status
Simulation time 58421600 ps
CPU time 15.88 seconds
Started May 21 03:16:21 PM PDT 24
Finished May 21 03:16:37 PM PDT 24
Peak memory 276076 kb
Host smart-88b93809-1678-4e9d-b97e-743e971e58c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276990260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1276990260
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.3663597585
Short name T754
Test name
Test status
Simulation time 358078800 ps
CPU time 108.9 seconds
Started May 21 03:16:22 PM PDT 24
Finished May 21 03:18:12 PM PDT 24
Peak memory 281496 kb
Host smart-854c0d2c-44c2-4f80-87af-7ce80258d9ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663597585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.3663597585
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.1876734506
Short name T359
Test name
Test status
Simulation time 10486400 ps
CPU time 22 seconds
Started May 21 03:16:19 PM PDT 24
Finished May 21 03:16:41 PM PDT 24
Peak memory 273612 kb
Host smart-86be5465-da09-4958-b410-458fc972d564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876734506 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.1876734506
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.4142440983
Short name T122
Test name
Test status
Simulation time 11590673800 ps
CPU time 342.7 seconds
Started May 21 03:15:50 PM PDT 24
Finished May 21 03:21:33 PM PDT 24
Peak memory 263104 kb
Host smart-c41b9609-191f-45c8-8ec5-30716b273acf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142440983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.4142440983
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.1752764021
Short name T898
Test name
Test status
Simulation time 4029333100 ps
CPU time 2276.5 seconds
Started May 21 03:16:02 PM PDT 24
Finished May 21 03:53:59 PM PDT 24
Peak memory 264868 kb
Host smart-e503c1e9-b702-46a1-a9ec-2cae926fd4af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752764021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.1752764021
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.1137112211
Short name T774
Test name
Test status
Simulation time 776670100 ps
CPU time 2675.48 seconds
Started May 21 03:15:52 PM PDT 24
Finished May 21 04:00:29 PM PDT 24
Peak memory 265188 kb
Host smart-33523385-8948-4d8b-b8cd-fd04d2e6d261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137112211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1137112211
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1745288920
Short name T778
Test name
Test status
Simulation time 1518715300 ps
CPU time 939.46 seconds
Started May 21 03:15:55 PM PDT 24
Finished May 21 03:31:35 PM PDT 24
Peak memory 273368 kb
Host smart-9b96e5bb-3bae-411e-bb0c-68c436014e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745288920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1745288920
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3979581941
Short name T44
Test name
Test status
Simulation time 6464310400 ps
CPU time 30.15 seconds
Started May 21 03:15:44 PM PDT 24
Finished May 21 03:16:15 PM PDT 24
Peak memory 265232 kb
Host smart-666e9d5e-6d13-44bd-a673-6c52e0fbc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979581941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3979581941
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2171029164
Short name T911
Test name
Test status
Simulation time 358091800 ps
CPU time 36.79 seconds
Started May 21 03:16:34 PM PDT 24
Finished May 21 03:17:12 PM PDT 24
Peak memory 262144 kb
Host smart-07947f2d-9117-48dc-9e9f-ec270d36a00b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171029164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2171029164
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.837655522
Short name T850
Test name
Test status
Simulation time 191071476100 ps
CPU time 2858.73 seconds
Started May 21 03:15:57 PM PDT 24
Finished May 21 04:03:37 PM PDT 24
Peak memory 265024 kb
Host smart-b82c8f9f-d83f-43b6-b46e-4ddf7e4fea1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837655522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_full_mem_access.837655522
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3534930774
Short name T1090
Test name
Test status
Simulation time 44348300 ps
CPU time 37.5 seconds
Started May 21 03:15:48 PM PDT 24
Finished May 21 03:16:26 PM PDT 24
Peak memory 264592 kb
Host smart-a9a7e980-46d2-44b4-b2ee-51308880bf73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534930774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3534930774
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2623725114
Short name T976
Test name
Test status
Simulation time 135222700 ps
CPU time 13.67 seconds
Started May 21 03:16:25 PM PDT 24
Finished May 21 03:16:40 PM PDT 24
Peak memory 265332 kb
Host smart-1e520be7-b6c1-454a-a5e2-82ff9fab0564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623725114 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2623725114
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2300020754
Short name T168
Test name
Test status
Simulation time 160187914000 ps
CPU time 982.9 seconds
Started May 21 03:15:40 PM PDT 24
Finished May 21 03:32:04 PM PDT 24
Peak memory 263236 kb
Host smart-edfc8885-a486-4690-a5f2-23a11fee6bde
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300020754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.2300020754
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.194157841
Short name T524
Test name
Test status
Simulation time 4480725900 ps
CPU time 122.89 seconds
Started May 21 03:15:59 PM PDT 24
Finished May 21 03:18:03 PM PDT 24
Peak memory 262516 kb
Host smart-2023a81a-6585-430f-9dc6-aa5e0a63b4c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194157841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw
_sec_otp.194157841
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2849563962
Short name T564
Test name
Test status
Simulation time 2954456500 ps
CPU time 123.62 seconds
Started May 21 03:16:27 PM PDT 24
Finished May 21 03:18:33 PM PDT 24
Peak memory 292224 kb
Host smart-a6018a59-8f47-47f9-90d3-c258d30b9a46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849563962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2849563962
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1292162896
Short name T799
Test name
Test status
Simulation time 24387958600 ps
CPU time 300.5 seconds
Started May 21 03:16:35 PM PDT 24
Finished May 21 03:21:36 PM PDT 24
Peak memory 289844 kb
Host smart-82b8e075-dbba-4242-9f84-40048815cef4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292162896 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1292162896
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3782883832
Short name T817
Test name
Test status
Simulation time 8946928800 ps
CPU time 64.67 seconds
Started May 21 03:16:27 PM PDT 24
Finished May 21 03:17:34 PM PDT 24
Peak memory 265168 kb
Host smart-e4bd44ef-db4f-493f-bc13-0458658234a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782883832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3782883832
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3173455906
Short name T963
Test name
Test status
Simulation time 79825021700 ps
CPU time 195.83 seconds
Started May 21 03:16:27 PM PDT 24
Finished May 21 03:19:45 PM PDT 24
Peak memory 259628 kb
Host smart-6ef6c138-eec6-43c7-8f9f-270f56ba8718
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317
3455906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3173455906
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.1769159585
Short name T407
Test name
Test status
Simulation time 2078351600 ps
CPU time 75.74 seconds
Started May 21 03:15:44 PM PDT 24
Finished May 21 03:17:01 PM PDT 24
Peak memory 260740 kb
Host smart-d14706ca-7275-4555-beba-c8a613a11c38
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769159585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1769159585
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.301295680
Short name T593
Test name
Test status
Simulation time 15165800 ps
CPU time 13.44 seconds
Started May 21 03:16:49 PM PDT 24
Finished May 21 03:17:04 PM PDT 24
Peak memory 265272 kb
Host smart-c507fa5a-d494-4627-aef7-4a6bcd873ea3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301295680 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.301295680
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1780186266
Short name T652
Test name
Test status
Simulation time 1742168700 ps
CPU time 162.07 seconds
Started May 21 03:15:40 PM PDT 24
Finished May 21 03:18:23 PM PDT 24
Peak memory 262744 kb
Host smart-aa80e1e0-688d-48b9-bf8e-9b2cd366e033
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780186266 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1780186266
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.2050781006
Short name T488
Test name
Test status
Simulation time 76253700 ps
CPU time 129.83 seconds
Started May 21 03:15:59 PM PDT 24
Finished May 21 03:18:10 PM PDT 24
Peak memory 260972 kb
Host smart-2eab3777-bbef-48ac-92df-12e5d64a8411
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050781006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.2050781006
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.3836799470
Short name T559
Test name
Test status
Simulation time 6599028500 ps
CPU time 249.24 seconds
Started May 21 03:16:10 PM PDT 24
Finished May 21 03:20:20 PM PDT 24
Peak memory 281756 kb
Host smart-85af2304-d80c-49c5-9109-058b73a8702a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836799470 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.3836799470
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.478258569
Short name T922
Test name
Test status
Simulation time 199881400 ps
CPU time 14 seconds
Started May 21 03:16:32 PM PDT 24
Finished May 21 03:16:47 PM PDT 24
Peak memory 274368 kb
Host smart-722446bb-5141-4932-b54c-f4d29f9fc1d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=478258569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.478258569
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.963946937
Short name T1053
Test name
Test status
Simulation time 46195500 ps
CPU time 68.77 seconds
Started May 21 03:15:33 PM PDT 24
Finished May 21 03:16:42 PM PDT 24
Peak memory 262532 kb
Host smart-bf1c4059-04a6-4279-a81a-63002ef73be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963946937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.963946937
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.167373011
Short name T69
Test name
Test status
Simulation time 912480200 ps
CPU time 18.36 seconds
Started May 21 03:16:39 PM PDT 24
Finished May 21 03:16:59 PM PDT 24
Peak memory 264872 kb
Host smart-56ca435c-cce7-4644-85f1-a922cd1d5ce6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167373011 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.167373011
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1020953835
Short name T234
Test name
Test status
Simulation time 39435700 ps
CPU time 13.88 seconds
Started May 21 03:16:21 PM PDT 24
Finished May 21 03:16:36 PM PDT 24
Peak memory 265424 kb
Host smart-c89e89be-dd12-4a8b-ad7c-5e35809911c9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020953835 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1020953835
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3881230675
Short name T445
Test name
Test status
Simulation time 440558600 ps
CPU time 22.16 seconds
Started May 21 03:16:13 PM PDT 24
Finished May 21 03:16:36 PM PDT 24
Peak memory 265252 kb
Host smart-e87dd4f5-b53c-4a7d-9f53-c2e07d041ae8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881230675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.3881230675
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.465856667
Short name T113
Test name
Test status
Simulation time 787277900 ps
CPU time 927.68 seconds
Started May 21 03:15:33 PM PDT 24
Finished May 21 03:31:01 PM PDT 24
Peak memory 285852 kb
Host smart-8016ab99-9959-485b-a865-22232859b437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465856667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.465856667
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1242010271
Short name T211
Test name
Test status
Simulation time 201023600 ps
CPU time 103.77 seconds
Started May 21 03:15:46 PM PDT 24
Finished May 21 03:17:30 PM PDT 24
Peak memory 265140 kb
Host smart-01afa426-1881-4e70-9d0a-b69ef582ea3b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1242010271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1242010271
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.1319148840
Short name T227
Test name
Test status
Simulation time 113224500 ps
CPU time 34.25 seconds
Started May 21 03:16:19 PM PDT 24
Finished May 21 03:16:54 PM PDT 24
Peak memory 273588 kb
Host smart-4907cbaa-ba9f-41f6-86dd-eb259b2c45b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319148840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.1319148840
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2416579706
Short name T755
Test name
Test status
Simulation time 18944500 ps
CPU time 22.7 seconds
Started May 21 03:16:05 PM PDT 24
Finished May 21 03:16:29 PM PDT 24
Peak memory 265244 kb
Host smart-d186a93d-5788-45ff-8f54-b964b7ac1d83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416579706 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2416579706
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2507124181
Short name T550
Test name
Test status
Simulation time 4529359100 ps
CPU time 129.47 seconds
Started May 21 03:15:57 PM PDT 24
Finished May 21 03:18:07 PM PDT 24
Peak memory 289788 kb
Host smart-6229bdf7-c59b-41b8-a774-cb86f7556d92
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507124181 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.2507124181
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.235310355
Short name T589
Test name
Test status
Simulation time 587211700 ps
CPU time 126.73 seconds
Started May 21 03:16:12 PM PDT 24
Finished May 21 03:18:20 PM PDT 24
Peak memory 281920 kb
Host smart-4f40e105-94bf-428a-a04b-c639619e6fc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
235310355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.235310355
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.4256543481
Short name T539
Test name
Test status
Simulation time 2827741600 ps
CPU time 137.6 seconds
Started May 21 03:15:56 PM PDT 24
Finished May 21 03:18:14 PM PDT 24
Peak memory 294520 kb
Host smart-cb5fbbc9-71c6-4778-8a2f-adf363c11cb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256543481 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.4256543481
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.4032813838
Short name T428
Test name
Test status
Simulation time 14856792800 ps
CPU time 496.41 seconds
Started May 21 03:15:55 PM PDT 24
Finished May 21 03:24:12 PM PDT 24
Peak memory 313508 kb
Host smart-bed6ed61-8019-45e6-87d8-70d3624f1dbd
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032813838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.4032813838
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1240471523
Short name T750
Test name
Test status
Simulation time 43248900 ps
CPU time 31.08 seconds
Started May 21 03:16:17 PM PDT 24
Finished May 21 03:16:49 PM PDT 24
Peak memory 273572 kb
Host smart-02de17da-5d35-493e-9b3f-17a57914cd0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240471523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1240471523
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.127251153
Short name T1075
Test name
Test status
Simulation time 29655700 ps
CPU time 31.1 seconds
Started May 21 03:16:26 PM PDT 24
Finished May 21 03:16:59 PM PDT 24
Peak memory 273508 kb
Host smart-0a7f97d7-7471-4d1d-9a01-891086ce99c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127251153 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.127251153
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.1810201309
Short name T678
Test name
Test status
Simulation time 19909744700 ps
CPU time 662.65 seconds
Started May 21 03:16:08 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 312244 kb
Host smart-ea1dd519-72ea-47cf-8e7c-7cc0e345818c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810201309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.1810201309
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.3772121421
Short name T15
Test name
Test status
Simulation time 1546201900 ps
CPU time 4959.58 seconds
Started May 21 03:16:19 PM PDT 24
Finished May 21 04:39:00 PM PDT 24
Peak memory 287108 kb
Host smart-368d7e7b-8d09-496f-8b0f-124bad3e8639
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772121421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3772121421
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1197151394
Short name T367
Test name
Test status
Simulation time 621998600 ps
CPU time 71.52 seconds
Started May 21 03:16:20 PM PDT 24
Finished May 21 03:17:32 PM PDT 24
Peak memory 263260 kb
Host smart-76fe7aed-3594-4837-8002-8c51fbc8e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197151394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1197151394
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2940851636
Short name T851
Test name
Test status
Simulation time 928669300 ps
CPU time 102.07 seconds
Started May 21 03:16:04 PM PDT 24
Finished May 21 03:17:47 PM PDT 24
Peak memory 265308 kb
Host smart-0319a494-4164-4c14-847f-2dc423b81145
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940851636 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2940851636
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.2209083032
Short name T401
Test name
Test status
Simulation time 911028600 ps
CPU time 64.51 seconds
Started May 21 03:16:05 PM PDT 24
Finished May 21 03:17:10 PM PDT 24
Peak memory 273736 kb
Host smart-615cadf4-9f30-44d3-b3e4-2e8a47092e90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209083032 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.2209083032
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.706308663
Short name T39
Test name
Test status
Simulation time 713393800 ps
CPU time 172.88 seconds
Started May 21 03:15:39 PM PDT 24
Finished May 21 03:18:33 PM PDT 24
Peak memory 281552 kb
Host smart-9ba0b847-818e-4298-98ec-8e4adfdd0920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706308663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.706308663
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3094806909
Short name T471
Test name
Test status
Simulation time 55336700 ps
CPU time 26.04 seconds
Started May 21 03:15:33 PM PDT 24
Finished May 21 03:15:59 PM PDT 24
Peak memory 258964 kb
Host smart-d869cad7-7a77-45e3-baaf-ced0e228db37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094806909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3094806909
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.742838171
Short name T58
Test name
Test status
Simulation time 685008900 ps
CPU time 1010.89 seconds
Started May 21 03:16:45 PM PDT 24
Finished May 21 03:33:39 PM PDT 24
Peak memory 286548 kb
Host smart-e9af8e62-f844-4ada-95e0-fcfbc7793691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742838171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.742838171
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3610670194
Short name T489
Test name
Test status
Simulation time 41141100 ps
CPU time 26.36 seconds
Started May 21 03:15:33 PM PDT 24
Finished May 21 03:16:00 PM PDT 24
Peak memory 261448 kb
Host smart-5b6fc1e8-e796-409e-bf02-716adb8f5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610670194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3610670194
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.652723967
Short name T636
Test name
Test status
Simulation time 213718500 ps
CPU time 14.02 seconds
Started May 21 03:24:55 PM PDT 24
Finished May 21 03:25:11 PM PDT 24
Peak memory 258232 kb
Host smart-a7c374a9-b79e-44ea-abd2-5abc30cb903c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652723967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.652723967
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3167310588
Short name T913
Test name
Test status
Simulation time 15588900 ps
CPU time 15.49 seconds
Started May 21 03:24:54 PM PDT 24
Finished May 21 03:25:11 PM PDT 24
Peak memory 275676 kb
Host smart-5d780aec-f857-45fd-9925-de4a4f82806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167310588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3167310588
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2767142724
Short name T385
Test name
Test status
Simulation time 59247000 ps
CPU time 22.52 seconds
Started May 21 03:24:49 PM PDT 24
Finished May 21 03:25:12 PM PDT 24
Peak memory 273540 kb
Host smart-0ae4aded-943b-4229-8499-b0f304afd16e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767142724 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2767142724
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2437907161
Short name T561
Test name
Test status
Simulation time 11292536100 ps
CPU time 233.57 seconds
Started May 21 03:24:48 PM PDT 24
Finished May 21 03:28:43 PM PDT 24
Peak memory 262520 kb
Host smart-021e9ce5-4fda-452a-9450-08775be9aec8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437907161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.2437907161
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.255542035
Short name T281
Test name
Test status
Simulation time 1225779000 ps
CPU time 172.77 seconds
Started May 21 03:24:49 PM PDT 24
Finished May 21 03:27:42 PM PDT 24
Peak memory 293260 kb
Host smart-724b5b63-9246-4d19-b559-cd7fe025cefb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255542035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas
h_ctrl_intr_rd.255542035
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.4226352127
Short name T607
Test name
Test status
Simulation time 50324748300 ps
CPU time 265.32 seconds
Started May 21 03:24:48 PM PDT 24
Finished May 21 03:29:14 PM PDT 24
Peak memory 292400 kb
Host smart-98cf3f3e-9805-4a04-a83c-f3eb500e9b8f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226352127 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.4226352127
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3504614489
Short name T1093
Test name
Test status
Simulation time 134737200 ps
CPU time 112.21 seconds
Started May 21 03:24:47 PM PDT 24
Finished May 21 03:26:40 PM PDT 24
Peak memory 259944 kb
Host smart-08fb21eb-2d47-4ab6-a839-a765e047792b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504614489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3504614489
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2149919515
Short name T405
Test name
Test status
Simulation time 29438300 ps
CPU time 31.29 seconds
Started May 21 03:24:48 PM PDT 24
Finished May 21 03:25:20 PM PDT 24
Peak memory 273580 kb
Host smart-6582423e-fa7d-4856-a982-d634708536c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149919515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2149919515
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1954968037
Short name T819
Test name
Test status
Simulation time 29174600 ps
CPU time 28.87 seconds
Started May 21 03:24:48 PM PDT 24
Finished May 21 03:25:17 PM PDT 24
Peak memory 276496 kb
Host smart-4de4f81b-3e79-4e78-97f1-e7d7cefc1afe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954968037 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1954968037
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.710786555
Short name T31
Test name
Test status
Simulation time 5686460700 ps
CPU time 76 seconds
Started May 21 03:24:47 PM PDT 24
Finished May 21 03:26:03 PM PDT 24
Peak memory 263276 kb
Host smart-7036963a-8cf7-4e1f-99a4-c49fa95f10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710786555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.710786555
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.852037065
Short name T1054
Test name
Test status
Simulation time 59457700 ps
CPU time 48.57 seconds
Started May 21 03:24:42 PM PDT 24
Finished May 21 03:25:32 PM PDT 24
Peak memory 270684 kb
Host smart-85e19b98-6e06-48e3-b19e-4b5d916cba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852037065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.852037065
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2059292307
Short name T884
Test name
Test status
Simulation time 87441600 ps
CPU time 13.77 seconds
Started May 21 03:25:00 PM PDT 24
Finished May 21 03:25:14 PM PDT 24
Peak memory 265212 kb
Host smart-a83991c4-c684-4a99-b6e2-5ae03c665316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059292307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2059292307
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.1611469513
Short name T229
Test name
Test status
Simulation time 31490600 ps
CPU time 13.51 seconds
Started May 21 03:25:00 PM PDT 24
Finished May 21 03:25:15 PM PDT 24
Peak memory 276016 kb
Host smart-267f5f67-24f3-4bef-ac20-3bc3a4ee9517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611469513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1611469513
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1008903151
Short name T708
Test name
Test status
Simulation time 44823000 ps
CPU time 22.12 seconds
Started May 21 03:24:56 PM PDT 24
Finished May 21 03:25:20 PM PDT 24
Peak memory 265372 kb
Host smart-1a571ca3-9364-4c1f-970c-363bf839dda7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008903151 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1008903151
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.397790079
Short name T397
Test name
Test status
Simulation time 2573719900 ps
CPU time 77.75 seconds
Started May 21 03:24:53 PM PDT 24
Finished May 21 03:26:12 PM PDT 24
Peak memory 262656 kb
Host smart-54599710-ceb2-4a8e-b34b-b9b20fde2662
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397790079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h
w_sec_otp.397790079
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.607546331
Short name T231
Test name
Test status
Simulation time 535042300 ps
CPU time 117.72 seconds
Started May 21 03:24:55 PM PDT 24
Finished May 21 03:26:54 PM PDT 24
Peak memory 294300 kb
Host smart-deec057d-b5e4-4a02-bafe-bb9207b2983e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607546331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flas
h_ctrl_intr_rd.607546331
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3038737991
Short name T87
Test name
Test status
Simulation time 11055011800 ps
CPU time 155.28 seconds
Started May 21 03:24:55 PM PDT 24
Finished May 21 03:27:32 PM PDT 24
Peak memory 292080 kb
Host smart-dc33ae51-b3a8-4043-badd-2a718f1ab81f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038737991 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3038737991
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1109799349
Short name T202
Test name
Test status
Simulation time 78075400 ps
CPU time 32.1 seconds
Started May 21 03:24:55 PM PDT 24
Finished May 21 03:25:28 PM PDT 24
Peak memory 273580 kb
Host smart-6fe7791e-d16c-49c0-8a7a-a97e940df970
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109799349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1109799349
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.1396865053
Short name T731
Test name
Test status
Simulation time 30642500 ps
CPU time 32.01 seconds
Started May 21 03:24:54 PM PDT 24
Finished May 21 03:25:27 PM PDT 24
Peak memory 269080 kb
Host smart-8b60db4b-ccf3-42d3-a2d4-7c7befad27c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396865053 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.1396865053
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3719983488
Short name T386
Test name
Test status
Simulation time 1520432100 ps
CPU time 71.44 seconds
Started May 21 03:25:00 PM PDT 24
Finished May 21 03:26:13 PM PDT 24
Peak memory 262656 kb
Host smart-5b447016-bec7-435a-a1c3-64e51416d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719983488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3719983488
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1362445695
Short name T590
Test name
Test status
Simulation time 41377900 ps
CPU time 119.46 seconds
Started May 21 03:24:54 PM PDT 24
Finished May 21 03:26:55 PM PDT 24
Peak memory 277116 kb
Host smart-47007f15-1cb7-465d-a094-794ca4aa3978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362445695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1362445695
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2195259087
Short name T1005
Test name
Test status
Simulation time 89635800 ps
CPU time 13.77 seconds
Started May 21 03:25:05 PM PDT 24
Finished May 21 03:25:20 PM PDT 24
Peak memory 265232 kb
Host smart-7f79aefe-4bee-4a2e-b5c3-c893263573d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195259087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2195259087
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2982125175
Short name T1031
Test name
Test status
Simulation time 61063100 ps
CPU time 13.29 seconds
Started May 21 03:25:06 PM PDT 24
Finished May 21 03:25:21 PM PDT 24
Peak memory 275112 kb
Host smart-01fc675c-45bb-4641-8135-13e57af2fb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982125175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2982125175
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.2386004881
Short name T598
Test name
Test status
Simulation time 27830800 ps
CPU time 21.58 seconds
Started May 21 03:25:07 PM PDT 24
Finished May 21 03:25:30 PM PDT 24
Peak memory 265464 kb
Host smart-3217c4ad-e29a-475f-b4e5-55e1df20f381
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386004881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.2386004881
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.827596935
Short name T430
Test name
Test status
Simulation time 1532994900 ps
CPU time 118.7 seconds
Started May 21 03:25:01 PM PDT 24
Finished May 21 03:27:01 PM PDT 24
Peak memory 262608 kb
Host smart-7190baee-9852-4c1b-9672-4a21403ccda2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827596935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.827596935
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.394500528
Short name T442
Test name
Test status
Simulation time 1806130700 ps
CPU time 126.22 seconds
Started May 21 03:25:00 PM PDT 24
Finished May 21 03:27:08 PM PDT 24
Peak memory 293384 kb
Host smart-eeae3a28-614b-4b8d-8dbd-85d3ad731abc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394500528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flas
h_ctrl_intr_rd.394500528
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.80951332
Short name T392
Test name
Test status
Simulation time 46696652200 ps
CPU time 271.64 seconds
Started May 21 03:25:01 PM PDT 24
Finished May 21 03:29:34 PM PDT 24
Peak memory 284496 kb
Host smart-b7c9daea-1188-4a0b-92d3-33aa0912e84e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80951332 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.80951332
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.399390749
Short name T654
Test name
Test status
Simulation time 131664200 ps
CPU time 129.55 seconds
Started May 21 03:25:01 PM PDT 24
Finished May 21 03:27:12 PM PDT 24
Peak memory 262384 kb
Host smart-b20ea064-ccac-4954-9c36-8022a9007283
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399390749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.399390749
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.1661475224
Short name T844
Test name
Test status
Simulation time 158491100 ps
CPU time 32.36 seconds
Started May 21 03:25:01 PM PDT 24
Finished May 21 03:25:35 PM PDT 24
Peak memory 273616 kb
Host smart-b358903c-513c-4d61-bfdf-0efdeb725542
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661475224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.1661475224
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.4234366182
Short name T691
Test name
Test status
Simulation time 75682200 ps
CPU time 29.29 seconds
Started May 21 03:25:01 PM PDT 24
Finished May 21 03:25:31 PM PDT 24
Peak memory 269288 kb
Host smart-cde39661-20b6-4561-b397-128e9ae98576
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234366182 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.4234366182
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.2393367861
Short name T606
Test name
Test status
Simulation time 2787550300 ps
CPU time 74.02 seconds
Started May 21 03:25:04 PM PDT 24
Finished May 21 03:26:19 PM PDT 24
Peak memory 262928 kb
Host smart-6d85b25b-b0ad-4da3-9b4b-12e5be1c597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393367861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2393367861
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.257622333
Short name T423
Test name
Test status
Simulation time 69408700 ps
CPU time 97.79 seconds
Started May 21 03:24:59 PM PDT 24
Finished May 21 03:26:37 PM PDT 24
Peak memory 275556 kb
Host smart-b70311c5-f7e3-4398-accb-5a3426d89a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257622333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.257622333
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.918020735
Short name T954
Test name
Test status
Simulation time 62074000 ps
CPU time 13.96 seconds
Started May 21 03:25:16 PM PDT 24
Finished May 21 03:25:32 PM PDT 24
Peak memory 265200 kb
Host smart-47c67954-4360-43f6-872c-8026ee5099ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918020735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.918020735
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.3010741433
Short name T518
Test name
Test status
Simulation time 14662300 ps
CPU time 13.28 seconds
Started May 21 03:25:14 PM PDT 24
Finished May 21 03:25:30 PM PDT 24
Peak memory 275756 kb
Host smart-f9788e64-81bb-4cd1-84c3-6d99fa4a00bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010741433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3010741433
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3200368203
Short name T358
Test name
Test status
Simulation time 100777600 ps
CPU time 22.83 seconds
Started May 21 03:25:13 PM PDT 24
Finished May 21 03:25:37 PM PDT 24
Peak memory 265216 kb
Host smart-9daa7583-52ed-4e02-9a3b-40d00ad8151c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200368203 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3200368203
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.655146261
Short name T1106
Test name
Test status
Simulation time 7630293500 ps
CPU time 131.25 seconds
Started May 21 03:25:07 PM PDT 24
Finished May 21 03:27:19 PM PDT 24
Peak memory 261964 kb
Host smart-5a6318ab-270f-4ac5-9c5e-bf92fd52e3ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655146261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h
w_sec_otp.655146261
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.198624861
Short name T462
Test name
Test status
Simulation time 2203469800 ps
CPU time 133.7 seconds
Started May 21 03:25:05 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 298060 kb
Host smart-44af5cb3-7e86-44ce-afa5-17b72586da6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198624861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flas
h_ctrl_intr_rd.198624861
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3552377538
Short name T695
Test name
Test status
Simulation time 23562272100 ps
CPU time 476.05 seconds
Started May 21 03:25:07 PM PDT 24
Finished May 21 03:33:04 PM PDT 24
Peak memory 284212 kb
Host smart-2cbbf19d-6209-471f-b8c7-8160a223376d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552377538 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3552377538
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.475068394
Short name T794
Test name
Test status
Simulation time 96575700 ps
CPU time 131.03 seconds
Started May 21 03:25:05 PM PDT 24
Finished May 21 03:27:17 PM PDT 24
Peak memory 261080 kb
Host smart-9caf713a-f11f-4d3e-a014-f0e4bc160732
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475068394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.475068394
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3940560647
Short name T1029
Test name
Test status
Simulation time 49294000 ps
CPU time 31.69 seconds
Started May 21 03:25:15 PM PDT 24
Finished May 21 03:25:49 PM PDT 24
Peak memory 273576 kb
Host smart-77a5af84-811e-407a-aa32-2542ef87e205
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940560647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3940560647
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1252384760
Short name T517
Test name
Test status
Simulation time 66073700 ps
CPU time 31.19 seconds
Started May 21 03:25:16 PM PDT 24
Finished May 21 03:25:49 PM PDT 24
Peak memory 274860 kb
Host smart-70e38dc8-5b5c-406a-9ea4-8ad8cbb06f9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252384760 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1252384760
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.2713045247
Short name T693
Test name
Test status
Simulation time 6829875200 ps
CPU time 70.66 seconds
Started May 21 03:25:14 PM PDT 24
Finished May 21 03:26:28 PM PDT 24
Peak memory 262648 kb
Host smart-cfda822d-96b7-4115-9f1b-733a42bd2c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713045247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2713045247
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.3541485340
Short name T717
Test name
Test status
Simulation time 46405800 ps
CPU time 122.35 seconds
Started May 21 03:25:05 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 276040 kb
Host smart-155cc5e7-534f-4c10-909c-0feb1ff1aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541485340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3541485340
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.3452310186
Short name T749
Test name
Test status
Simulation time 117233000 ps
CPU time 13.85 seconds
Started May 21 03:25:17 PM PDT 24
Finished May 21 03:25:33 PM PDT 24
Peak memory 265148 kb
Host smart-0fd41f5f-6ba8-4455-b2cb-3afe179a0d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452310186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
3452310186
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3379604737
Short name T723
Test name
Test status
Simulation time 28372600 ps
CPU time 16.09 seconds
Started May 21 03:25:18 PM PDT 24
Finished May 21 03:25:35 PM PDT 24
Peak memory 275064 kb
Host smart-525c8b92-b27d-438b-94c9-e66c06fbf80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379604737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3379604737
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2490845595
Short name T161
Test name
Test status
Simulation time 32138700 ps
CPU time 20.92 seconds
Started May 21 03:25:14 PM PDT 24
Finished May 21 03:25:38 PM PDT 24
Peak memory 265336 kb
Host smart-77c6dd8c-37da-4648-8baa-fcbc84970cc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490845595 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2490845595
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2713036253
Short name T672
Test name
Test status
Simulation time 1658119800 ps
CPU time 136.82 seconds
Started May 21 03:25:14 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 262548 kb
Host smart-6d434574-4834-4f52-a496-18e62e652ec9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713036253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2713036253
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.474019153
Short name T61
Test name
Test status
Simulation time 1486273800 ps
CPU time 147.26 seconds
Started May 21 03:25:17 PM PDT 24
Finished May 21 03:27:46 PM PDT 24
Peak memory 293136 kb
Host smart-3609bf7a-0fa4-4e01-a1c9-7c0d7765d94b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474019153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.474019153
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2076157477
Short name T719
Test name
Test status
Simulation time 5858803200 ps
CPU time 139.62 seconds
Started May 21 03:25:16 PM PDT 24
Finished May 21 03:27:38 PM PDT 24
Peak memory 292112 kb
Host smart-d3f48fda-8e95-4233-9dec-011b53030173
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076157477 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.2076157477
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.1488460562
Short name T533
Test name
Test status
Simulation time 139873800 ps
CPU time 111.52 seconds
Started May 21 03:25:15 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 261200 kb
Host smart-272c100b-9d42-4053-a893-746f463ecd2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488460562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.1488460562
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.2401418706
Short name T618
Test name
Test status
Simulation time 32885300 ps
CPU time 31.45 seconds
Started May 21 03:25:14 PM PDT 24
Finished May 21 03:25:48 PM PDT 24
Peak memory 273576 kb
Host smart-ca90001e-c692-43cb-9a51-153c0ee4e35b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401418706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.2401418706
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.715977988
Short name T478
Test name
Test status
Simulation time 51903300 ps
CPU time 31.46 seconds
Started May 21 03:25:15 PM PDT 24
Finished May 21 03:25:49 PM PDT 24
Peak memory 274740 kb
Host smart-8ed8be36-ec5c-4b72-a353-0dcd03071e8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715977988 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.715977988
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3486397820
Short name T804
Test name
Test status
Simulation time 19088502000 ps
CPU time 68.78 seconds
Started May 21 03:25:19 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 263492 kb
Host smart-dc5e41ed-58c4-4cc0-8eaf-faec0ff3502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486397820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3486397820
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.466293611
Short name T818
Test name
Test status
Simulation time 2542622600 ps
CPU time 172.69 seconds
Started May 21 03:25:15 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 279020 kb
Host smart-e67f4982-5498-4ef5-b353-6b2be761ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466293611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.466293611
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.3395166765
Short name T764
Test name
Test status
Simulation time 79933200 ps
CPU time 14.19 seconds
Started May 21 03:25:22 PM PDT 24
Finished May 21 03:25:37 PM PDT 24
Peak memory 265172 kb
Host smart-1e2f2c5a-f987-4748-ab50-48e0a1df2fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395166765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
3395166765
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2184175505
Short name T939
Test name
Test status
Simulation time 13855400 ps
CPU time 15.99 seconds
Started May 21 03:25:23 PM PDT 24
Finished May 21 03:25:40 PM PDT 24
Peak memory 275160 kb
Host smart-82312cd7-7da4-47a3-8325-064fdf144168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184175505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2184175505
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.3544651745
Short name T748
Test name
Test status
Simulation time 10931600 ps
CPU time 21.94 seconds
Started May 21 03:25:24 PM PDT 24
Finished May 21 03:25:47 PM PDT 24
Peak memory 273636 kb
Host smart-c35c5457-d1aa-42b0-b756-663b8bfc9aad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544651745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.3544651745
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.667885413
Short name T308
Test name
Test status
Simulation time 4487535300 ps
CPU time 91.14 seconds
Started May 21 03:25:17 PM PDT 24
Finished May 21 03:26:50 PM PDT 24
Peak memory 262704 kb
Host smart-0320e835-d470-4ed0-bcd0-9022987e5b91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667885413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.667885413
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.977842581
Short name T1085
Test name
Test status
Simulation time 1221894800 ps
CPU time 180.69 seconds
Started May 21 03:25:18 PM PDT 24
Finished May 21 03:28:21 PM PDT 24
Peak memory 289872 kb
Host smart-5208e12d-6632-401c-994c-15aec7ad26e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977842581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.977842581
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1225102577
Short name T775
Test name
Test status
Simulation time 30758217400 ps
CPU time 279.71 seconds
Started May 21 03:25:23 PM PDT 24
Finished May 21 03:30:04 PM PDT 24
Peak memory 291240 kb
Host smart-112a4d37-45e8-4f08-9df7-c559b60b8b39
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225102577 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1225102577
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.3637962152
Short name T130
Test name
Test status
Simulation time 122364600 ps
CPU time 111.75 seconds
Started May 21 03:25:17 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 259944 kb
Host smart-e4aa2af5-cc8e-40a7-8f6a-b250e9e98840
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637962152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.3637962152
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.2021851385
Short name T1069
Test name
Test status
Simulation time 54241600 ps
CPU time 29.37 seconds
Started May 21 03:25:24 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 267472 kb
Host smart-f491cf35-206b-4f0b-bc77-761a7c7e5390
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021851385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.2021851385
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.149732006
Short name T1045
Test name
Test status
Simulation time 29754600 ps
CPU time 29.37 seconds
Started May 21 03:25:25 PM PDT 24
Finished May 21 03:25:55 PM PDT 24
Peak memory 275632 kb
Host smart-d4631151-7ccb-41a1-b7e2-2f25179fe294
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149732006 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.149732006
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.4155316674
Short name T853
Test name
Test status
Simulation time 1690958200 ps
CPU time 64.51 seconds
Started May 21 03:25:23 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 263292 kb
Host smart-932988df-2aae-4f55-9150-b41f638dd206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155316674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.4155316674
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.2986078336
Short name T703
Test name
Test status
Simulation time 22765200 ps
CPU time 97.67 seconds
Started May 21 03:25:17 PM PDT 24
Finished May 21 03:26:57 PM PDT 24
Peak memory 276428 kb
Host smart-2c70e2bc-0cb9-4efa-8f36-1284728accce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986078336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2986078336
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3062617776
Short name T677
Test name
Test status
Simulation time 55505400 ps
CPU time 13.63 seconds
Started May 21 03:25:30 PM PDT 24
Finished May 21 03:25:45 PM PDT 24
Peak memory 265200 kb
Host smart-4251d1fa-9cef-4f7c-bc6c-bec0653013db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062617776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3062617776
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.2312610399
Short name T981
Test name
Test status
Simulation time 15760600 ps
CPU time 15.52 seconds
Started May 21 03:25:28 PM PDT 24
Finished May 21 03:25:44 PM PDT 24
Peak memory 275116 kb
Host smart-6c2973cc-d567-4b43-910a-69d7d3900637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312610399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2312610399
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3131635899
Short name T989
Test name
Test status
Simulation time 4017120800 ps
CPU time 81.71 seconds
Started May 21 03:25:23 PM PDT 24
Finished May 21 03:26:45 PM PDT 24
Peak memory 262504 kb
Host smart-c0f92c90-6146-43b8-8a91-db8469deb77e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131635899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3131635899
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.2709253574
Short name T235
Test name
Test status
Simulation time 3721782800 ps
CPU time 205.46 seconds
Started May 21 03:25:24 PM PDT 24
Finished May 21 03:28:51 PM PDT 24
Peak memory 289952 kb
Host smart-6a3bd5da-f73c-4530-99f6-f8fd06e377d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709253574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.2709253574
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1590357063
Short name T611
Test name
Test status
Simulation time 114467642200 ps
CPU time 220.41 seconds
Started May 21 03:25:29 PM PDT 24
Finished May 21 03:29:10 PM PDT 24
Peak memory 292128 kb
Host smart-5688f9d4-4a19-498e-be74-3ea4c58ed539
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590357063 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1590357063
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2576755694
Short name T972
Test name
Test status
Simulation time 38854800 ps
CPU time 131.03 seconds
Started May 21 03:25:26 PM PDT 24
Finished May 21 03:27:38 PM PDT 24
Peak memory 259976 kb
Host smart-024398be-f231-4818-81f5-bf859e3859e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576755694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2576755694
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.1989518104
Short name T864
Test name
Test status
Simulation time 37584600 ps
CPU time 31.65 seconds
Started May 21 03:25:29 PM PDT 24
Finished May 21 03:26:01 PM PDT 24
Peak memory 274564 kb
Host smart-f2951461-b317-4c09-9955-9c29d0db1402
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989518104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.1989518104
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3550335448
Short name T333
Test name
Test status
Simulation time 41540200 ps
CPU time 28.37 seconds
Started May 21 03:25:28 PM PDT 24
Finished May 21 03:25:57 PM PDT 24
Peak memory 274700 kb
Host smart-30be4193-cecf-44e7-86f4-2e9d845714a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550335448 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3550335448
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.2615237883
Short name T482
Test name
Test status
Simulation time 2894591700 ps
CPU time 68.36 seconds
Started May 21 03:25:29 PM PDT 24
Finished May 21 03:26:38 PM PDT 24
Peak memory 263176 kb
Host smart-f1058c14-0889-4f87-a2ad-60be0824da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615237883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2615237883
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3415499800
Short name T246
Test name
Test status
Simulation time 18229900 ps
CPU time 75.66 seconds
Started May 21 03:25:23 PM PDT 24
Finished May 21 03:26:39 PM PDT 24
Peak memory 274396 kb
Host smart-15d53420-f0a5-4c70-89e3-1e9d3f13d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415499800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3415499800
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2406439235
Short name T1020
Test name
Test status
Simulation time 39701500 ps
CPU time 13.79 seconds
Started May 21 03:25:38 PM PDT 24
Finished May 21 03:25:52 PM PDT 24
Peak memory 265236 kb
Host smart-2b4c9672-584b-4863-9f77-25417c4cf151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406439235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2406439235
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.3057532698
Short name T395
Test name
Test status
Simulation time 37862700 ps
CPU time 13.24 seconds
Started May 21 03:25:40 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 275064 kb
Host smart-a7e1593c-e2bb-4e87-82b1-22d6956e8efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057532698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3057532698
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.4004695028
Short name T637
Test name
Test status
Simulation time 23246800 ps
CPU time 22.54 seconds
Started May 21 03:25:35 PM PDT 24
Finished May 21 03:25:58 PM PDT 24
Peak memory 265400 kb
Host smart-4b0f7ac2-54e5-4f4c-b071-7fd7c2b12376
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004695028 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.4004695028
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3600142668
Short name T643
Test name
Test status
Simulation time 1193997500 ps
CPU time 105.96 seconds
Started May 21 03:25:31 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 259436 kb
Host smart-445bc244-25fb-4b81-8a74-2884597a5069
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600142668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.3600142668
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.1560665702
Short name T715
Test name
Test status
Simulation time 2864729400 ps
CPU time 131.39 seconds
Started May 21 03:25:36 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 293072 kb
Host smart-e0c32265-8949-485f-b14d-c40e9ad84ffc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560665702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.1560665702
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2166265928
Short name T497
Test name
Test status
Simulation time 24916459400 ps
CPU time 147.74 seconds
Started May 21 03:25:35 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 292132 kb
Host smart-3a27a5a7-98d8-4b01-9bf8-59067540a8f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166265928 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2166265928
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.398985467
Short name T868
Test name
Test status
Simulation time 76394000 ps
CPU time 131.39 seconds
Started May 21 03:25:28 PM PDT 24
Finished May 21 03:27:41 PM PDT 24
Peak memory 259972 kb
Host smart-2db85aac-1af3-42c4-baa6-5b97b3daccc8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398985467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ot
p_reset.398985467
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.90843994
Short name T700
Test name
Test status
Simulation time 48468700 ps
CPU time 32.4 seconds
Started May 21 03:25:36 PM PDT 24
Finished May 21 03:26:09 PM PDT 24
Peak memory 273552 kb
Host smart-456f92d1-8d36-44a7-9c39-b90f44de0d10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90843994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_rw_evict.90843994
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2236484709
Short name T946
Test name
Test status
Simulation time 45842700 ps
CPU time 31.67 seconds
Started May 21 03:25:35 PM PDT 24
Finished May 21 03:26:08 PM PDT 24
Peak memory 274804 kb
Host smart-7ea1b04c-9a65-441f-b6de-03f21cbc2a67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236484709 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2236484709
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1799422251
Short name T356
Test name
Test status
Simulation time 5145175600 ps
CPU time 65.8 seconds
Started May 21 03:25:35 PM PDT 24
Finished May 21 03:26:42 PM PDT 24
Peak memory 261564 kb
Host smart-902482e6-c254-4f65-857c-f1a7a38a5052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799422251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1799422251
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.2291559121
Short name T532
Test name
Test status
Simulation time 69498100 ps
CPU time 152.03 seconds
Started May 21 03:25:29 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 276460 kb
Host smart-be442677-9076-4f9d-a239-5a6e1eb73483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291559121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2291559121
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3156927435
Short name T1059
Test name
Test status
Simulation time 98018500 ps
CPU time 13.61 seconds
Started May 21 03:25:44 PM PDT 24
Finished May 21 03:25:58 PM PDT 24
Peak memory 265208 kb
Host smart-03b2dc1f-be71-4944-aef6-179e757c9973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156927435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3156927435
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2208807316
Short name T587
Test name
Test status
Simulation time 90906200 ps
CPU time 15.89 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:09 PM PDT 24
Peak memory 275184 kb
Host smart-f7c0cacf-8eb5-4c5a-bf5e-8d3b3e973c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208807316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2208807316
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.4220737354
Short name T105
Test name
Test status
Simulation time 10695200 ps
CPU time 20.27 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:13 PM PDT 24
Peak memory 265412 kb
Host smart-6e1a8d97-0235-4b4f-b0b4-8b552267cfe2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220737354 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.4220737354
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1528589976
Short name T305
Test name
Test status
Simulation time 4662238300 ps
CPU time 104.8 seconds
Started May 21 03:25:40 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 262596 kb
Host smart-f26bb032-ee54-400c-93c2-8b28b9b28aa4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528589976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.1528589976
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.725718410
Short name T321
Test name
Test status
Simulation time 11884661700 ps
CPU time 151.83 seconds
Started May 21 03:25:39 PM PDT 24
Finished May 21 03:28:11 PM PDT 24
Peak memory 289976 kb
Host smart-8be6022e-2498-4a00-976d-6969c614b5b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725718410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas
h_ctrl_intr_rd.725718410
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1476945458
Short name T623
Test name
Test status
Simulation time 7784850200 ps
CPU time 146.5 seconds
Started May 21 03:25:40 PM PDT 24
Finished May 21 03:28:07 PM PDT 24
Peak memory 292136 kb
Host smart-48112854-0985-4cfd-ab7b-67db7ef69cfb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476945458 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1476945458
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.2545484402
Short name T458
Test name
Test status
Simulation time 46430800 ps
CPU time 132.18 seconds
Started May 21 03:25:40 PM PDT 24
Finished May 21 03:27:53 PM PDT 24
Peak memory 261020 kb
Host smart-642a94dc-acca-444f-9f06-216976733440
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545484402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.2545484402
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2392302303
Short name T777
Test name
Test status
Simulation time 78304200 ps
CPU time 31.43 seconds
Started May 21 03:25:50 PM PDT 24
Finished May 21 03:26:22 PM PDT 24
Peak memory 274792 kb
Host smart-80d667b9-87ba-4c05-9c45-a88196b19979
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392302303 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2392302303
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1522672165
Short name T788
Test name
Test status
Simulation time 969904600 ps
CPU time 58.31 seconds
Started May 21 03:25:47 PM PDT 24
Finished May 21 03:26:47 PM PDT 24
Peak memory 263208 kb
Host smart-ea16e118-07a7-45f8-a993-554cb72a8362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522672165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1522672165
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3016469451
Short name T867
Test name
Test status
Simulation time 1387824500 ps
CPU time 218.69 seconds
Started May 21 03:25:40 PM PDT 24
Finished May 21 03:29:20 PM PDT 24
Peak memory 281564 kb
Host smart-cd41752c-7ee4-4734-bce7-12c62118209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016469451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3016469451
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.680935163
Short name T486
Test name
Test status
Simulation time 61569900 ps
CPU time 13.69 seconds
Started May 21 03:25:50 PM PDT 24
Finished May 21 03:26:06 PM PDT 24
Peak memory 265124 kb
Host smart-0af59dd4-f578-43a1-9400-c0b78ff328b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680935163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.680935163
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.1644280357
Short name T800
Test name
Test status
Simulation time 54969200 ps
CPU time 16.13 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:09 PM PDT 24
Peak memory 275152 kb
Host smart-6be8adcb-1412-4ffd-b31f-e6e43e698787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644280357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1644280357
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.1369766582
Short name T73
Test name
Test status
Simulation time 10039400 ps
CPU time 22.21 seconds
Started May 21 03:25:52 PM PDT 24
Finished May 21 03:26:17 PM PDT 24
Peak memory 265356 kb
Host smart-bfc79eb7-31ac-498f-a08f-08baf63ca9a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369766582 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.1369766582
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2631367531
Short name T948
Test name
Test status
Simulation time 3316431300 ps
CPU time 125.62 seconds
Started May 21 03:25:46 PM PDT 24
Finished May 21 03:27:53 PM PDT 24
Peak memory 262736 kb
Host smart-ef04b827-a6d0-416a-8220-1e87dc1f0efb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631367531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2631367531
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1445004483
Short name T806
Test name
Test status
Simulation time 1711554000 ps
CPU time 225.41 seconds
Started May 21 03:25:47 PM PDT 24
Finished May 21 03:29:33 PM PDT 24
Peak memory 289816 kb
Host smart-8a97cf25-d13d-4c88-9b2e-595aa5d4f126
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445004483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1445004483
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3849395122
Short name T1038
Test name
Test status
Simulation time 23886404400 ps
CPU time 166.99 seconds
Started May 21 03:25:50 PM PDT 24
Finished May 21 03:28:38 PM PDT 24
Peak memory 292768 kb
Host smart-ed5687ca-b3d8-4770-9c3b-38b383a774e0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849395122 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3849395122
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3559310830
Short name T713
Test name
Test status
Simulation time 293360100 ps
CPU time 132.18 seconds
Started May 21 03:25:45 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 261136 kb
Host smart-613adeba-77d1-4e0e-848f-0b60488c3fec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559310830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3559310830
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3923372267
Short name T25
Test name
Test status
Simulation time 46243200 ps
CPU time 32.29 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:25 PM PDT 24
Peak memory 273544 kb
Host smart-29211fc6-1dad-4e2b-ae9b-c36104d95293
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923372267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3923372267
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.623781388
Short name T469
Test name
Test status
Simulation time 1285389100 ps
CPU time 61.5 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:54 PM PDT 24
Peak memory 262444 kb
Host smart-9a48c4a7-a500-4090-99be-122386eddc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623781388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.623781388
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.642507761
Short name T441
Test name
Test status
Simulation time 22904200 ps
CPU time 96.48 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:27:30 PM PDT 24
Peak memory 275456 kb
Host smart-9476708f-67c4-4d1f-8520-34229ea03773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642507761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.642507761
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3642697163
Short name T464
Test name
Test status
Simulation time 136566300 ps
CPU time 14.07 seconds
Started May 21 03:17:12 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 265208 kb
Host smart-490a6a4a-afc3-4e4e-9b48-8c390ad73088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642697163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
642697163
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3955647010
Short name T210
Test name
Test status
Simulation time 75916700 ps
CPU time 14.01 seconds
Started May 21 03:17:31 PM PDT 24
Finished May 21 03:17:45 PM PDT 24
Peak memory 265136 kb
Host smart-3eda5534-cc61-4875-98b4-cf82fb7f9fc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955647010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3955647010
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1867273441
Short name T766
Test name
Test status
Simulation time 39237500 ps
CPU time 13.47 seconds
Started May 21 03:17:15 PM PDT 24
Finished May 21 03:17:29 PM PDT 24
Peak memory 275140 kb
Host smart-84e7dbc1-2d0d-475f-898c-68e9f9ec7b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867273441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1867273441
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2678414340
Short name T797
Test name
Test status
Simulation time 10554800 ps
CPU time 22.18 seconds
Started May 21 03:17:04 PM PDT 24
Finished May 21 03:17:27 PM PDT 24
Peak memory 273656 kb
Host smart-329e8fa7-f1b8-455c-a609-218e7ce3c6ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678414340 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2678414340
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1217665297
Short name T619
Test name
Test status
Simulation time 2962409800 ps
CPU time 306.88 seconds
Started May 21 03:16:57 PM PDT 24
Finished May 21 03:22:05 PM PDT 24
Peak memory 263092 kb
Host smart-58cab1b5-b9b4-409d-b16e-6fd190298c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217665297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1217665297
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2003269886
Short name T579
Test name
Test status
Simulation time 12712804100 ps
CPU time 2389.83 seconds
Started May 21 03:16:43 PM PDT 24
Finished May 21 03:56:34 PM PDT 24
Peak memory 262700 kb
Host smart-2f3d55a7-36be-4f24-a77b-1015718f35c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003269886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.2003269886
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.4000180062
Short name T183
Test name
Test status
Simulation time 783478700 ps
CPU time 2984.51 seconds
Started May 21 03:17:10 PM PDT 24
Finished May 21 04:06:57 PM PDT 24
Peak memory 265176 kb
Host smart-9e0237be-fff5-4ecb-8d9c-27ce7c3ae487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000180062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.4000180062
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.1564252383
Short name T808
Test name
Test status
Simulation time 1705119400 ps
CPU time 870.22 seconds
Started May 21 03:16:46 PM PDT 24
Finished May 21 03:31:19 PM PDT 24
Peak memory 273536 kb
Host smart-5e142186-fb7e-48b4-82f3-78b37b76f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564252383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1564252383
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.3793354998
Short name T327
Test name
Test status
Simulation time 1395262700 ps
CPU time 41.84 seconds
Started May 21 03:17:25 PM PDT 24
Finished May 21 03:18:07 PM PDT 24
Peak memory 262276 kb
Host smart-470a8b3a-5efa-40c2-9c9f-49faf3ed7873
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793354998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.3793354998
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.3421496103
Short name T76
Test name
Test status
Simulation time 157490137800 ps
CPU time 4535.45 seconds
Started May 21 03:16:51 PM PDT 24
Finished May 21 04:32:28 PM PDT 24
Peak memory 265240 kb
Host smart-7dfc5514-3502-4b03-a9da-41571e38549b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421496103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.3421496103
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2381278282
Short name T934
Test name
Test status
Simulation time 676930081100 ps
CPU time 2535.62 seconds
Started May 21 03:16:39 PM PDT 24
Finished May 21 03:58:56 PM PDT 24
Peak memory 265272 kb
Host smart-8723dc4a-c70d-46da-a2f5-ccb54254a706
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381278282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.2381278282
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.4019289366
Short name T280
Test name
Test status
Simulation time 36954700 ps
CPU time 56.11 seconds
Started May 21 03:16:30 PM PDT 24
Finished May 21 03:17:27 PM PDT 24
Peak memory 262552 kb
Host smart-c22f47e9-9941-430f-abf3-c414f1c50a89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019289366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.4019289366
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2689147358
Short name T839
Test name
Test status
Simulation time 10018354500 ps
CPU time 67.98 seconds
Started May 21 03:17:50 PM PDT 24
Finished May 21 03:18:59 PM PDT 24
Peak memory 286348 kb
Host smart-794f1bda-2bb2-448e-a562-4466f5ae7173
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689147358 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2689147358
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1154836323
Short name T124
Test name
Test status
Simulation time 25172100 ps
CPU time 13.68 seconds
Started May 21 03:17:13 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 265152 kb
Host smart-bd26ffdc-00e0-4c3d-8a95-816a7e319e5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154836323 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1154836323
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3701499122
Short name T1067
Test name
Test status
Simulation time 120168391000 ps
CPU time 934.17 seconds
Started May 21 03:16:46 PM PDT 24
Finished May 21 03:32:23 PM PDT 24
Peak memory 263368 kb
Host smart-1dc24995-5362-4855-b109-dea38a642b81
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701499122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3701499122
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.4253971953
Short name T992
Test name
Test status
Simulation time 11391773600 ps
CPU time 153.28 seconds
Started May 21 03:16:39 PM PDT 24
Finished May 21 03:19:13 PM PDT 24
Peak memory 262492 kb
Host smart-d4185b81-f2c0-44e8-b6c4-b0c4a463d59c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253971953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.4253971953
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3596064282
Short name T252
Test name
Test status
Simulation time 19969093000 ps
CPU time 722.17 seconds
Started May 21 03:17:03 PM PDT 24
Finished May 21 03:29:06 PM PDT 24
Peak memory 327908 kb
Host smart-8d2009b6-0bef-460e-b86e-1627b525ea42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596064282 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3596064282
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1045287056
Short name T110
Test name
Test status
Simulation time 740107100 ps
CPU time 205.38 seconds
Started May 21 03:16:57 PM PDT 24
Finished May 21 03:20:24 PM PDT 24
Peak memory 293508 kb
Host smart-d21158c1-3e52-47dd-ad21-77edd585d913
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045287056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1045287056
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3439692889
Short name T647
Test name
Test status
Simulation time 12005286900 ps
CPU time 260.03 seconds
Started May 21 03:17:23 PM PDT 24
Finished May 21 03:21:44 PM PDT 24
Peak memory 291312 kb
Host smart-d845f8f0-3c58-4bbb-b8b9-06ec727d9e51
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439692889 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3439692889
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.3001540493
Short name T410
Test name
Test status
Simulation time 20569207400 ps
CPU time 92.61 seconds
Started May 21 03:16:57 PM PDT 24
Finished May 21 03:18:31 PM PDT 24
Peak memory 259956 kb
Host smart-b7676ec9-4104-44b8-b113-e043800a9669
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001540493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.3001540493
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1825758966
Short name T452
Test name
Test status
Simulation time 19273055400 ps
CPU time 170.13 seconds
Started May 21 03:17:07 PM PDT 24
Finished May 21 03:19:58 PM PDT 24
Peak memory 260288 kb
Host smart-1e52e887-ce96-425f-99c5-b8b80d4c57fb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182
5758966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1825758966
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1094607110
Short name T1019
Test name
Test status
Simulation time 3974076900 ps
CPU time 65.55 seconds
Started May 21 03:16:46 PM PDT 24
Finished May 21 03:17:54 PM PDT 24
Peak memory 260704 kb
Host smart-1c36b721-ed70-4b74-85b0-560bc61515ae
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094607110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1094607110
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3509256055
Short name T977
Test name
Test status
Simulation time 45890600 ps
CPU time 13.48 seconds
Started May 21 03:17:13 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 265180 kb
Host smart-ed8dcdfb-495d-4bc2-b83a-e2b3cdcb3078
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509256055 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3509256055
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.497763841
Short name T125
Test name
Test status
Simulation time 2673338900 ps
CPU time 72.34 seconds
Started May 21 03:16:51 PM PDT 24
Finished May 21 03:18:05 PM PDT 24
Peak memory 259892 kb
Host smart-91098344-a675-4aa3-9c57-2cff3818902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497763841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.497763841
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.153079529
Short name T1003
Test name
Test status
Simulation time 8401142100 ps
CPU time 164.28 seconds
Started May 21 03:16:57 PM PDT 24
Finished May 21 03:19:43 PM PDT 24
Peak memory 261276 kb
Host smart-7dc20dc7-c038-4240-b3cb-98b66c1064bf
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153079529 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.153079529
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.3708067181
Short name T668
Test name
Test status
Simulation time 254595600 ps
CPU time 133.46 seconds
Started May 21 03:16:38 PM PDT 24
Finished May 21 03:18:52 PM PDT 24
Peak memory 260888 kb
Host smart-9928a4eb-da44-4abd-b91f-85fd4dcf848d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708067181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.3708067181
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.4231759065
Short name T854
Test name
Test status
Simulation time 6954434100 ps
CPU time 175.37 seconds
Started May 21 03:17:03 PM PDT 24
Finished May 21 03:20:00 PM PDT 24
Peak memory 281764 kb
Host smart-c5c8b186-f64d-493b-b9ca-e34f27d53f08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231759065 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.4231759065
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3518572823
Short name T605
Test name
Test status
Simulation time 1355344200 ps
CPU time 313.93 seconds
Started May 21 03:16:41 PM PDT 24
Finished May 21 03:21:58 PM PDT 24
Peak memory 265232 kb
Host smart-43a5879c-8e52-4337-b3ba-23d3eb290c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518572823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3518572823
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1997621570
Short name T1007
Test name
Test status
Simulation time 42119900 ps
CPU time 13.74 seconds
Started May 21 03:17:13 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 265396 kb
Host smart-2b4fc4c9-85b3-4110-b90f-b9e73649ee5d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997621570 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1997621570
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.2869785794
Short name T1050
Test name
Test status
Simulation time 8868297500 ps
CPU time 168.72 seconds
Started May 21 03:17:04 PM PDT 24
Finished May 21 03:19:54 PM PDT 24
Peak memory 259892 kb
Host smart-a542a3b3-f54e-44cf-be26-fa22a55a75d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869785794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.2869785794
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3246489673
Short name T101
Test name
Test status
Simulation time 2584511100 ps
CPU time 762.4 seconds
Started May 21 03:16:32 PM PDT 24
Finished May 21 03:29:15 PM PDT 24
Peak memory 285376 kb
Host smart-bc06ad4f-c3b6-4d9a-850d-a52ac8137719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246489673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3246489673
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2634970287
Short name T951
Test name
Test status
Simulation time 720446500 ps
CPU time 145.2 seconds
Started May 21 03:16:43 PM PDT 24
Finished May 21 03:19:10 PM PDT 24
Peak memory 265256 kb
Host smart-5d46f51a-093c-49d1-9de6-546608df68e9
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634970287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2634970287
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2589749699
Short name T1072
Test name
Test status
Simulation time 107484700 ps
CPU time 39.61 seconds
Started May 21 03:17:29 PM PDT 24
Finished May 21 03:18:09 PM PDT 24
Peak memory 274592 kb
Host smart-95a02858-07bd-461a-a85d-413bfb51f8f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589749699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2589749699
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.204313954
Short name T544
Test name
Test status
Simulation time 19309600 ps
CPU time 23.3 seconds
Started May 21 03:17:03 PM PDT 24
Finished May 21 03:17:28 PM PDT 24
Peak memory 265204 kb
Host smart-747f00c8-2f79-4c07-9f88-e64393a567ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204313954 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.204313954
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.53265360
Short name T621
Test name
Test status
Simulation time 32317600 ps
CPU time 21.29 seconds
Started May 21 03:16:50 PM PDT 24
Finished May 21 03:17:12 PM PDT 24
Peak memory 265304 kb
Host smart-8e7d9ef5-3631-4f23-9e71-cbca5996e22d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53265360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_serr.53265360
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.2362904424
Short name T483
Test name
Test status
Simulation time 488389000 ps
CPU time 114.64 seconds
Started May 21 03:16:50 PM PDT 24
Finished May 21 03:18:46 PM PDT 24
Peak memory 289240 kb
Host smart-923c5c5c-34cc-452b-826b-768a1290a889
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362904424 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.2362904424
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.151365424
Short name T222
Test name
Test status
Simulation time 2108368700 ps
CPU time 141.1 seconds
Started May 21 03:17:14 PM PDT 24
Finished May 21 03:19:36 PM PDT 24
Peak memory 281736 kb
Host smart-669cb543-c89d-4747-92e8-85f426396a3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
151365424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.151365424
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1508327701
Short name T735
Test name
Test status
Simulation time 4944155600 ps
CPU time 140.12 seconds
Started May 21 03:17:15 PM PDT 24
Finished May 21 03:19:36 PM PDT 24
Peak memory 281768 kb
Host smart-034595da-b1be-4c69-b484-dad108c54164
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508327701 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1508327701
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3873026148
Short name T208
Test name
Test status
Simulation time 2799324400 ps
CPU time 536.86 seconds
Started May 21 03:17:07 PM PDT 24
Finished May 21 03:26:05 PM PDT 24
Peak memory 313812 kb
Host smart-469e89c1-8fb1-4f6c-b55b-c873e1f3b30b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873026148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.3873026148
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.1804272974
Short name T449
Test name
Test status
Simulation time 80952800 ps
CPU time 32.66 seconds
Started May 21 03:17:11 PM PDT 24
Finished May 21 03:17:45 PM PDT 24
Peak memory 274620 kb
Host smart-056b53e6-2ac4-498b-afc8-2a72a88a2885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804272974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.1804272974
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.273704073
Short name T599
Test name
Test status
Simulation time 3598049500 ps
CPU time 589.84 seconds
Started May 21 03:16:59 PM PDT 24
Finished May 21 03:26:49 PM PDT 24
Peak memory 320188 kb
Host smart-f04d09a8-cb12-4820-bea8-9e8ffed5a0f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273704073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_se
rr.273704073
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3096067752
Short name T201
Test name
Test status
Simulation time 4948941000 ps
CPU time 4918.47 seconds
Started May 21 03:17:19 PM PDT 24
Finished May 21 04:39:19 PM PDT 24
Peak memory 288628 kb
Host smart-263048b0-456a-43a5-a471-8532ec5ddb3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096067752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3096067752
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1984891988
Short name T534
Test name
Test status
Simulation time 694053000 ps
CPU time 64.72 seconds
Started May 21 03:17:39 PM PDT 24
Finished May 21 03:18:44 PM PDT 24
Peak memory 263064 kb
Host smart-db111c24-7baa-4102-898d-673bcc861924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984891988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1984891988
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1109454600
Short name T1062
Test name
Test status
Simulation time 1651211700 ps
CPU time 88.65 seconds
Started May 21 03:16:52 PM PDT 24
Finished May 21 03:18:23 PM PDT 24
Peak memory 265324 kb
Host smart-c1e109ad-1625-40c0-a699-79ad177db80f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109454600 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1109454600
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.1576150969
Short name T37
Test name
Test status
Simulation time 1626997000 ps
CPU time 61.67 seconds
Started May 21 03:16:52 PM PDT 24
Finished May 21 03:17:56 PM PDT 24
Peak memory 273540 kb
Host smart-da05dda1-b58c-4b9a-9192-0a0d7f9d17a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576150969 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.1576150969
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.1633461322
Short name T109
Test name
Test status
Simulation time 69052100 ps
CPU time 51.64 seconds
Started May 21 03:16:45 PM PDT 24
Finished May 21 03:17:39 PM PDT 24
Peak memory 270544 kb
Host smart-4aa1cd13-da7c-48cc-b41c-24cd29b76fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633461322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1633461322
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.2290535896
Short name T537
Test name
Test status
Simulation time 54179300 ps
CPU time 25.61 seconds
Started May 21 03:16:30 PM PDT 24
Finished May 21 03:16:56 PM PDT 24
Peak memory 258920 kb
Host smart-aa34c4e8-dfed-4198-91a7-6efb311d5aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290535896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2290535896
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2795739864
Short name T1006
Test name
Test status
Simulation time 83233900 ps
CPU time 304.9 seconds
Started May 21 03:17:14 PM PDT 24
Finished May 21 03:22:20 PM PDT 24
Peak memory 281700 kb
Host smart-696815fb-24be-4296-80ec-e8aa29b61b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795739864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2795739864
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.765331333
Short name T915
Test name
Test status
Simulation time 323067700 ps
CPU time 24.09 seconds
Started May 21 03:16:48 PM PDT 24
Finished May 21 03:17:14 PM PDT 24
Peak memory 259084 kb
Host smart-23ae66f4-125d-4a96-9525-3c3c53896200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765331333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.765331333
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1984138893
Short name T492
Test name
Test status
Simulation time 4256633000 ps
CPU time 192.31 seconds
Started May 21 03:16:52 PM PDT 24
Finished May 21 03:20:07 PM PDT 24
Peak memory 265208 kb
Host smart-a1a8f08d-4650-488b-bfc2-8a5cca318b6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984138893 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.1984138893
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.3893604726
Short name T921
Test name
Test status
Simulation time 133925500 ps
CPU time 13.74 seconds
Started May 21 03:25:59 PM PDT 24
Finished May 21 03:26:13 PM PDT 24
Peak memory 265224 kb
Host smart-89cc94f5-d5da-4ccd-81d1-ae24a40724ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893604726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
3893604726
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.724619045
Short name T549
Test name
Test status
Simulation time 53899900 ps
CPU time 16.44 seconds
Started May 21 03:25:57 PM PDT 24
Finished May 21 03:26:14 PM PDT 24
Peak memory 275176 kb
Host smart-45cda2f4-173c-488c-b3fe-d9d2384c05b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724619045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.724619045
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.604986738
Short name T498
Test name
Test status
Simulation time 10983700 ps
CPU time 20.5 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:26:14 PM PDT 24
Peak memory 280252 kb
Host smart-e4fbc870-0495-486c-8258-9704780ccbeb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604986738 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.604986738
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4126470272
Short name T306
Test name
Test status
Simulation time 3091261300 ps
CPU time 100.44 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 262616 kb
Host smart-a27ef517-af44-4331-b6f1-8ea852a68259
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126470272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.4126470272
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.920426902
Short name T1042
Test name
Test status
Simulation time 105998400 ps
CPU time 130.98 seconds
Started May 21 03:25:51 PM PDT 24
Finished May 21 03:28:04 PM PDT 24
Peak memory 259812 kb
Host smart-2732baa8-38be-457b-ac18-eed64fe2bbed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920426902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.920426902
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1629616489
Short name T418
Test name
Test status
Simulation time 2342584300 ps
CPU time 60.55 seconds
Started May 21 03:25:56 PM PDT 24
Finished May 21 03:26:57 PM PDT 24
Peak memory 263248 kb
Host smart-605f7c55-4374-4e05-b046-9c5251a0e03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629616489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1629616489
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2645913638
Short name T496
Test name
Test status
Simulation time 31140800 ps
CPU time 76.02 seconds
Started May 21 03:25:53 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 275928 kb
Host smart-38b64353-f273-4aa4-b5f5-cf3a11eb09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645913638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2645913638
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1550883368
Short name T1004
Test name
Test status
Simulation time 21027300 ps
CPU time 13.63 seconds
Started May 21 03:26:00 PM PDT 24
Finished May 21 03:26:15 PM PDT 24
Peak memory 265180 kb
Host smart-3921d4c4-3fa6-43b6-a1b5-304ae6d65c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550883368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1550883368
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.103498433
Short name T432
Test name
Test status
Simulation time 41260600 ps
CPU time 13.67 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:26:15 PM PDT 24
Peak memory 275736 kb
Host smart-076a56a1-e116-490d-a9f1-9c56d91f10a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103498433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.103498433
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.2077423530
Short name T1073
Test name
Test status
Simulation time 25566100 ps
CPU time 22.21 seconds
Started May 21 03:25:57 PM PDT 24
Finished May 21 03:26:19 PM PDT 24
Peak memory 265364 kb
Host smart-df2738f3-f7aa-421e-9562-48613c12bf4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077423530 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.2077423530
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3023101542
Short name T409
Test name
Test status
Simulation time 9389281700 ps
CPU time 55.34 seconds
Started May 21 03:25:59 PM PDT 24
Finished May 21 03:26:55 PM PDT 24
Peak memory 262596 kb
Host smart-6dbf0dd9-4df4-44d4-9c7c-3611728050bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023101542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3023101542
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2373146228
Short name T658
Test name
Test status
Simulation time 4348937100 ps
CPU time 82.44 seconds
Started May 21 03:25:58 PM PDT 24
Finished May 21 03:27:21 PM PDT 24
Peak memory 262912 kb
Host smart-19fa5c36-0cf2-4f1b-b806-2c6ad7ab3a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373146228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2373146228
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.642452262
Short name T1021
Test name
Test status
Simulation time 47040800 ps
CPU time 122.87 seconds
Started May 21 03:26:00 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 276812 kb
Host smart-26e56405-ae42-4445-bf56-7582cf961c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642452262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.642452262
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.1645589190
Short name T490
Test name
Test status
Simulation time 36096300 ps
CPU time 13.69 seconds
Started May 21 03:26:02 PM PDT 24
Finished May 21 03:26:17 PM PDT 24
Peak memory 265200 kb
Host smart-2dd8e32f-45de-42a9-8853-6456eee4401b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645589190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
1645589190
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.56787946
Short name T435
Test name
Test status
Simulation time 39353700 ps
CPU time 15.72 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:26:18 PM PDT 24
Peak memory 275208 kb
Host smart-87e5cf2e-5cff-4344-bd1a-78a8852877c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56787946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.56787946
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.445781314
Short name T639
Test name
Test status
Simulation time 12666000 ps
CPU time 22.02 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:26:24 PM PDT 24
Peak memory 265228 kb
Host smart-bb479af7-76ba-4e30-ab52-850d2ff4cdf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445781314 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.445781314
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.111818347
Short name T849
Test name
Test status
Simulation time 4100690300 ps
CPU time 100.02 seconds
Started May 21 03:26:02 PM PDT 24
Finished May 21 03:27:43 PM PDT 24
Peak memory 262556 kb
Host smart-0d8433ef-a5ac-4c76-9a43-3e5ff2fccb22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111818347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h
w_sec_otp.111818347
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.65205919
Short name T11
Test name
Test status
Simulation time 710134900 ps
CPU time 115.17 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 259784 kb
Host smart-d508b8bc-425b-479f-8e49-c7ad68834b42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65205919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp
_reset.65205919
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2956880581
Short name T371
Test name
Test status
Simulation time 10145017300 ps
CPU time 85.46 seconds
Started May 21 03:26:03 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 263112 kb
Host smart-f6ecddcc-8f91-4172-bc3a-06b499a0d99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956880581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2956880581
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2939534172
Short name T85
Test name
Test status
Simulation time 35769400 ps
CPU time 169.97 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:28:52 PM PDT 24
Peak memory 276876 kb
Host smart-35968147-23d2-40b0-a794-c54148d2b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939534172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2939534172
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2458941166
Short name T493
Test name
Test status
Simulation time 65168300 ps
CPU time 14.35 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:30 PM PDT 24
Peak memory 265196 kb
Host smart-dbd9c321-7b10-4cdf-a926-f50ce75e5c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458941166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2458941166
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.451029658
Short name T516
Test name
Test status
Simulation time 32168400 ps
CPU time 15.63 seconds
Started May 21 03:26:08 PM PDT 24
Finished May 21 03:26:25 PM PDT 24
Peak memory 275172 kb
Host smart-6e993a84-7409-43fa-9c40-55b238bd0660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451029658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.451029658
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.1443804416
Short name T164
Test name
Test status
Simulation time 42014200 ps
CPU time 21.15 seconds
Started May 21 03:26:04 PM PDT 24
Finished May 21 03:26:25 PM PDT 24
Peak memory 265288 kb
Host smart-03e974a2-66f1-4c25-beee-b7ef68286e41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443804416 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.1443804416
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.237839010
Short name T633
Test name
Test status
Simulation time 2376144900 ps
CPU time 198.53 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:29:20 PM PDT 24
Peak memory 259296 kb
Host smart-6a2f5116-a527-4e59-bedc-4b830cf15c43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237839010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.237839010
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1320926289
Short name T565
Test name
Test status
Simulation time 72203000 ps
CPU time 130.2 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:28:12 PM PDT 24
Peak memory 260048 kb
Host smart-cefdd915-7c59-445a-bcd4-b334d8960c9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320926289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1320926289
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2147318089
Short name T502
Test name
Test status
Simulation time 49255500 ps
CPU time 122.89 seconds
Started May 21 03:26:01 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 275784 kb
Host smart-fdec6508-4807-4c77-b5c2-e2693f691212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147318089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2147318089
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3361149958
Short name T460
Test name
Test status
Simulation time 204997400 ps
CPU time 14.12 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 265168 kb
Host smart-50de9e54-c62c-4d23-abdc-93caa5052544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361149958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3361149958
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2310891965
Short name T535
Test name
Test status
Simulation time 26206000 ps
CPU time 16.38 seconds
Started May 21 03:26:08 PM PDT 24
Finished May 21 03:26:27 PM PDT 24
Peak memory 275696 kb
Host smart-af6994aa-4ab9-4baa-a037-31747e08979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310891965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2310891965
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.287930857
Short name T876
Test name
Test status
Simulation time 35928000 ps
CPU time 22.14 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:37 PM PDT 24
Peak memory 280668 kb
Host smart-c407f592-321f-44c8-85a3-c7a503942f6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287930857 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.287930857
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.564191565
Short name T937
Test name
Test status
Simulation time 9935664300 ps
CPU time 68.11 seconds
Started May 21 03:26:07 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 262644 kb
Host smart-c15528e0-0bd4-4edd-bf05-10d25d6ab555
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564191565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_h
w_sec_otp.564191565
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.3731221216
Short name T987
Test name
Test status
Simulation time 203762300 ps
CPU time 132.49 seconds
Started May 21 03:26:08 PM PDT 24
Finished May 21 03:28:23 PM PDT 24
Peak memory 259788 kb
Host smart-1d1c4a34-861e-4c37-aff5-1a4aed675c10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731221216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.3731221216
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3577616913
Short name T389
Test name
Test status
Simulation time 1521808100 ps
CPU time 75.75 seconds
Started May 21 03:26:09 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 264552 kb
Host smart-01caa773-afa2-4cb4-a751-ad30ee81bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577616913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3577616913
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3553867500
Short name T526
Test name
Test status
Simulation time 32322000 ps
CPU time 98.83 seconds
Started May 21 03:26:08 PM PDT 24
Finished May 21 03:27:49 PM PDT 24
Peak memory 276540 kb
Host smart-735c66ed-6eea-421f-be29-13aef461ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553867500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3553867500
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.147573114
Short name T1097
Test name
Test status
Simulation time 45806000 ps
CPU time 13.8 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:29 PM PDT 24
Peak memory 265180 kb
Host smart-e15695f3-c104-49bf-85ff-11f4f938aa89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147573114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.147573114
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2189508812
Short name T258
Test name
Test status
Simulation time 13908600 ps
CPU time 15.51 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:31 PM PDT 24
Peak memory 274888 kb
Host smart-6064dea3-3c2a-4c62-b8ce-0b44611b3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189508812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2189508812
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.1291026507
Short name T952
Test name
Test status
Simulation time 29048800 ps
CPU time 22.13 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:26:38 PM PDT 24
Peak memory 265316 kb
Host smart-452c6d56-6280-439c-aec0-bde43446604f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291026507 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.1291026507
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4162193207
Short name T1051
Test name
Test status
Simulation time 5576424500 ps
CPU time 113.67 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:28:08 PM PDT 24
Peak memory 261904 kb
Host smart-5dcf2172-656b-4504-a0c4-12f9d4b781f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162193207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.4162193207
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.3863997517
Short name T842
Test name
Test status
Simulation time 147466100 ps
CPU time 110.61 seconds
Started May 21 03:26:12 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 259956 kb
Host smart-81d4ad05-ca81-404f-8bcf-888385b659a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863997517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.3863997517
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.4162860247
Short name T874
Test name
Test status
Simulation time 3672996100 ps
CPU time 72.2 seconds
Started May 21 03:26:14 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 263220 kb
Host smart-71f981f5-ec12-4e68-b0c7-3cb011d7909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162860247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.4162860247
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.2253043638
Short name T791
Test name
Test status
Simulation time 43489500 ps
CPU time 75.24 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:27:31 PM PDT 24
Peak memory 274976 kb
Host smart-cb959b9e-5054-493b-a204-9e84598f9c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253043638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2253043638
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1845879375
Short name T841
Test name
Test status
Simulation time 30325800 ps
CPU time 13.66 seconds
Started May 21 03:26:25 PM PDT 24
Finished May 21 03:26:41 PM PDT 24
Peak memory 265176 kb
Host smart-4f53a07d-4172-4c80-8797-cdbce81734bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845879375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1845879375
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1311779653
Short name T870
Test name
Test status
Simulation time 63319100 ps
CPU time 15.46 seconds
Started May 21 03:26:28 PM PDT 24
Finished May 21 03:26:45 PM PDT 24
Peak memory 275104 kb
Host smart-8702f4b9-2997-4fd4-a3ab-22d0da2ec496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311779653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1311779653
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2128819402
Short name T362
Test name
Test status
Simulation time 13058700 ps
CPU time 22.27 seconds
Started May 21 03:26:21 PM PDT 24
Finished May 21 03:26:44 PM PDT 24
Peak memory 265280 kb
Host smart-aecae943-e7b9-472d-9328-3f702292ed91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128819402 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2128819402
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2444884249
Short name T1070
Test name
Test status
Simulation time 43125429500 ps
CPU time 139.51 seconds
Started May 21 03:26:21 PM PDT 24
Finished May 21 03:28:41 PM PDT 24
Peak memory 262612 kb
Host smart-355b3cca-d6db-463c-8e7c-2d9b8c81ab4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444884249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2444884249
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1595119587
Short name T935
Test name
Test status
Simulation time 39872000 ps
CPU time 132.32 seconds
Started May 21 03:26:21 PM PDT 24
Finished May 21 03:28:34 PM PDT 24
Peak memory 261112 kb
Host smart-05ff23b5-49f6-4318-b90f-c0994f4c9835
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595119587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1595119587
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.3233273894
Short name T373
Test name
Test status
Simulation time 2110207700 ps
CPU time 64.26 seconds
Started May 21 03:26:19 PM PDT 24
Finished May 21 03:27:24 PM PDT 24
Peak memory 263124 kb
Host smart-d4775a85-a7c2-403c-9f0f-98f21f4b6694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233273894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3233273894
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2265159787
Short name T738
Test name
Test status
Simulation time 35588600 ps
CPU time 121.5 seconds
Started May 21 03:26:13 PM PDT 24
Finished May 21 03:28:16 PM PDT 24
Peak memory 276868 kb
Host smart-7bfe1e29-9caa-4285-b10b-396196497d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265159787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2265159787
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.1695037700
Short name T1058
Test name
Test status
Simulation time 53231400 ps
CPU time 13.75 seconds
Started May 21 03:26:25 PM PDT 24
Finished May 21 03:26:41 PM PDT 24
Peak memory 265184 kb
Host smart-ca8e466f-9c0c-4ce0-b746-0196b6e32c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695037700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
1695037700
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.910782601
Short name T455
Test name
Test status
Simulation time 18474900 ps
CPU time 13.41 seconds
Started May 21 03:26:28 PM PDT 24
Finished May 21 03:26:43 PM PDT 24
Peak memory 275044 kb
Host smart-4f6b6dd8-f18f-4c0d-91e4-8605116cc81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910782601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.910782601
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1728152046
Short name T162
Test name
Test status
Simulation time 11033700 ps
CPU time 21.52 seconds
Started May 21 03:26:26 PM PDT 24
Finished May 21 03:26:50 PM PDT 24
Peak memory 265312 kb
Host smart-2027f3b6-879c-47c6-9423-5ef40d0bdeeb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728152046 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1728152046
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3920893055
Short name T704
Test name
Test status
Simulation time 649318800 ps
CPU time 63.01 seconds
Started May 21 03:26:24 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 262512 kb
Host smart-6e9e6489-ba93-4315-85f2-23df8edd0a78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920893055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.3920893055
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.239851958
Short name T707
Test name
Test status
Simulation time 38197000 ps
CPU time 108.12 seconds
Started May 21 03:26:26 PM PDT 24
Finished May 21 03:28:16 PM PDT 24
Peak memory 260128 kb
Host smart-5795fa91-bde8-47ff-8abb-8a5593b2d54a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239851958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.239851958
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2073194236
Short name T427
Test name
Test status
Simulation time 4261609400 ps
CPU time 71.8 seconds
Started May 21 03:26:23 PM PDT 24
Finished May 21 03:27:36 PM PDT 24
Peak memory 263152 kb
Host smart-91f1cd90-3b04-4ae7-a5e5-0a08351a35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073194236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2073194236
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3134210605
Short name T402
Test name
Test status
Simulation time 71061000 ps
CPU time 189.76 seconds
Started May 21 03:26:28 PM PDT 24
Finished May 21 03:29:39 PM PDT 24
Peak memory 280608 kb
Host smart-e1b1b884-10f7-447e-b3b8-064a17562b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134210605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3134210605
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.2961914831
Short name T585
Test name
Test status
Simulation time 52216300 ps
CPU time 13.74 seconds
Started May 21 03:26:29 PM PDT 24
Finished May 21 03:26:44 PM PDT 24
Peak memory 265168 kb
Host smart-b3c09eef-ade6-4edc-92e8-f4cc5d1d99c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961914831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
2961914831
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.2858515891
Short name T554
Test name
Test status
Simulation time 15156500 ps
CPU time 15.45 seconds
Started May 21 03:26:32 PM PDT 24
Finished May 21 03:26:49 PM PDT 24
Peak memory 275724 kb
Host smart-ee11a6a6-079e-485a-982a-8611e0d2b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858515891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2858515891
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.2201885151
Short name T384
Test name
Test status
Simulation time 12869900 ps
CPU time 22.23 seconds
Started May 21 03:26:26 PM PDT 24
Finished May 21 03:26:50 PM PDT 24
Peak memory 265268 kb
Host smart-45acd5c0-53b5-4db0-81c3-bdcfb0406f98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201885151 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.2201885151
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3651816379
Short name T578
Test name
Test status
Simulation time 2668784400 ps
CPU time 35.41 seconds
Started May 21 03:26:24 PM PDT 24
Finished May 21 03:27:02 PM PDT 24
Peak memory 262024 kb
Host smart-1ab3dc3b-f911-42e1-85e5-f34194d54f46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651816379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.3651816379
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.1033612692
Short name T509
Test name
Test status
Simulation time 73683700 ps
CPU time 133.52 seconds
Started May 21 03:26:25 PM PDT 24
Finished May 21 03:28:41 PM PDT 24
Peak memory 261140 kb
Host smart-836f463b-79b2-49bc-a37f-b5830d2a157c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033612692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.1033612692
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3592735686
Short name T680
Test name
Test status
Simulation time 512478200 ps
CPU time 50.68 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:27:23 PM PDT 24
Peak memory 263208 kb
Host smart-579a5352-8b8a-475a-a0f4-6342d267fe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592735686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3592735686
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.315503260
Short name T470
Test name
Test status
Simulation time 109433100 ps
CPU time 146.35 seconds
Started May 21 03:26:25 PM PDT 24
Finished May 21 03:28:53 PM PDT 24
Peak memory 276336 kb
Host smart-cdd4b8b0-4c6d-4ab7-8f26-ba51e3735582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315503260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.315503260
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.1956584334
Short name T736
Test name
Test status
Simulation time 237709200 ps
CPU time 13.78 seconds
Started May 21 03:26:33 PM PDT 24
Finished May 21 03:26:48 PM PDT 24
Peak memory 265156 kb
Host smart-c9ebee6d-d482-48f0-acc5-0a1dad493044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956584334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
1956584334
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2978739105
Short name T1026
Test name
Test status
Simulation time 59121700 ps
CPU time 13.46 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:26:45 PM PDT 24
Peak memory 275204 kb
Host smart-b90e7b07-1f49-46c1-966f-5dda3c3f6b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978739105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2978739105
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.297762203
Short name T165
Test name
Test status
Simulation time 20662000 ps
CPU time 22.06 seconds
Started May 21 03:26:31 PM PDT 24
Finished May 21 03:26:55 PM PDT 24
Peak memory 265304 kb
Host smart-e5bff8f1-f1cf-49a3-a478-3223e22e0301
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297762203 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.297762203
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2235556207
Short name T608
Test name
Test status
Simulation time 8530343600 ps
CPU time 130.27 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:28:43 PM PDT 24
Peak memory 262628 kb
Host smart-fdf54559-e246-4ddf-91d8-4b3ae7ba3c04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235556207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2235556207
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.251777489
Short name T153
Test name
Test status
Simulation time 37158200 ps
CPU time 137.05 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:28:49 PM PDT 24
Peak memory 259992 kb
Host smart-02b59b38-2835-4fce-8db0-253ebd37e29d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251777489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.251777489
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.2176554276
Short name T391
Test name
Test status
Simulation time 7126200000 ps
CPU time 78.09 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:27:50 PM PDT 24
Peak memory 263328 kb
Host smart-41b56667-af49-45c3-8b6c-973d2e9b4617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176554276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2176554276
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1148168837
Short name T814
Test name
Test status
Simulation time 108430000 ps
CPU time 124.38 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:28:36 PM PDT 24
Peak memory 276080 kb
Host smart-151bfab8-e26a-4381-bb1a-a645899e7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148168837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1148168837
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.189033987
Short name T895
Test name
Test status
Simulation time 48515200 ps
CPU time 13.72 seconds
Started May 21 03:17:59 PM PDT 24
Finished May 21 03:18:13 PM PDT 24
Peak memory 265176 kb
Host smart-8a85dd9b-f956-4f1a-a639-e680f714a6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189033987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.189033987
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.798757853
Short name T521
Test name
Test status
Simulation time 57109300 ps
CPU time 13.38 seconds
Started May 21 03:18:03 PM PDT 24
Finished May 21 03:18:17 PM PDT 24
Peak memory 276052 kb
Host smart-b44a775f-43af-4480-97ba-535e13990cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798757853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.798757853
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1421013795
Short name T381
Test name
Test status
Simulation time 15594700 ps
CPU time 20.78 seconds
Started May 21 03:17:53 PM PDT 24
Finished May 21 03:18:14 PM PDT 24
Peak memory 265380 kb
Host smart-740110fa-5d3a-49b7-90be-f9af7500b0ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421013795 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1421013795
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3853685789
Short name T584
Test name
Test status
Simulation time 20262561600 ps
CPU time 2356.82 seconds
Started May 21 03:17:40 PM PDT 24
Finished May 21 03:56:58 PM PDT 24
Peak memory 264228 kb
Host smart-98b8bc37-554b-4844-bb11-320059f58f5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853685789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3853685789
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1116107476
Short name T47
Test name
Test status
Simulation time 502615600 ps
CPU time 24.29 seconds
Started May 21 03:17:32 PM PDT 24
Finished May 21 03:17:57 PM PDT 24
Peak memory 265244 kb
Host smart-8aa7af53-7981-45b6-82ac-fef694046cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116107476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1116107476
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4122743347
Short name T286
Test name
Test status
Simulation time 10020251700 ps
CPU time 69.34 seconds
Started May 21 03:17:58 PM PDT 24
Finished May 21 03:19:08 PM PDT 24
Peak memory 280728 kb
Host smart-c2cad834-6725-424a-ae8e-7d86fffbae19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122743347 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4122743347
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2954426750
Short name T610
Test name
Test status
Simulation time 25706500 ps
CPU time 13.24 seconds
Started May 21 03:18:17 PM PDT 24
Finished May 21 03:18:31 PM PDT 24
Peak memory 265196 kb
Host smart-4fe35c98-c992-40db-ab59-de565b230776
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954426750 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2954426750
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2083015331
Short name T166
Test name
Test status
Simulation time 230198148800 ps
CPU time 1006.14 seconds
Started May 21 03:17:58 PM PDT 24
Finished May 21 03:34:45 PM PDT 24
Peak memory 263552 kb
Host smart-6bac329a-6b66-4f93-827f-ab77cbf16902
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083015331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2083015331
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.4101431327
Short name T475
Test name
Test status
Simulation time 2426213400 ps
CPU time 164.03 seconds
Started May 21 03:17:35 PM PDT 24
Finished May 21 03:20:19 PM PDT 24
Peak memory 262028 kb
Host smart-fbc6ad6b-cbce-41f3-85f6-d59ca99366a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101431327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.4101431327
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.3590539267
Short name T434
Test name
Test status
Simulation time 723747800 ps
CPU time 147.06 seconds
Started May 21 03:17:58 PM PDT 24
Finished May 21 03:20:26 PM PDT 24
Peak memory 293112 kb
Host smart-e305d7a6-d0aa-4cf7-89be-02ceefb13a94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590539267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.3590539267
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1099898808
Short name T318
Test name
Test status
Simulation time 23969258100 ps
CPU time 491.26 seconds
Started May 21 03:18:00 PM PDT 24
Finished May 21 03:26:11 PM PDT 24
Peak memory 284340 kb
Host smart-05a3fbb7-1314-47d1-8584-82481456ea4a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099898808 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1099898808
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.425456361
Short name T28
Test name
Test status
Simulation time 2070272600 ps
CPU time 68.07 seconds
Started May 21 03:17:47 PM PDT 24
Finished May 21 03:18:55 PM PDT 24
Peak memory 265140 kb
Host smart-79e18526-eeac-425a-a766-9717ee38f768
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425456361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.flash_ctrl_intr_wr.425456361
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1150709087
Short name T802
Test name
Test status
Simulation time 77914920700 ps
CPU time 175.13 seconds
Started May 21 03:17:47 PM PDT 24
Finished May 21 03:20:43 PM PDT 24
Peak memory 259668 kb
Host smart-1c971acf-af9c-4966-ab68-24ed3b9c6044
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115
0709087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1150709087
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.825589598
Short name T580
Test name
Test status
Simulation time 45013000 ps
CPU time 13.27 seconds
Started May 21 03:17:52 PM PDT 24
Finished May 21 03:18:06 PM PDT 24
Peak memory 265184 kb
Host smart-57d1c29f-0790-4a28-a893-5142a92b5211
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825589598 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.825589598
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.1352740345
Short name T100
Test name
Test status
Simulation time 8958805400 ps
CPU time 224.78 seconds
Started May 21 03:17:30 PM PDT 24
Finished May 21 03:21:15 PM PDT 24
Peak memory 273336 kb
Host smart-9a51fa47-f456-439d-97b3-0321bd584489
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352740345 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.1352740345
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.1585446220
Short name T577
Test name
Test status
Simulation time 238475700 ps
CPU time 131.85 seconds
Started May 21 03:17:24 PM PDT 24
Finished May 21 03:19:37 PM PDT 24
Peak memory 261164 kb
Host smart-03b05306-67e6-44ae-bf93-6fbe52ef9812
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585446220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.1585446220
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.2067028171
Short name T861
Test name
Test status
Simulation time 48951800 ps
CPU time 195.02 seconds
Started May 21 03:17:24 PM PDT 24
Finished May 21 03:20:39 PM PDT 24
Peak memory 262416 kb
Host smart-7844bffb-29af-45a2-b529-1ef083962ca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067028171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2067028171
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2772388216
Short name T414
Test name
Test status
Simulation time 1633459900 ps
CPU time 27.89 seconds
Started May 21 03:17:47 PM PDT 24
Finished May 21 03:18:15 PM PDT 24
Peak memory 259128 kb
Host smart-b04a5f47-1e0a-41ba-a17d-a413346ffb89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772388216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.2772388216
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.637444278
Short name T978
Test name
Test status
Simulation time 829487400 ps
CPU time 599.14 seconds
Started May 21 03:17:20 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 284896 kb
Host smart-d17893b7-7d77-4781-a562-63c0f97687e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637444278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.637444278
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.633080738
Short name T843
Test name
Test status
Simulation time 620171300 ps
CPU time 113.3 seconds
Started May 21 03:17:56 PM PDT 24
Finished May 21 03:19:50 PM PDT 24
Peak memory 281676 kb
Host smart-d341cb4d-f3d9-4c63-9866-abe6ffda3895
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633080738 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_ro.633080738
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.3038219226
Short name T613
Test name
Test status
Simulation time 619483000 ps
CPU time 142.31 seconds
Started May 21 03:17:41 PM PDT 24
Finished May 21 03:20:04 PM PDT 24
Peak memory 281784 kb
Host smart-825260fc-1c4f-4eab-8906-209d5ec15e8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3038219226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3038219226
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2484543999
Short name T191
Test name
Test status
Simulation time 7602970400 ps
CPU time 140.13 seconds
Started May 21 03:18:00 PM PDT 24
Finished May 21 03:20:20 PM PDT 24
Peak memory 281724 kb
Host smart-2be0b2f3-d986-4866-b666-44ca81960318
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484543999 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2484543999
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3475631757
Short name T328
Test name
Test status
Simulation time 12919654500 ps
CPU time 560.09 seconds
Started May 21 03:17:41 PM PDT 24
Finished May 21 03:27:02 PM PDT 24
Peak memory 313756 kb
Host smart-b20cb8ba-23de-441a-90b0-c5b4b5081a2e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475631757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3475631757
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.2016818524
Short name T255
Test name
Test status
Simulation time 13407064500 ps
CPU time 550.89 seconds
Started May 21 03:17:49 PM PDT 24
Finished May 21 03:27:01 PM PDT 24
Peak memory 331608 kb
Host smart-45edf036-5208-421b-8c76-8208a00c1f35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016818524 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.2016818524
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.639327770
Short name T332
Test name
Test status
Simulation time 45927200 ps
CPU time 31.82 seconds
Started May 21 03:17:49 PM PDT 24
Finished May 21 03:18:22 PM PDT 24
Peak memory 272592 kb
Host smart-927ec9bb-4525-47ea-a486-fd83383ffab2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639327770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_rw_evict.639327770
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.3963503111
Short name T189
Test name
Test status
Simulation time 8508337500 ps
CPU time 735.73 seconds
Started May 21 03:17:57 PM PDT 24
Finished May 21 03:30:14 PM PDT 24
Peak memory 313552 kb
Host smart-c0dd4618-8aa7-4adc-b821-290d42579ed3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963503111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.3963503111
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3527146671
Short name T446
Test name
Test status
Simulation time 1941524200 ps
CPU time 58.1 seconds
Started May 21 03:17:54 PM PDT 24
Finished May 21 03:18:52 PM PDT 24
Peak memory 263472 kb
Host smart-9d7bf568-829c-43c2-8cc4-e8ff1e2182ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527146671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3527146671
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.103705067
Short name T438
Test name
Test status
Simulation time 22616200 ps
CPU time 97.75 seconds
Started May 21 03:17:13 PM PDT 24
Finished May 21 03:18:53 PM PDT 24
Peak memory 275344 kb
Host smart-f0a3f8e0-653a-4712-9b31-816c1280ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103705067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.103705067
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3986746566
Short name T696
Test name
Test status
Simulation time 4162128000 ps
CPU time 183.84 seconds
Started May 21 03:17:35 PM PDT 24
Finished May 21 03:20:40 PM PDT 24
Peak memory 265136 kb
Host smart-aa709383-35e2-4eb7-b639-39bd628beced
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986746566 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.3986746566
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.4206299825
Short name T411
Test name
Test status
Simulation time 27494100 ps
CPU time 15.7 seconds
Started May 21 03:26:31 PM PDT 24
Finished May 21 03:26:48 PM PDT 24
Peak memory 275696 kb
Host smart-372fbbc9-7cb7-433e-a286-c89299f1725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206299825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.4206299825
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.412476869
Short name T152
Test name
Test status
Simulation time 149427900 ps
CPU time 110.02 seconds
Started May 21 03:26:30 PM PDT 24
Finished May 21 03:28:22 PM PDT 24
Peak memory 260020 kb
Host smart-e370c43e-3581-44c1-8f21-3da4c738cc7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412476869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.412476869
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.1824548982
Short name T597
Test name
Test status
Simulation time 24717500 ps
CPU time 15.62 seconds
Started May 21 03:26:35 PM PDT 24
Finished May 21 03:26:52 PM PDT 24
Peak memory 275188 kb
Host smart-41534bf2-aa1e-4516-b898-4bc9c9ce30f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824548982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1824548982
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3176670421
Short name T491
Test name
Test status
Simulation time 145764900 ps
CPU time 136.42 seconds
Started May 21 03:26:36 PM PDT 24
Finished May 21 03:28:53 PM PDT 24
Peak memory 259780 kb
Host smart-5e284765-85b9-46ae-ada5-f8b96aca5c3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176670421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3176670421
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3247519085
Short name T1057
Test name
Test status
Simulation time 28035800 ps
CPU time 13.1 seconds
Started May 21 03:26:34 PM PDT 24
Finished May 21 03:26:48 PM PDT 24
Peak memory 275096 kb
Host smart-75b028e8-c9e8-4040-9a20-a48435dee4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247519085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3247519085
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2765662706
Short name T694
Test name
Test status
Simulation time 556524100 ps
CPU time 131.16 seconds
Started May 21 03:26:34 PM PDT 24
Finished May 21 03:28:47 PM PDT 24
Peak memory 260016 kb
Host smart-d1f3c8c9-3d31-45cb-a14e-29bb773c5f32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765662706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2765662706
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.3662715911
Short name T698
Test name
Test status
Simulation time 116548600 ps
CPU time 15.62 seconds
Started May 21 03:26:36 PM PDT 24
Finished May 21 03:26:53 PM PDT 24
Peak memory 275656 kb
Host smart-7ebaaf41-77a1-4ae1-b0ad-78f711d45a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662715911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3662715911
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.2959535219
Short name T795
Test name
Test status
Simulation time 183484800 ps
CPU time 131.5 seconds
Started May 21 03:26:36 PM PDT 24
Finished May 21 03:28:48 PM PDT 24
Peak memory 261080 kb
Host smart-81545b19-4287-40bd-aca0-0eb81e90f77b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959535219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.2959535219
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.741111305
Short name T893
Test name
Test status
Simulation time 14251000 ps
CPU time 13.16 seconds
Started May 21 03:26:36 PM PDT 24
Finished May 21 03:26:50 PM PDT 24
Peak memory 275064 kb
Host smart-34d51ded-81dc-417f-809a-b0acfa2a9af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741111305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.741111305
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1299547224
Short name T500
Test name
Test status
Simulation time 86900900 ps
CPU time 133.22 seconds
Started May 21 03:26:35 PM PDT 24
Finished May 21 03:28:49 PM PDT 24
Peak memory 259960 kb
Host smart-3f2e67f1-087f-4870-87b8-9a5bfada842c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299547224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1299547224
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.50395841
Short name T454
Test name
Test status
Simulation time 29476400 ps
CPU time 13.79 seconds
Started May 21 03:26:42 PM PDT 24
Finished May 21 03:26:56 PM PDT 24
Peak memory 275108 kb
Host smart-94a19caa-4ec6-452e-b078-c28c21519a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50395841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.50395841
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1918096811
Short name T979
Test name
Test status
Simulation time 89065200 ps
CPU time 133.73 seconds
Started May 21 03:26:35 PM PDT 24
Finished May 21 03:28:50 PM PDT 24
Peak memory 261032 kb
Host smart-62ba4645-ac3c-4e84-838b-a319485c94b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918096811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1918096811
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.4020425663
Short name T953
Test name
Test status
Simulation time 32344900 ps
CPU time 13.52 seconds
Started May 21 03:26:41 PM PDT 24
Finished May 21 03:26:55 PM PDT 24
Peak memory 274996 kb
Host smart-05af2161-8742-4528-a51b-5d34ab298cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020425663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4020425663
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1727707377
Short name T1046
Test name
Test status
Simulation time 40354900 ps
CPU time 130.06 seconds
Started May 21 03:26:40 PM PDT 24
Finished May 21 03:28:50 PM PDT 24
Peak memory 260100 kb
Host smart-3a5db890-8907-4b2e-8f36-0d4e112e0581
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727707377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1727707377
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3002902853
Short name T857
Test name
Test status
Simulation time 32492400 ps
CPU time 15.49 seconds
Started May 21 03:26:41 PM PDT 24
Finished May 21 03:26:57 PM PDT 24
Peak memory 276024 kb
Host smart-137a9b2d-2766-4c90-b4f0-d37814a0ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002902853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3002902853
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3922349330
Short name T567
Test name
Test status
Simulation time 46225300 ps
CPU time 135.54 seconds
Started May 21 03:26:39 PM PDT 24
Finished May 21 03:28:56 PM PDT 24
Peak memory 259856 kb
Host smart-74827d3f-a016-49ff-813c-140910ef5486
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922349330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3922349330
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.879899837
Short name T1036
Test name
Test status
Simulation time 15330100 ps
CPU time 16.15 seconds
Started May 21 03:26:49 PM PDT 24
Finished May 21 03:27:07 PM PDT 24
Peak memory 275640 kb
Host smart-8b770ef1-bd60-4f4d-b693-9753f28e8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879899837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.879899837
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.3841379152
Short name T1052
Test name
Test status
Simulation time 139346700 ps
CPU time 111.28 seconds
Started May 21 03:26:41 PM PDT 24
Finished May 21 03:28:33 PM PDT 24
Peak memory 259924 kb
Host smart-d4f6544d-e9e0-47e1-b4f3-95ab39e64724
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841379152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.3841379152
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.68195912
Short name T413
Test name
Test status
Simulation time 71700000 ps
CPU time 15.94 seconds
Started May 21 03:26:51 PM PDT 24
Finished May 21 03:27:07 PM PDT 24
Peak memory 275752 kb
Host smart-cdb53c82-854f-4fd3-8089-1668786671ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68195912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.68195912
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3119825393
Short name T154
Test name
Test status
Simulation time 144108500 ps
CPU time 130.48 seconds
Started May 21 03:26:47 PM PDT 24
Finished May 21 03:28:58 PM PDT 24
Peak memory 259856 kb
Host smart-adb0227d-428d-435f-a76b-2ab7e86e2382
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119825393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3119825393
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.1106405007
Short name T1010
Test name
Test status
Simulation time 83321500 ps
CPU time 13.73 seconds
Started May 21 03:18:27 PM PDT 24
Finished May 21 03:18:43 PM PDT 24
Peak memory 265128 kb
Host smart-2c93d6a0-c0c3-4c86-aa55-5f11f2ea9379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106405007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1
106405007
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1442349002
Short name T912
Test name
Test status
Simulation time 81119800 ps
CPU time 13.66 seconds
Started May 21 03:18:23 PM PDT 24
Finished May 21 03:18:38 PM PDT 24
Peak memory 276064 kb
Host smart-ef0e6010-a1b1-4409-82e1-1e76dee7728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442349002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1442349002
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.4029327930
Short name T72
Test name
Test status
Simulation time 27502100 ps
CPU time 21.02 seconds
Started May 21 03:18:21 PM PDT 24
Finished May 21 03:18:44 PM PDT 24
Peak memory 265276 kb
Host smart-74676312-8224-483b-a36d-6796c5e73aa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029327930 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.4029327930
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3012820454
Short name T1018
Test name
Test status
Simulation time 2097594000 ps
CPU time 2149.84 seconds
Started May 21 03:18:10 PM PDT 24
Finished May 21 03:54:01 PM PDT 24
Peak memory 264584 kb
Host smart-05b4aa8b-0b8f-4bb9-aeaa-5cd3aff8a883
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012820454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3012820454
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.854381794
Short name T289
Test name
Test status
Simulation time 1327189400 ps
CPU time 892.04 seconds
Started May 21 03:18:04 PM PDT 24
Finished May 21 03:32:57 PM PDT 24
Peak memory 273376 kb
Host smart-19f516a0-fdd5-4e61-aaa7-7270f22cb20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854381794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.854381794
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.1664766202
Short name T1002
Test name
Test status
Simulation time 193307300 ps
CPU time 21.69 seconds
Started May 21 03:18:21 PM PDT 24
Finished May 21 03:18:44 PM PDT 24
Peak memory 265192 kb
Host smart-87784004-40fc-4aa5-b2da-93b580991ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664766202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1664766202
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3772186118
Short name T143
Test name
Test status
Simulation time 10013986600 ps
CPU time 261.87 seconds
Started May 21 03:18:45 PM PDT 24
Finished May 21 03:23:10 PM PDT 24
Peak memory 283360 kb
Host smart-00c1fa1e-1e66-41ce-abcb-9e2177477009
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772186118 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3772186118
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.705094202
Short name T562
Test name
Test status
Simulation time 26426300 ps
CPU time 13.6 seconds
Started May 21 03:18:37 PM PDT 24
Finished May 21 03:18:54 PM PDT 24
Peak memory 265352 kb
Host smart-65352cb8-b5da-4e6c-946f-76f65d0e5455
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705094202 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.705094202
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.1964826455
Short name T1056
Test name
Test status
Simulation time 40124548300 ps
CPU time 798.87 seconds
Started May 21 03:18:28 PM PDT 24
Finished May 21 03:31:49 PM PDT 24
Peak memory 264476 kb
Host smart-0cc8330e-417f-4ba4-aecc-0e442a081940
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964826455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.1964826455
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2249096752
Short name T667
Test name
Test status
Simulation time 2846035300 ps
CPU time 225.26 seconds
Started May 21 03:18:06 PM PDT 24
Finished May 21 03:21:52 PM PDT 24
Peak memory 262600 kb
Host smart-267d46b3-8580-4547-b8cb-59394901dbe1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249096752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.2249096752
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.4123752282
Short name T560
Test name
Test status
Simulation time 5528034400 ps
CPU time 261.28 seconds
Started May 21 03:18:11 PM PDT 24
Finished May 21 03:22:33 PM PDT 24
Peak memory 284136 kb
Host smart-8e39a1b4-2be1-4955-a21c-4ef879d947c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123752282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.4123752282
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1667900354
Short name T831
Test name
Test status
Simulation time 49057909500 ps
CPU time 279.26 seconds
Started May 21 03:18:31 PM PDT 24
Finished May 21 03:23:13 PM PDT 24
Peak memory 284204 kb
Host smart-0e4c0cca-eb0e-4eaf-b3ad-2eeeea20d73a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667900354 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1667900354
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.445633703
Short name T444
Test name
Test status
Simulation time 8612914700 ps
CPU time 69.63 seconds
Started May 21 03:18:25 PM PDT 24
Finished May 21 03:19:36 PM PDT 24
Peak memory 265252 kb
Host smart-e593ea7b-011c-4daa-a755-6b24e7eabbf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445633703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.flash_ctrl_intr_wr.445633703
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.147358801
Short name T687
Test name
Test status
Simulation time 24187148000 ps
CPU time 214.18 seconds
Started May 21 03:18:20 PM PDT 24
Finished May 21 03:21:56 PM PDT 24
Peak memory 265156 kb
Host smart-230050a1-91c0-4ad7-ae16-8e63d35d7548
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147
358801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.147358801
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2548755453
Short name T641
Test name
Test status
Simulation time 6543701000 ps
CPU time 70.59 seconds
Started May 21 03:18:05 PM PDT 24
Finished May 21 03:19:17 PM PDT 24
Peak memory 263624 kb
Host smart-88e7a2a7-d275-4a30-bbdc-554766ee8db1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548755453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2548755453
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3652176885
Short name T132
Test name
Test status
Simulation time 24624100 ps
CPU time 13.63 seconds
Started May 21 03:18:20 PM PDT 24
Finished May 21 03:18:36 PM PDT 24
Peak memory 265232 kb
Host smart-7b0b01ea-a929-4cc8-88c6-7ab91ff5f0a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652176885 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3652176885
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.3822412439
Short name T573
Test name
Test status
Simulation time 125623700 ps
CPU time 129.56 seconds
Started May 21 03:18:04 PM PDT 24
Finished May 21 03:20:14 PM PDT 24
Peak memory 259972 kb
Host smart-82f64c66-26ed-4c7d-a14f-1ea3ad8a407d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822412439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.3822412439
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1492819831
Short name T878
Test name
Test status
Simulation time 933499300 ps
CPU time 519.4 seconds
Started May 21 03:18:11 PM PDT 24
Finished May 21 03:26:51 PM PDT 24
Peak memory 262544 kb
Host smart-7e5cd3a6-d373-4a1a-b867-970595604f78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492819831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1492819831
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.3367916252
Short name T889
Test name
Test status
Simulation time 19730800 ps
CPU time 13.76 seconds
Started May 21 03:18:16 PM PDT 24
Finished May 21 03:18:30 PM PDT 24
Peak memory 258744 kb
Host smart-2508084e-d8f0-43c4-accd-da559df33c22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367916252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.3367916252
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.612338296
Short name T858
Test name
Test status
Simulation time 1517183500 ps
CPU time 1035.38 seconds
Started May 21 03:18:29 PM PDT 24
Finished May 21 03:35:46 PM PDT 24
Peak memory 284608 kb
Host smart-173f26f5-68ee-4702-8a95-59d0764072fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612338296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.612338296
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.1573933362
Short name T88
Test name
Test status
Simulation time 122213700 ps
CPU time 38.06 seconds
Started May 21 03:18:31 PM PDT 24
Finished May 21 03:19:12 PM PDT 24
Peak memory 276784 kb
Host smart-46649ed8-da33-4c2e-8cec-a4fc15cabfe7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573933362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.1573933362
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.4152481603
Short name T417
Test name
Test status
Simulation time 522796800 ps
CPU time 131.46 seconds
Started May 21 03:18:38 PM PDT 24
Finished May 21 03:20:54 PM PDT 24
Peak memory 281772 kb
Host smart-79c840f5-6ee3-479e-bd8d-d94ab1e33c97
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152481603 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.4152481603
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3546739246
Short name T468
Test name
Test status
Simulation time 2137958700 ps
CPU time 140.94 seconds
Started May 21 03:18:22 PM PDT 24
Finished May 21 03:20:45 PM PDT 24
Peak memory 281728 kb
Host smart-97dcb0af-d6b7-4f18-a17b-4a527982f8c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3546739246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3546739246
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3300606591
Short name T720
Test name
Test status
Simulation time 2388806000 ps
CPU time 120.17 seconds
Started May 21 03:18:08 PM PDT 24
Finished May 21 03:20:09 PM PDT 24
Peak memory 281740 kb
Host smart-bff6362e-1d3a-4d63-8d41-01310fd38047
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300606591 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3300606591
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.2314563572
Short name T1025
Test name
Test status
Simulation time 35363131500 ps
CPU time 532.69 seconds
Started May 21 03:18:05 PM PDT 24
Finished May 21 03:26:59 PM PDT 24
Peak memory 313872 kb
Host smart-488b70d6-6047-4a3a-b28d-a70c9400a498
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314563572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.2314563572
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.1437487022
Short name T834
Test name
Test status
Simulation time 34804500 ps
CPU time 32.79 seconds
Started May 21 03:18:21 PM PDT 24
Finished May 21 03:18:56 PM PDT 24
Peak memory 274580 kb
Host smart-8c55546d-5eae-4691-8ad9-5c0cf53a3e09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437487022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.1437487022
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.334344944
Short name T91
Test name
Test status
Simulation time 28526600 ps
CPU time 31.23 seconds
Started May 21 03:18:33 PM PDT 24
Finished May 21 03:19:07 PM PDT 24
Peak memory 276372 kb
Host smart-5e700de1-d65c-4a09-a5ad-678e74e9af02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334344944 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.334344944
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.3893154040
Short name T586
Test name
Test status
Simulation time 13998080000 ps
CPU time 661.53 seconds
Started May 21 03:18:10 PM PDT 24
Finished May 21 03:29:12 PM PDT 24
Peak memory 320108 kb
Host smart-17f6e09e-d299-4a4a-ac91-ae0ede067f0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893154040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.3893154040
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1502480234
Short name T1037
Test name
Test status
Simulation time 1445466800 ps
CPU time 73.59 seconds
Started May 21 03:18:22 PM PDT 24
Finished May 21 03:19:37 PM PDT 24
Peak memory 262300 kb
Host smart-ba1be2b3-ea08-47e4-b64a-3fc60b973e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502480234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1502480234
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1798314003
Short name T107
Test name
Test status
Simulation time 33106900 ps
CPU time 97.49 seconds
Started May 21 03:18:19 PM PDT 24
Finished May 21 03:19:58 PM PDT 24
Peak memory 275368 kb
Host smart-d373a80a-6979-4f83-858f-e93b28445fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798314003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1798314003
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1286722275
Short name T408
Test name
Test status
Simulation time 43205228200 ps
CPU time 175.28 seconds
Started May 21 03:18:09 PM PDT 24
Finished May 21 03:21:05 PM PDT 24
Peak memory 259240 kb
Host smart-2df9b5eb-a64c-4854-a3ea-344b6953247a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286722275 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.1286722275
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1839406889
Short name T810
Test name
Test status
Simulation time 67692900 ps
CPU time 15.82 seconds
Started May 21 03:26:51 PM PDT 24
Finished May 21 03:27:08 PM PDT 24
Peak memory 275132 kb
Host smart-7d90d1b4-6dd3-412b-9778-c2a389cc9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839406889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1839406889
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.386134964
Short name T961
Test name
Test status
Simulation time 54357700 ps
CPU time 129.64 seconds
Started May 21 03:26:49 PM PDT 24
Finished May 21 03:29:00 PM PDT 24
Peak memory 264288 kb
Host smart-ad5c0e70-21dc-416e-b2ad-7898f057b7af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386134964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot
p_reset.386134964
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.104288415
Short name T510
Test name
Test status
Simulation time 115025800 ps
CPU time 15.79 seconds
Started May 21 03:26:49 PM PDT 24
Finished May 21 03:27:06 PM PDT 24
Peak memory 275604 kb
Host smart-22d440e2-fc6f-4067-92f8-a9b654ded94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104288415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.104288415
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.36327509
Short name T614
Test name
Test status
Simulation time 687224200 ps
CPU time 130.28 seconds
Started May 21 03:26:47 PM PDT 24
Finished May 21 03:28:58 PM PDT 24
Peak memory 261172 kb
Host smart-7b2cb3a9-6374-4d77-aff1-706123c528bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36327509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp
_reset.36327509
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3224959592
Short name T523
Test name
Test status
Simulation time 17702200 ps
CPU time 16.3 seconds
Started May 21 03:26:52 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 274928 kb
Host smart-aa83642b-cb34-4ea0-bc1b-84f271578d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224959592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3224959592
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3380195998
Short name T596
Test name
Test status
Simulation time 135628100 ps
CPU time 134.49 seconds
Started May 21 03:26:48 PM PDT 24
Finished May 21 03:29:03 PM PDT 24
Peak memory 263684 kb
Host smart-4e76165b-2e29-45b7-a361-a4267141f9d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380195998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3380195998
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1914016258
Short name T993
Test name
Test status
Simulation time 62216600 ps
CPU time 16 seconds
Started May 21 03:26:47 PM PDT 24
Finished May 21 03:27:04 PM PDT 24
Peak memory 275740 kb
Host smart-48137d89-902b-473c-a978-02f1a056199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914016258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1914016258
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.970331051
Short name T676
Test name
Test status
Simulation time 161534400 ps
CPU time 110.22 seconds
Started May 21 03:26:49 PM PDT 24
Finished May 21 03:28:41 PM PDT 24
Peak memory 259988 kb
Host smart-ef55c3e1-4f84-424c-a257-158496c63498
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970331051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.970331051
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.219371083
Short name T193
Test name
Test status
Simulation time 16109100 ps
CPU time 16.2 seconds
Started May 21 03:26:47 PM PDT 24
Finished May 21 03:27:05 PM PDT 24
Peak memory 275152 kb
Host smart-8bc02fa6-9d52-4436-9d5d-e6f4a355b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219371083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.219371083
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2660699465
Short name T624
Test name
Test status
Simulation time 40054700 ps
CPU time 131.69 seconds
Started May 21 03:26:47 PM PDT 24
Finished May 21 03:28:59 PM PDT 24
Peak memory 261024 kb
Host smart-a3107367-e97a-4bff-8b25-d82c07ae1670
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660699465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2660699465
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2092564181
Short name T199
Test name
Test status
Simulation time 22513900 ps
CPU time 15.77 seconds
Started May 21 03:26:49 PM PDT 24
Finished May 21 03:27:06 PM PDT 24
Peak memory 275644 kb
Host smart-8741eb89-600f-4f0c-8fb2-47e9e6dfcb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092564181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2092564181
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3552614239
Short name T145
Test name
Test status
Simulation time 38330600 ps
CPU time 109.59 seconds
Started May 21 03:26:50 PM PDT 24
Finished May 21 03:28:41 PM PDT 24
Peak memory 259956 kb
Host smart-44d31f66-35c7-464f-b489-5bdffd2b7591
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552614239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3552614239
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1368198069
Short name T399
Test name
Test status
Simulation time 18078800 ps
CPU time 16.18 seconds
Started May 21 03:26:53 PM PDT 24
Finished May 21 03:27:10 PM PDT 24
Peak memory 276004 kb
Host smart-20ab525e-dde9-4e40-aab5-ac84dc395f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368198069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1368198069
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.1560593186
Short name T828
Test name
Test status
Simulation time 79378200 ps
CPU time 132.49 seconds
Started May 21 03:26:48 PM PDT 24
Finished May 21 03:29:01 PM PDT 24
Peak memory 259800 kb
Host smart-9daffaf4-1431-46f0-8468-0d9f9975c1c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560593186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.1560593186
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.2960568936
Short name T746
Test name
Test status
Simulation time 29365200 ps
CPU time 16.26 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:27:12 PM PDT 24
Peak memory 275128 kb
Host smart-d8bfc72c-ab4d-4f67-8438-3cc0ad2691eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960568936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2960568936
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.4207001679
Short name T792
Test name
Test status
Simulation time 42654700 ps
CPU time 128.8 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:29:04 PM PDT 24
Peak memory 261052 kb
Host smart-65e88389-d123-463e-bd2c-0acae969740c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207001679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.4207001679
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.3746097238
Short name T740
Test name
Test status
Simulation time 43825100 ps
CPU time 13.79 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:27:10 PM PDT 24
Peak memory 275920 kb
Host smart-5f37ec13-44d5-48be-96a3-e5018bbe685b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746097238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3746097238
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.1532290724
Short name T662
Test name
Test status
Simulation time 21736400 ps
CPU time 13.38 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 275760 kb
Host smart-c4ea8fd8-7b13-48bd-b9b5-94f17a7f994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532290724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1532290724
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2766041250
Short name T429
Test name
Test status
Simulation time 44060100 ps
CPU time 138.21 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:29:13 PM PDT 24
Peak memory 261136 kb
Host smart-1711cca0-65a7-493c-a3b2-b10ad5274a9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766041250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2766041250
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.155772451
Short name T856
Test name
Test status
Simulation time 32593900 ps
CPU time 13.7 seconds
Started May 21 03:19:13 PM PDT 24
Finished May 21 03:19:28 PM PDT 24
Peak memory 265152 kb
Host smart-2ffd56d6-9c27-4b17-9313-f0efa65d9503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155772451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.155772451
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.808676950
Short name T664
Test name
Test status
Simulation time 16706600 ps
CPU time 16 seconds
Started May 21 03:18:56 PM PDT 24
Finished May 21 03:19:15 PM PDT 24
Peak memory 275160 kb
Host smart-d906c3b5-704a-4d05-a122-5695dcc77c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808676950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.808676950
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.895406103
Short name T859
Test name
Test status
Simulation time 18974600 ps
CPU time 20.36 seconds
Started May 21 03:19:00 PM PDT 24
Finished May 21 03:19:23 PM PDT 24
Peak memory 265372 kb
Host smart-bb000c7d-0711-46b2-95f8-417dc275384e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895406103 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.895406103
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3174618143
Short name T232
Test name
Test status
Simulation time 4735887900 ps
CPU time 2305.83 seconds
Started May 21 03:19:01 PM PDT 24
Finished May 21 03:57:29 PM PDT 24
Peak memory 264888 kb
Host smart-01240730-8b2b-478a-b074-756bc0ef33e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174618143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3174618143
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3301586068
Short name T798
Test name
Test status
Simulation time 3492358800 ps
CPU time 1150.7 seconds
Started May 21 03:18:58 PM PDT 24
Finished May 21 03:38:11 PM PDT 24
Peak memory 273380 kb
Host smart-ba82edcc-b169-45be-9066-c53b3b42da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301586068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3301586068
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1845749353
Short name T971
Test name
Test status
Simulation time 158056900 ps
CPU time 25.32 seconds
Started May 21 03:18:45 PM PDT 24
Finished May 21 03:19:13 PM PDT 24
Peak memory 265216 kb
Host smart-340bab90-bb57-47d4-b6ec-1ad3c2153e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845749353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1845749353
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3583378803
Short name T144
Test name
Test status
Simulation time 10035287500 ps
CPU time 113.02 seconds
Started May 21 03:19:15 PM PDT 24
Finished May 21 03:21:09 PM PDT 24
Peak memory 274204 kb
Host smart-5593afc2-9230-47c7-b09b-cf75e1d97cc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583378803 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3583378803
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3973108689
Short name T283
Test name
Test status
Simulation time 39995400 ps
CPU time 14.14 seconds
Started May 21 03:19:15 PM PDT 24
Finished May 21 03:19:30 PM PDT 24
Peak memory 265356 kb
Host smart-b53639fa-0b30-47ee-80b0-acf464aa446b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973108689 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3973108689
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.395405358
Short name T787
Test name
Test status
Simulation time 80135297000 ps
CPU time 822.24 seconds
Started May 21 03:18:51 PM PDT 24
Finished May 21 03:32:35 PM PDT 24
Peak memory 264480 kb
Host smart-524089ae-9ab8-42b9-9ecc-421ecaa959fa
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395405358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.flash_ctrl_hw_rma_reset.395405358
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3699401426
Short name T670
Test name
Test status
Simulation time 2455312900 ps
CPU time 89.29 seconds
Started May 21 03:18:43 PM PDT 24
Finished May 21 03:20:16 PM PDT 24
Peak memory 262516 kb
Host smart-46c36e10-99da-4eed-8793-a73866361113
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699401426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3699401426
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.897000139
Short name T236
Test name
Test status
Simulation time 2220847800 ps
CPU time 263.37 seconds
Started May 21 03:18:59 PM PDT 24
Finished May 21 03:23:25 PM PDT 24
Peak memory 284104 kb
Host smart-d8c3222b-7dd1-4002-b774-d2090cce6b74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897000139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.897000139
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3137776954
Short name T660
Test name
Test status
Simulation time 24382228900 ps
CPU time 329.23 seconds
Started May 21 03:18:49 PM PDT 24
Finished May 21 03:24:19 PM PDT 24
Peak memory 293324 kb
Host smart-22fae605-fdbe-4c4b-a6ac-d4b059d8d46f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137776954 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3137776954
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.2897995072
Short name T473
Test name
Test status
Simulation time 5586200700 ps
CPU time 85.85 seconds
Started May 21 03:18:50 PM PDT 24
Finished May 21 03:20:18 PM PDT 24
Peak memory 260980 kb
Host smart-d193021f-0027-4d05-841e-dbdd6b308a7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897995072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.2897995072
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1062722446
Short name T543
Test name
Test status
Simulation time 63985668500 ps
CPU time 267.22 seconds
Started May 21 03:19:16 PM PDT 24
Finished May 21 03:23:45 PM PDT 24
Peak memory 260368 kb
Host smart-ca505d6a-0aa4-4b05-8d3a-0aa0b9d30561
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106
2722446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1062722446
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2575064585
Short name T336
Test name
Test status
Simulation time 11551745900 ps
CPU time 76.36 seconds
Started May 21 03:18:44 PM PDT 24
Finished May 21 03:20:03 PM PDT 24
Peak memory 259908 kb
Host smart-687270fc-bba0-44f0-9282-aca8ffa63a1a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575064585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2575064585
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3199467757
Short name T665
Test name
Test status
Simulation time 15174700 ps
CPU time 13.54 seconds
Started May 21 03:18:56 PM PDT 24
Finished May 21 03:19:13 PM PDT 24
Peak memory 265160 kb
Host smart-0d26fe4b-8fc2-4301-a8e8-f17f6f6b0910
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199467757 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3199467757
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3884194053
Short name T104
Test name
Test status
Simulation time 191138154000 ps
CPU time 343.08 seconds
Started May 21 03:18:39 PM PDT 24
Finished May 21 03:24:27 PM PDT 24
Peak memory 273248 kb
Host smart-0b4a17f2-10a9-4424-85ac-277d88b9371a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884194053 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.3884194053
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.702581081
Short name T139
Test name
Test status
Simulation time 220725100 ps
CPU time 131.36 seconds
Started May 21 03:18:50 PM PDT 24
Finished May 21 03:21:03 PM PDT 24
Peak memory 259840 kb
Host smart-62aea312-7aad-462a-816b-c28c3fcbfcd5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702581081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.702581081
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.4208189053
Short name T942
Test name
Test status
Simulation time 2712468000 ps
CPU time 179.97 seconds
Started May 21 03:18:32 PM PDT 24
Finished May 21 03:21:35 PM PDT 24
Peak memory 261792 kb
Host smart-816841ce-02b6-43d8-ab5c-24a8caaf6c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208189053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.4208189053
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3667435889
Short name T865
Test name
Test status
Simulation time 4456818500 ps
CPU time 169.69 seconds
Started May 21 03:18:54 PM PDT 24
Finished May 21 03:21:47 PM PDT 24
Peak memory 264620 kb
Host smart-9d16e8a3-2563-4c96-9294-15ab27d68156
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667435889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3667435889
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.217725557
Short name T829
Test name
Test status
Simulation time 403883400 ps
CPU time 448.95 seconds
Started May 21 03:18:34 PM PDT 24
Finished May 21 03:26:06 PM PDT 24
Peak memory 282536 kb
Host smart-feaa17e8-c384-4994-b7fb-41aff69e979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217725557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.217725557
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2441081345
Short name T692
Test name
Test status
Simulation time 336412200 ps
CPU time 37.68 seconds
Started May 21 03:19:03 PM PDT 24
Finished May 21 03:19:42 PM PDT 24
Peak memory 273556 kb
Host smart-bbbed927-8c3a-4df6-864f-c6da5c913858
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441081345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2441081345
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.2588398571
Short name T1022
Test name
Test status
Simulation time 2172783300 ps
CPU time 118.02 seconds
Started May 21 03:18:54 PM PDT 24
Finished May 21 03:20:54 PM PDT 24
Peak memory 296924 kb
Host smart-76cb715e-68d0-4503-bdfd-912cfb0cf8d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588398571 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.2588398571
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.281643589
Short name T253
Test name
Test status
Simulation time 1141627500 ps
CPU time 147.99 seconds
Started May 21 03:18:45 PM PDT 24
Finished May 21 03:21:16 PM PDT 24
Peak memory 281764 kb
Host smart-00df695e-70e7-4b5f-a540-6c798c4ae14c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
281643589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.281643589
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.531341471
Short name T625
Test name
Test status
Simulation time 2251262700 ps
CPU time 139.21 seconds
Started May 21 03:18:44 PM PDT 24
Finished May 21 03:21:07 PM PDT 24
Peak memory 281764 kb
Host smart-719122ad-8701-46ca-853d-db704beddb34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531341471 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.531341471
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.3661618859
Short name T209
Test name
Test status
Simulation time 7716706000 ps
CPU time 702.31 seconds
Started May 21 03:18:46 PM PDT 24
Finished May 21 03:30:31 PM PDT 24
Peak memory 309556 kb
Host smart-47dff928-7137-49b5-a374-6e93a8c244ec
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661618859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.3661618859
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.147126649
Short name T1071
Test name
Test status
Simulation time 63378600 ps
CPU time 28.42 seconds
Started May 21 03:18:57 PM PDT 24
Finished May 21 03:19:28 PM PDT 24
Peak memory 273576 kb
Host smart-5d0211cf-5399-4996-aaeb-384689fe84b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147126649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.147126649
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.4139762720
Short name T26
Test name
Test status
Simulation time 43854500 ps
CPU time 32.2 seconds
Started May 21 03:19:01 PM PDT 24
Finished May 21 03:19:35 PM PDT 24
Peak memory 274876 kb
Host smart-f1014a95-3583-4419-9dc9-03bb9a1bfcf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139762720 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.4139762720
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.4066733377
Short name T1076
Test name
Test status
Simulation time 1736126100 ps
CPU time 65.03 seconds
Started May 21 03:18:54 PM PDT 24
Finished May 21 03:20:00 PM PDT 24
Peak memory 262684 kb
Host smart-01f49d2f-2e82-4be6-ba2f-44e93563a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066733377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.4066733377
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.2473877172
Short name T996
Test name
Test status
Simulation time 22944400 ps
CPU time 117.85 seconds
Started May 21 03:18:44 PM PDT 24
Finished May 21 03:20:45 PM PDT 24
Peak memory 277216 kb
Host smart-c1ce5dcc-3def-4f9a-9626-e55061e573df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473877172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2473877172
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.72188288
Short name T761
Test name
Test status
Simulation time 13737511800 ps
CPU time 232.16 seconds
Started May 21 03:18:45 PM PDT 24
Finished May 21 03:22:40 PM PDT 24
Peak memory 259504 kb
Host smart-be9c1413-57f6-423e-b7f6-ef8f98a80cbe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72188288 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_wo.72188288
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1039533002
Short name T416
Test name
Test status
Simulation time 43992200 ps
CPU time 13.21 seconds
Started May 21 03:26:56 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 275672 kb
Host smart-8c3607f8-c243-45ee-8856-2fbce77ed1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039533002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1039533002
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.328943708
Short name T779
Test name
Test status
Simulation time 151961500 ps
CPU time 131.37 seconds
Started May 21 03:26:56 PM PDT 24
Finished May 21 03:29:09 PM PDT 24
Peak memory 259656 kb
Host smart-e3af9446-7449-49ec-aa8f-894712f59ab7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328943708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot
p_reset.328943708
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2310220794
Short name T784
Test name
Test status
Simulation time 158737600 ps
CPU time 15.65 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:27:10 PM PDT 24
Peak memory 275212 kb
Host smart-e63c6253-0f15-4c95-9787-8d408e60f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310220794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2310220794
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.2761348914
Short name T135
Test name
Test status
Simulation time 38883200 ps
CPU time 110.09 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:28:46 PM PDT 24
Peak memory 261100 kb
Host smart-f11be49b-b8e8-47cf-9b5e-9890d5eae120
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761348914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.2761348914
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2674830760
Short name T732
Test name
Test status
Simulation time 37302500 ps
CPU time 16.17 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:27:13 PM PDT 24
Peak memory 274936 kb
Host smart-0b270458-a397-44fd-be2d-91554a5efb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674830760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2674830760
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2407267892
Short name T730
Test name
Test status
Simulation time 147483500 ps
CPU time 130.84 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:29:08 PM PDT 24
Peak memory 259932 kb
Host smart-59626359-5f3b-4e72-b126-c872c9821029
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407267892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2407267892
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3721076735
Short name T228
Test name
Test status
Simulation time 159052800 ps
CPU time 13.29 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 275048 kb
Host smart-4a690965-df41-4488-b7b6-c0e8148ef854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721076735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3721076735
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3882998614
Short name T531
Test name
Test status
Simulation time 328231900 ps
CPU time 131.59 seconds
Started May 21 03:26:55 PM PDT 24
Finished May 21 03:29:08 PM PDT 24
Peak memory 259948 kb
Host smart-10ce45b4-9066-42ac-89a4-300727eab11a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882998614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3882998614
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.4222032725
Short name T200
Test name
Test status
Simulation time 13367100 ps
CPU time 15.73 seconds
Started May 21 03:26:57 PM PDT 24
Finished May 21 03:27:14 PM PDT 24
Peak memory 275752 kb
Host smart-c477c635-469a-4f6a-a332-c9bcfa8ec90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222032725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.4222032725
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2718223163
Short name T553
Test name
Test status
Simulation time 41338600 ps
CPU time 131.46 seconds
Started May 21 03:26:54 PM PDT 24
Finished May 21 03:29:07 PM PDT 24
Peak memory 260060 kb
Host smart-e67c4c39-b1d4-492f-b961-fe2848626e42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718223163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2718223163
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.910057897
Short name T726
Test name
Test status
Simulation time 23437600 ps
CPU time 15.49 seconds
Started May 21 03:26:59 PM PDT 24
Finished May 21 03:27:16 PM PDT 24
Peak memory 275808 kb
Host smart-75d2e113-3e6d-4be6-8526-0f2909f73033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910057897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.910057897
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.984718252
Short name T803
Test name
Test status
Simulation time 40353700 ps
CPU time 110.76 seconds
Started May 21 03:27:00 PM PDT 24
Finished May 21 03:28:51 PM PDT 24
Peak memory 259968 kb
Host smart-251a2359-62a6-4e4f-862e-e60e85a49012
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984718252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.984718252
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.128135652
Short name T569
Test name
Test status
Simulation time 44022900 ps
CPU time 15.71 seconds
Started May 21 03:27:01 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 275124 kb
Host smart-6d309ea6-155c-4c03-b20a-78ca548a1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128135652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.128135652
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.2093864962
Short name T1035
Test name
Test status
Simulation time 207036600 ps
CPU time 130.93 seconds
Started May 21 03:27:02 PM PDT 24
Finished May 21 03:29:14 PM PDT 24
Peak memory 264532 kb
Host smart-c072bf75-90d4-4a77-b28c-5fe7a6ca2f65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093864962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.2093864962
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3094009585
Short name T997
Test name
Test status
Simulation time 13401600 ps
CPU time 15.78 seconds
Started May 21 03:27:02 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 275136 kb
Host smart-d0adfa7f-fd68-4de6-91a8-a48908f6cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094009585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3094009585
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.458106643
Short name T150
Test name
Test status
Simulation time 136783900 ps
CPU time 132.2 seconds
Started May 21 03:27:02 PM PDT 24
Finished May 21 03:29:15 PM PDT 24
Peak memory 260008 kb
Host smart-818e1245-a4ac-4274-a92f-2d3330178bff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458106643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_ot
p_reset.458106643
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3962499514
Short name T424
Test name
Test status
Simulation time 13485900 ps
CPU time 15.47 seconds
Started May 21 03:26:59 PM PDT 24
Finished May 21 03:27:16 PM PDT 24
Peak memory 275684 kb
Host smart-3c87cb89-e259-4922-a509-eae33ada8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962499514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3962499514
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.3135777279
Short name T426
Test name
Test status
Simulation time 38942800 ps
CPU time 112.2 seconds
Started May 21 03:27:00 PM PDT 24
Finished May 21 03:28:53 PM PDT 24
Peak memory 259944 kb
Host smart-3bef5610-7295-4f67-9c53-572c9bb75d2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135777279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.3135777279
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.954682687
Short name T53
Test name
Test status
Simulation time 21389300 ps
CPU time 15.68 seconds
Started May 21 03:27:06 PM PDT 24
Finished May 21 03:27:23 PM PDT 24
Peak memory 276008 kb
Host smart-131cacfc-b3c4-4e4d-8870-6289e3d3a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954682687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.954682687
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.888507855
Short name T477
Test name
Test status
Simulation time 77448200 ps
CPU time 132.02 seconds
Started May 21 03:27:01 PM PDT 24
Finished May 21 03:29:14 PM PDT 24
Peak memory 260100 kb
Host smart-43b2f970-96b7-440f-806d-cd2e36862e86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888507855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.888507855
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3451319023
Short name T448
Test name
Test status
Simulation time 168976000 ps
CPU time 13.84 seconds
Started May 21 03:19:39 PM PDT 24
Finished May 21 03:19:54 PM PDT 24
Peak memory 265132 kb
Host smart-a764d59d-08d0-40db-8df2-f8101e9bbc67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451319023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
451319023
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2748068105
Short name T394
Test name
Test status
Simulation time 16682400 ps
CPU time 15.93 seconds
Started May 21 03:19:30 PM PDT 24
Finished May 21 03:19:47 PM PDT 24
Peak memory 275120 kb
Host smart-ae9258e5-4084-4bd9-806a-57de8f90b31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748068105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2748068105
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.2679451434
Short name T646
Test name
Test status
Simulation time 16744900 ps
CPU time 22.1 seconds
Started May 21 03:19:30 PM PDT 24
Finished May 21 03:19:53 PM PDT 24
Peak memory 265276 kb
Host smart-bd0ff30e-500c-4e27-b3fa-0ff841be315a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679451434 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.2679451434
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2470274663
Short name T75
Test name
Test status
Simulation time 12876972700 ps
CPU time 2698.1 seconds
Started May 21 03:19:07 PM PDT 24
Finished May 21 04:04:07 PM PDT 24
Peak memory 264772 kb
Host smart-5c652f2f-c87c-4e11-8f9e-c8b2abfc3ae0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470274663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.2470274663
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2037586467
Short name T1079
Test name
Test status
Simulation time 848095900 ps
CPU time 841.91 seconds
Started May 21 03:19:20 PM PDT 24
Finished May 21 03:33:22 PM PDT 24
Peak memory 273380 kb
Host smart-bcea9a4d-bec6-4ff3-888b-a9fe1f4b2ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037586467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2037586467
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2322765089
Short name T45
Test name
Test status
Simulation time 649124900 ps
CPU time 23.96 seconds
Started May 21 03:19:29 PM PDT 24
Finished May 21 03:19:55 PM PDT 24
Peak memory 265176 kb
Host smart-c0160e2b-a27e-43a7-943e-b21761cb1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322765089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2322765089
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3736007219
Short name T551
Test name
Test status
Simulation time 10031463100 ps
CPU time 53.97 seconds
Started May 21 03:19:29 PM PDT 24
Finished May 21 03:20:24 PM PDT 24
Peak memory 271812 kb
Host smart-0aee482f-15bc-4019-a769-773f9a12ba1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736007219 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3736007219
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1500270364
Short name T684
Test name
Test status
Simulation time 26333200 ps
CPU time 14.19 seconds
Started May 21 03:19:28 PM PDT 24
Finished May 21 03:19:42 PM PDT 24
Peak memory 265300 kb
Host smart-7ec52e43-9a4f-46fb-82fe-504663440ad1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500270364 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1500270364
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2792860384
Short name T689
Test name
Test status
Simulation time 1090906900 ps
CPU time 97.54 seconds
Started May 21 03:19:16 PM PDT 24
Finished May 21 03:20:54 PM PDT 24
Peak memory 262576 kb
Host smart-c2523bb4-17e4-4999-9b1a-a59e95164053
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792860384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2792860384
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2955053033
Short name T990
Test name
Test status
Simulation time 1216844800 ps
CPU time 115.67 seconds
Started May 21 03:19:17 PM PDT 24
Finished May 21 03:21:14 PM PDT 24
Peak memory 289904 kb
Host smart-3192eaa9-0017-40cb-84b7-ec192265f50b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955053033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2955053033
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1267531793
Short name T52
Test name
Test status
Simulation time 22821337800 ps
CPU time 138.32 seconds
Started May 21 03:19:25 PM PDT 24
Finished May 21 03:21:44 PM PDT 24
Peak memory 292316 kb
Host smart-87c14b99-47de-4f87-9110-1e1795c8d996
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267531793 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1267531793
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.492867316
Short name T721
Test name
Test status
Simulation time 5585011600 ps
CPU time 75.78 seconds
Started May 21 03:19:34 PM PDT 24
Finished May 21 03:20:51 PM PDT 24
Peak memory 260008 kb
Host smart-42eadc8f-f6b0-48d5-a842-248c47dd9d06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492867316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.492867316
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1016373104
Short name T682
Test name
Test status
Simulation time 78437748100 ps
CPU time 197.96 seconds
Started May 21 03:19:27 PM PDT 24
Finished May 21 03:22:46 PM PDT 24
Peak memory 260332 kb
Host smart-1f1db215-f72e-4468-81bf-159786e60465
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101
6373104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1016373104
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3929859871
Short name T4
Test name
Test status
Simulation time 3190025300 ps
CPU time 68.93 seconds
Started May 21 03:19:08 PM PDT 24
Finished May 21 03:20:19 PM PDT 24
Peak memory 259740 kb
Host smart-f76ec564-abac-4a59-9648-94812d527f74
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929859871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3929859871
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.3540016808
Short name T131
Test name
Test status
Simulation time 22663700 ps
CPU time 13.75 seconds
Started May 21 03:19:29 PM PDT 24
Finished May 21 03:19:44 PM PDT 24
Peak memory 265188 kb
Host smart-8108ae20-09e3-4c7d-a749-78fc933d0c7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540016808 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.3540016808
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3298800403
Short name T79
Test name
Test status
Simulation time 10122715700 ps
CPU time 293.94 seconds
Started May 21 03:19:08 PM PDT 24
Finished May 21 03:24:04 PM PDT 24
Peak memory 274348 kb
Host smart-80fdb6e2-3a8d-4ce9-88ba-0ea30642a7ce
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298800403 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3298800403
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.1945243806
Short name T890
Test name
Test status
Simulation time 67359400 ps
CPU time 128.22 seconds
Started May 21 03:19:08 PM PDT 24
Finished May 21 03:21:18 PM PDT 24
Peak memory 260992 kb
Host smart-ff328238-35c9-41cb-962b-5e41200e7608
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945243806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.1945243806
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.794733097
Short name T902
Test name
Test status
Simulation time 237278300 ps
CPU time 319.73 seconds
Started May 21 03:19:02 PM PDT 24
Finished May 21 03:24:23 PM PDT 24
Peak memory 262624 kb
Host smart-07ec84cd-5a2c-4ed5-9d55-5cd9099a55ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794733097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.794733097
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.2931288626
Short name T1088
Test name
Test status
Simulation time 56357500 ps
CPU time 13.48 seconds
Started May 21 03:19:30 PM PDT 24
Finished May 21 03:19:44 PM PDT 24
Peak memory 265188 kb
Host smart-0f3ee0bb-2be4-49e6-b4a9-6bdaa6e865cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931288626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.2931288626
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.1784564825
Short name T425
Test name
Test status
Simulation time 80857600 ps
CPU time 327.94 seconds
Started May 21 03:19:29 PM PDT 24
Finished May 21 03:24:58 PM PDT 24
Peak memory 281336 kb
Host smart-50b49fe9-b394-46df-aec5-923525911070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784564825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1784564825
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.3137381988
Short name T1060
Test name
Test status
Simulation time 544379000 ps
CPU time 36.85 seconds
Started May 21 03:19:30 PM PDT 24
Finished May 21 03:20:08 PM PDT 24
Peak memory 273620 kb
Host smart-ef5c6497-6b07-4954-a33f-779947782e23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137381988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.3137381988
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.496901915
Short name T217
Test name
Test status
Simulation time 911686200 ps
CPU time 143.3 seconds
Started May 21 03:19:08 PM PDT 24
Finished May 21 03:21:34 PM PDT 24
Peak memory 280928 kb
Host smart-a404b9fb-968e-44b6-88d0-e0f640acf9ed
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496901915 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.496901915
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.16284443
Short name T205
Test name
Test status
Simulation time 1055702000 ps
CPU time 141.22 seconds
Started May 21 03:19:12 PM PDT 24
Finished May 21 03:21:34 PM PDT 24
Peak memory 281724 kb
Host smart-74214c6a-5db2-47c4-86fa-7a1a56b6f7d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
16284443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.16284443
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2280154459
Short name T759
Test name
Test status
Simulation time 737154700 ps
CPU time 158.63 seconds
Started May 21 03:19:16 PM PDT 24
Finished May 21 03:21:55 PM PDT 24
Peak memory 294456 kb
Host smart-5b5881d2-0f5f-41ee-a696-140edcf28839
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280154459 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2280154459
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.3714228026
Short name T1101
Test name
Test status
Simulation time 5235324500 ps
CPU time 534.61 seconds
Started May 21 03:19:26 PM PDT 24
Finished May 21 03:28:21 PM PDT 24
Peak memory 309540 kb
Host smart-866320a0-9029-427d-8743-23eacd3ae472
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714228026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.3714228026
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.3111255167
Short name T1066
Test name
Test status
Simulation time 9110762300 ps
CPU time 861.61 seconds
Started May 21 03:19:12 PM PDT 24
Finished May 21 03:33:34 PM PDT 24
Peak memory 342700 kb
Host smart-06f1c7e4-2be0-46aa-8cd9-b9c3f33e776d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111255167 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.3111255167
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.2129123227
Short name T204
Test name
Test status
Simulation time 41403600 ps
CPU time 31.31 seconds
Started May 21 03:19:29 PM PDT 24
Finished May 21 03:20:01 PM PDT 24
Peak memory 273548 kb
Host smart-a980665a-53ba-46d0-902e-3fb11fcb7c37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129123227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.2129123227
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.1800192108
Short name T1048
Test name
Test status
Simulation time 16050657300 ps
CPU time 553.24 seconds
Started May 21 03:19:12 PM PDT 24
Finished May 21 03:28:26 PM PDT 24
Peak memory 320060 kb
Host smart-48c621b8-6598-4f7b-83b5-68505de82906
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800192108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.1800192108
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.275867579
Short name T30
Test name
Test status
Simulation time 1330746400 ps
CPU time 68.39 seconds
Started May 21 03:19:31 PM PDT 24
Finished May 21 03:20:40 PM PDT 24
Peak memory 262892 kb
Host smart-3d5110f2-4503-4b71-9aae-da0361a753ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275867579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.275867579
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.336676453
Short name T821
Test name
Test status
Simulation time 86480900 ps
CPU time 99.58 seconds
Started May 21 03:18:58 PM PDT 24
Finished May 21 03:20:41 PM PDT 24
Peak memory 275460 kb
Host smart-a6f660fb-1fdb-4ffe-b1ff-4442e4d481d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336676453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.336676453
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.861634065
Short name T505
Test name
Test status
Simulation time 12646629400 ps
CPU time 209.88 seconds
Started May 21 03:19:08 PM PDT 24
Finished May 21 03:22:40 PM PDT 24
Peak memory 265204 kb
Host smart-e9ea8cec-2b12-4ec2-86eb-43bc54602b32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861634065 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_wo.861634065
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.3608679808
Short name T651
Test name
Test status
Simulation time 285452800 ps
CPU time 13.48 seconds
Started May 21 03:20:14 PM PDT 24
Finished May 21 03:20:28 PM PDT 24
Peak memory 265200 kb
Host smart-83701abb-4d47-4985-b5b4-3304c75c85ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608679808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3
608679808
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.3266648556
Short name T583
Test name
Test status
Simulation time 67124000 ps
CPU time 15.68 seconds
Started May 21 03:20:21 PM PDT 24
Finished May 21 03:20:37 PM PDT 24
Peak memory 275696 kb
Host smart-6a2c7a21-4d6f-489a-914e-553aabf77fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266648556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3266648556
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.4291569831
Short name T42
Test name
Test status
Simulation time 13059400 ps
CPU time 21.34 seconds
Started May 21 03:20:11 PM PDT 24
Finished May 21 03:20:33 PM PDT 24
Peak memory 273572 kb
Host smart-856ef092-5d39-4e17-88a8-0fbbca0942ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291569831 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.4291569831
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.977174833
Short name T642
Test name
Test status
Simulation time 46357494700 ps
CPU time 2356.23 seconds
Started May 21 03:19:43 PM PDT 24
Finished May 21 03:59:00 PM PDT 24
Peak memory 264820 kb
Host smart-956ef3b9-cdc7-4312-ad2b-be3774a88dc1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977174833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_erro
r_mp.977174833
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3658753428
Short name T1102
Test name
Test status
Simulation time 7174093700 ps
CPU time 903.77 seconds
Started May 21 03:19:48 PM PDT 24
Finished May 21 03:34:53 PM PDT 24
Peak memory 273352 kb
Host smart-826e9c68-c357-4f89-844c-eb10bcf6624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658753428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3658753428
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3774949498
Short name T479
Test name
Test status
Simulation time 600253600 ps
CPU time 27.58 seconds
Started May 21 03:19:48 PM PDT 24
Finished May 21 03:20:18 PM PDT 24
Peak memory 265196 kb
Host smart-a2f0c53c-17fd-46e0-9f62-1174d600dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774949498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3774949498
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.429150392
Short name T285
Test name
Test status
Simulation time 10070871600 ps
CPU time 49.4 seconds
Started May 21 03:20:21 PM PDT 24
Finished May 21 03:21:12 PM PDT 24
Peak memory 265436 kb
Host smart-09f3b9eb-8551-4249-aa2f-cb84f1706e96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429150392 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.429150392
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1584671371
Short name T215
Test name
Test status
Simulation time 16675000 ps
CPU time 13.49 seconds
Started May 21 03:20:13 PM PDT 24
Finished May 21 03:20:27 PM PDT 24
Peak memory 265184 kb
Host smart-b5b7bb7f-53ae-4de8-8aa1-b49ec0d520e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584671371 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1584671371
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3438043313
Short name T615
Test name
Test status
Simulation time 40122642800 ps
CPU time 837.07 seconds
Started May 21 03:19:39 PM PDT 24
Finished May 21 03:33:37 PM PDT 24
Peak memory 263956 kb
Host smart-58d34b8a-b2b6-4d61-91ee-c58c4a8266d6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438043313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.3438043313
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1387530880
Short name T503
Test name
Test status
Simulation time 1470158500 ps
CPU time 72.5 seconds
Started May 21 03:19:42 PM PDT 24
Finished May 21 03:20:56 PM PDT 24
Peak memory 262624 kb
Host smart-72fe3e49-d1a1-4ad8-b37f-ead221ebbd9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387530880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1387530880
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3686698766
Short name T653
Test name
Test status
Simulation time 546600400 ps
CPU time 189.35 seconds
Started May 21 03:19:51 PM PDT 24
Finished May 21 03:23:01 PM PDT 24
Peak memory 293468 kb
Host smart-5c719c2a-c765-4822-98f3-2f49b896544a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686698766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3686698766
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3635703775
Short name T338
Test name
Test status
Simulation time 97501207800 ps
CPU time 401.96 seconds
Started May 21 03:19:55 PM PDT 24
Finished May 21 03:26:39 PM PDT 24
Peak memory 291216 kb
Host smart-f3e336f7-1486-4656-9326-a6cec2fea02c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635703775 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3635703775
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2019176744
Short name T378
Test name
Test status
Simulation time 9680035300 ps
CPU time 73.46 seconds
Started May 21 03:19:52 PM PDT 24
Finished May 21 03:21:06 PM PDT 24
Peak memory 265268 kb
Host smart-e97e7554-5017-4afc-b540-279ccbd30b15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019176744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2019176744
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1634771705
Short name T919
Test name
Test status
Simulation time 22882457100 ps
CPU time 189.6 seconds
Started May 21 03:19:55 PM PDT 24
Finished May 21 03:23:06 PM PDT 24
Peak memory 265176 kb
Host smart-29722802-8297-42ef-bb73-3ac932ef2b90
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163
4771705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1634771705
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2573081820
Short name T96
Test name
Test status
Simulation time 2005846300 ps
CPU time 79.15 seconds
Started May 21 03:19:44 PM PDT 24
Finished May 21 03:21:04 PM PDT 24
Peak memory 260852 kb
Host smart-a044d539-ea7a-45aa-a6b1-0c50ddffa5f9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573081820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2573081820
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.3491787272
Short name T530
Test name
Test status
Simulation time 42459400 ps
CPU time 13.23 seconds
Started May 21 03:20:21 PM PDT 24
Finished May 21 03:20:36 PM PDT 24
Peak memory 265180 kb
Host smart-552c9968-9c4f-407a-b8ec-b4112c986282
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491787272 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.3491787272
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.728905481
Short name T558
Test name
Test status
Simulation time 4374775500 ps
CPU time 174.14 seconds
Started May 21 03:19:40 PM PDT 24
Finished May 21 03:22:36 PM PDT 24
Peak memory 262852 kb
Host smart-622cfee6-38d1-43da-b66f-1f9757902681
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728905481 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_mp_regions.728905481
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.2864606151
Short name T1039
Test name
Test status
Simulation time 146961900 ps
CPU time 130.95 seconds
Started May 21 03:19:39 PM PDT 24
Finished May 21 03:21:50 PM PDT 24
Peak memory 259900 kb
Host smart-6be9f8da-9698-405b-aff5-1e04c668d3f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864606151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.2864606151
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.4091168948
Short name T225
Test name
Test status
Simulation time 1459180400 ps
CPU time 342.45 seconds
Started May 21 03:19:41 PM PDT 24
Finished May 21 03:25:25 PM PDT 24
Peak memory 262444 kb
Host smart-645acaf6-249e-467e-adb3-420ebb6fff8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091168948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.4091168948
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1627823697
Short name T513
Test name
Test status
Simulation time 19255700 ps
CPU time 13.37 seconds
Started May 21 03:20:00 PM PDT 24
Finished May 21 03:20:15 PM PDT 24
Peak memory 258712 kb
Host smart-b504d346-dac3-4cca-9b62-6c7df5de6444
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627823697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1627823697
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2945610899
Short name T453
Test name
Test status
Simulation time 394897700 ps
CPU time 887.36 seconds
Started May 21 03:19:34 PM PDT 24
Finished May 21 03:34:22 PM PDT 24
Peak memory 283396 kb
Host smart-d98153c9-76c0-473c-bb0d-38f692de803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945610899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2945610899
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.2649916536
Short name T650
Test name
Test status
Simulation time 1149949900 ps
CPU time 125.51 seconds
Started May 21 03:19:50 PM PDT 24
Finished May 21 03:21:57 PM PDT 24
Peak memory 297160 kb
Host smart-f0036cff-e047-4fe5-bf26-bda2eecec91f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649916536 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.2649916536
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.975174431
Short name T905
Test name
Test status
Simulation time 528842000 ps
CPU time 144.85 seconds
Started May 21 03:19:49 PM PDT 24
Finished May 21 03:22:16 PM PDT 24
Peak memory 281716 kb
Host smart-06e5563c-e69a-4799-946e-a29535d7e400
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975174431 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.975174431
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.298216331
Short name T459
Test name
Test status
Simulation time 4108344300 ps
CPU time 584.45 seconds
Started May 21 03:19:50 PM PDT 24
Finished May 21 03:29:36 PM PDT 24
Peak memory 318624 kb
Host smart-ed7ed864-661d-45e5-944e-aa7d7bb2397b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298216331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_rw.298216331
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.2397248158
Short name T671
Test name
Test status
Simulation time 16184485400 ps
CPU time 729.24 seconds
Started May 21 03:19:48 PM PDT 24
Finished May 21 03:31:59 PM PDT 24
Peak memory 339400 kb
Host smart-c88f9e8c-5865-44ce-8f76-5aa67db425ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397248158 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.2397248158
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.1723893589
Short name T789
Test name
Test status
Simulation time 45886000 ps
CPU time 32.2 seconds
Started May 21 03:20:00 PM PDT 24
Finished May 21 03:20:34 PM PDT 24
Peak memory 267420 kb
Host smart-b79644df-cdea-40f5-a4a1-33f964000105
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723893589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.1723893589
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.769454629
Short name T334
Test name
Test status
Simulation time 135866300 ps
CPU time 31.16 seconds
Started May 21 03:20:00 PM PDT 24
Finished May 21 03:20:33 PM PDT 24
Peak memory 274908 kb
Host smart-e998faf5-7a6a-418d-858e-0d1a542ced8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769454629 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.769454629
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2214755891
Short name T374
Test name
Test status
Simulation time 971200200 ps
CPU time 61.37 seconds
Started May 21 03:20:10 PM PDT 24
Finished May 21 03:21:12 PM PDT 24
Peak memory 262980 kb
Host smart-fd5fc283-67c8-4dc1-b973-de5f2260adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214755891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2214755891
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2540108851
Short name T1013
Test name
Test status
Simulation time 37984900 ps
CPU time 169.14 seconds
Started May 21 03:19:45 PM PDT 24
Finished May 21 03:22:35 PM PDT 24
Peak memory 276592 kb
Host smart-e4562346-1811-4732-af06-adfd8231e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540108851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2540108851
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2101660092
Short name T835
Test name
Test status
Simulation time 2134730900 ps
CPU time 192.63 seconds
Started May 21 03:19:44 PM PDT 24
Finished May 21 03:22:57 PM PDT 24
Peak memory 265228 kb
Host smart-1d5bb77f-ba78-41fd-8e62-2f4dd10ad9a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101660092 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2101660092
Directory /workspace/9.flash_ctrl_wo/latest
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