Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	321404	1		T1	2		T2	2		T3	2
all_values[1]	321404	1		T1	2		T2	2		T3	2
all_values[2]	321404	1		T1	2		T2	2		T3	2
all_values[3]	321404	1		T1	2		T2	2		T3	2
all_values[4]	321404	1		T1	2		T2	2		T3	2
all_values[5]	321404	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	649063	1		T1	12		T2	12		T3	12
auto[1]	1279361	1		T24	4568		T34	26024		T27	6360

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	937831	1		T1	7		T2	6		T3	7
auto[1]	990593	1		T1	5		T2	6		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	321237	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	167	1		T243	1		T244	5		T339	3
all_values[1]	auto[0]	auto[1]	321237	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	167	1		T242	5		T243	1		T244	1
all_values[2]	auto[0]	auto[0]	1581	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	67	1		T242	1		T243	2		T338	1
all_values[2]	auto[1]	auto[0]	319701	1		T24	1142		T34	6506		T27	1590
all_values[2]	auto[1]	auto[1]	55	1		T242	1		T244	1		T339	1
all_values[3]	auto[0]	auto[0]	1586	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	54	1		T243	1		T244	2		T339	1
all_values[3]	auto[1]	auto[0]	77174	1		T24	571		T34	1577		T27	1590
all_values[3]	auto[1]	auto[1]	242590	1		T24	571		T34	4929		T35	1548
all_values[4]	auto[0]	auto[0]	1128	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	522	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	215469	1		T24	571		T34	4863		T27	1
all_values[4]	auto[1]	auto[1]	104285	1		T24	571		T34	1643		T27	1589
all_values[5]	auto[0]	auto[0]	1506	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	145	1		T2	1		T36	1		T38	1
all_values[5]	auto[1]	auto[0]	319686	1		T24	1142		T34	6506		T27	1590
all_values[5]	auto[1]	auto[1]	67	1		T242	1		T243	2		T339	1