Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00
Crosses 16 0 16 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
erase_cp 2 0 2 100.00 100 1 1 0
op_cp 4 0 4 100.00 100 1 1 0
op_evict_cp 5 0 5 100.00 100 1 1 0
part_cp 4 0 4 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
op_part_cross 16 0 16 100.00 100 1 1 0


Summary for Variable erase_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for erase_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashErasePage] 248276 1 T1 1284 T2 406 T3 340
auto[FlashEraseBank] 275046 1 T1 1964 T2 605 T17 7



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashOpRead] 258369 1 T1 1352 T2 1011 T3 14
auto[FlashOpProgram] 244058 1 T1 1896 T3 320 T17 2
auto[FlashOpErase] 16895 1 T3 6 T19 100 T5 100
auto[FlashOpInvalid] 4000 1 T5 200 T104 200 T93 200



Summary for Variable op_evict_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for op_evict_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
op[FlashOpRead] 258369 1 T1 1352 T2 1011 T3 14
op[FlashOpProgram] 244058 1 T1 1896 T3 320 T17 2
op[FlashOpErase] 16895 1 T3 6 T19 100 T5 100
read_erase_read 671 1 T58 6 T30 4 T26 12
read_prog_read 790 1 T1 7 T4 1 T58 15



Summary for Variable part_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for part_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] 380336 1 T1 2783 T2 731 T4 18
auto[FlashPartInfo] 139891 1 T1 451 T2 264 T3 340
auto[FlashPartInfo1] 745 1 T1 5 T2 5 T72 1
auto[FlashPartInfo2] 2350 1 T1 9 T2 11 T27 3



Summary for Cross op_part_cross

Samples crossed: part_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for op_part_cross

Bins
part_cpop_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] auto[FlashOpRead] 187997 1 T1 1055 T2 731 T4 10
auto[FlashPartData] auto[FlashOpProgram] 184596 1 T1 1728 T4 8 T20 1
auto[FlashPartData] auto[FlashOpErase] 3849 1 T5 100 T58 27 T44 30
auto[FlashPartData] auto[FlashOpInvalid] 3894 1 T5 200 T104 190 T93 198
auto[FlashPartInfo] auto[FlashOpRead] 68392 1 T1 283 T2 264 T3 14
auto[FlashPartInfo] auto[FlashOpProgram] 58388 1 T1 168 T3 320 T17 2
auto[FlashPartInfo] auto[FlashOpErase] 13019 1 T3 6 T19 100 T30 8
auto[FlashPartInfo] auto[FlashOpInvalid] 92 1 T104 10 T110 8 T410 8
auto[FlashPartInfo1] auto[FlashOpRead] 579 1 T1 5 T2 5 T36 5
auto[FlashPartInfo1] auto[FlashOpProgram] 161 1 T77 32 T112 32 T115 32
auto[FlashPartInfo1] auto[FlashOpErase] 3 1 T72 1 T380 1 T411 1
auto[FlashPartInfo1] auto[FlashOpInvalid] 2 1 T411 2 - - - -
auto[FlashPartInfo2] auto[FlashOpRead] 1401 1 T1 9 T2 11 T25 1
auto[FlashPartInfo2] auto[FlashOpProgram] 913 1 T27 3 T235 5 T75 5
auto[FlashPartInfo2] auto[FlashOpErase] 24 1 T93 1 T108 1 T125 1
auto[FlashPartInfo2] auto[FlashOpInvalid] 12 1 T93 2 T412 2 T413 2

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