Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	10	22	68.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	10	22	68.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32351	1		T19	212		T5	400		T58	16
auto[1]	16	1		T25	1		T56	1		T38	1
auto[2]	31	1		T44	8		T167	8		T172	4
auto[3]	65	1		T17	1		T20	1		T39	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8120	1		T19	53		T20	1		T5	100
evic_idx[1]	8118	1		T19	53		T5	100		T58	4
evic_idx[2]	8113	1		T17	1		T19	53		T5	100
evic_idx[3]	8112	1		T19	53		T5	100		T58	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31648	1		T19	212		T5	400		T48	516
evic_op[2]	290	1		T17	1		T20	1		T31	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	10	22	68.75	10

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4
[evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7906	1		T19	53		T5	100		T48	129
evic_idx[0]	evic_op[1]	auto[3]	5	1		T327	4		T328	1		-	-
evic_idx[0]	evic_op[2]	auto[0]	58	1		T31	1		T106	1		T108	1
evic_idx[0]	evic_op[2]	auto[1]	7	1		T38	1		T258	1		T208	1
evic_idx[0]	evic_op[2]	auto[3]	12	1		T20	1		T39	1		T216	1
evic_idx[1]	evic_op[1]	auto[0]	7907	1		T19	53		T5	100		T48	129
evic_idx[1]	evic_op[1]	auto[3]	7	1		T327	5		T328	2		-	-
evic_idx[1]	evic_op[2]	auto[0]	59	1		T31	1		T106	1		T108	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T329	1		T330	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	2	1		T331	1		T332	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T216	1		T333	1		T334	1
evic_idx[2]	evic_op[1]	auto[0]	7906	1		T19	53		T5	100		T48	129
evic_idx[2]	evic_op[1]	auto[3]	7	1		T327	5		T328	2		-	-
evic_idx[2]	evic_op[2]	auto[0]	56	1		T31	1		T201	1		T106	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T25	1		T56	1		T178	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T331	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T17	1		T216	1		T91	1
evic_idx[3]	evic_op[1]	auto[0]	7904	1		T19	53		T5	100		T48	129
evic_idx[3]	evic_op[1]	auto[3]	6	1		T325	1		T327	3		T328	2
evic_idx[3]	evic_op[2]	auto[0]	58	1		T31	1		T106	1		T108	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T335	1		T336	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T209	1		T211	1		T337	1