Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	25803	1		T269	1306		T347	2790		T348	1439
rd_lvl[2]	24728	1		T269	2488		T347	2326		T348	2374
rd_lvl[3]	8709	1		T62	862		T269	752		T347	1259
rd_lvl[4]	40941	1		T166	735		T62	1429		T269	1789
rd_lvl[5]	21112	1		T34	2142		T166	120		T62	166
rd_lvl[6]	15776	1		T34	1411		T62	403		T225	1179
rd_lvl[7]	9526	1		T34	66		T166	24		T62	430
rd_lvl[8]	17812	1		T166	4		T62	362		T349	52
rd_lvl[9]	11571	1		T224	699		T350	351		T269	1559
rd_lvl[10]	13502	1		T224	972		T62	1		T351	1252
rd_lvl[11]	8382	1		T62	1		T33	253		T351	405
rd_lvl[12]	7233	1		T166	20		T33	128		T350	1
rd_lvl[13]	2595	1		T24	220		T219	22		T267	346
rd_lvl[14]	4706	1		T24	109		T35	1113		T32	1420
rd_lvl[15]	4261	1		T35	435		T32	436		T352	250