Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	321404	1		T1	2		T2	2		T3	2
all_pins[1]	321404	1		T1	2		T2	2		T3	2
all_pins[2]	321404	1		T1	2		T2	2		T3	2
all_pins[3]	321404	1		T1	2		T2	2		T3	2
all_pins[4]	321404	1		T1	2		T2	2		T3	2
all_pins[5]	321404	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1598878	1		T1	12		T2	12		T3	12
values[0x1]	329546	1		T24	1142		T34	5348		T27	1589
transitions[0x0=>0x1]	296201	1		T24	1142		T34	5196		T27	1589
transitions[0x1=>0x0]	296183	1		T24	1142		T34	5196		T27	1589

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	321237	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	167	1		T243	1		T244	5		T339	3
all_pins[0]	transitions[0x0=>0x1]	82	1		T244	4		T339	3		T340	5
all_pins[0]	transitions[0x1=>0x0]	82	1		T242	5		T339	2		T338	3
all_pins[1]	values[0x0]	321237	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	167	1		T242	5		T243	1		T244	1
all_pins[1]	transitions[0x0=>0x1]	141	1		T242	4		T243	1		T244	1
all_pins[1]	transitions[0x1=>0x0]	1720	1		T352	88		T259	1102		T354	255
all_pins[2]	values[0x0]	319658	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	1746	1		T352	88		T259	1102		T354	255
all_pins[2]	transitions[0x0=>0x1]	45	1		T244	1		T339	1		T340	1
all_pins[2]	transitions[0x1=>0x0]	216989	1		T24	571		T34	3619		T35	1548
all_pins[3]	values[0x0]	102714	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	218690	1		T24	571		T34	3619		T35	1548
all_pins[3]	transitions[0x0=>0x1]	187211	1		T24	571		T34	3467		T35	1548
all_pins[3]	transitions[0x1=>0x0]	77230	1		T24	571		T34	1577		T27	1589
all_pins[4]	values[0x0]	212695	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	108709	1		T24	571		T34	1729		T27	1589
all_pins[4]	transitions[0x0=>0x1]	108698	1		T24	571		T34	1729		T27	1589
all_pins[4]	transitions[0x1=>0x0]	56	1		T243	2		T339	1		T344	3
all_pins[5]	values[0x0]	321337	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	67	1		T242	1		T243	2		T339	1
all_pins[5]	transitions[0x0=>0x1]	24	1		T242	1		T243	2		T341	1
all_pins[5]	transitions[0x1=>0x0]	106	1		T243	1		T244	4		T339	2