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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.51 95.75 94.17 98.85 92.52 98.09 98.30 97.90


Total test records in report: 1243
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T1075 /workspace/coverage/default/41.flash_ctrl_otp_reset.717259976 May 23 01:32:20 PM PDT 24 May 23 01:34:14 PM PDT 24 70472100 ps
T1076 /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1598244528 May 23 01:32:08 PM PDT 24 May 23 01:33:41 PM PDT 24 8154835800 ps
T1077 /workspace/coverage/default/3.flash_ctrl_erase_suspend.870861448 May 23 01:28:01 PM PDT 24 May 23 01:33:42 PM PDT 24 2855437900 ps
T1078 /workspace/coverage/default/8.flash_ctrl_ro_serr.235593296 May 23 01:28:39 PM PDT 24 May 23 01:31:07 PM PDT 24 2977282600 ps
T1079 /workspace/coverage/default/11.flash_ctrl_ro.2494324645 May 23 01:29:06 PM PDT 24 May 23 01:30:46 PM PDT 24 1991223700 ps
T1080 /workspace/coverage/default/6.flash_ctrl_error_mp.2933544866 May 23 01:28:15 PM PDT 24 May 23 02:05:46 PM PDT 24 5477241300 ps
T1081 /workspace/coverage/default/48.flash_ctrl_smoke.2154211429 May 23 01:32:36 PM PDT 24 May 23 01:35:07 PM PDT 24 1398484100 ps
T151 /workspace/coverage/default/1.flash_ctrl_rma_err.2444173665 May 23 01:27:56 PM PDT 24 May 23 01:43:01 PM PDT 24 41106546300 ps
T1082 /workspace/coverage/default/29.flash_ctrl_prog_reset.2055193403 May 23 01:31:26 PM PDT 24 May 23 01:31:41 PM PDT 24 84200900 ps
T1083 /workspace/coverage/default/24.flash_ctrl_intr_rd.802476815 May 23 01:31:03 PM PDT 24 May 23 01:33:18 PM PDT 24 682987700 ps
T1084 /workspace/coverage/default/10.flash_ctrl_prog_reset.1737675965 May 23 01:29:08 PM PDT 24 May 23 01:29:24 PM PDT 24 48710400 ps
T1085 /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1464661800 May 23 01:28:22 PM PDT 24 May 23 01:28:55 PM PDT 24 39128500 ps
T1086 /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.692714615 May 23 01:32:11 PM PDT 24 May 23 01:34:43 PM PDT 24 4227506900 ps
T1087 /workspace/coverage/default/24.flash_ctrl_rw_evict.154187439 May 23 01:30:58 PM PDT 24 May 23 01:31:31 PM PDT 24 235071500 ps
T1088 /workspace/coverage/default/13.flash_ctrl_sec_info_access.2258319009 May 23 01:29:40 PM PDT 24 May 23 01:30:42 PM PDT 24 1132702500 ps
T1089 /workspace/coverage/default/13.flash_ctrl_prog_reset.304140259 May 23 01:29:38 PM PDT 24 May 23 01:29:54 PM PDT 24 19707300 ps
T330 /workspace/coverage/default/0.flash_ctrl_fs_sup.3486319282 May 23 01:27:31 PM PDT 24 May 23 01:28:15 PM PDT 24 346277800 ps
T1090 /workspace/coverage/default/33.flash_ctrl_rw_evict.3316556721 May 23 01:31:50 PM PDT 24 May 23 01:32:21 PM PDT 24 39228100 ps
T1091 /workspace/coverage/default/35.flash_ctrl_intr_rd.605122211 May 23 01:31:50 PM PDT 24 May 23 01:34:47 PM PDT 24 1594295200 ps
T336 /workspace/coverage/default/4.flash_ctrl_fs_sup.1450396042 May 23 01:28:03 PM PDT 24 May 23 01:28:49 PM PDT 24 1360330900 ps
T363 /workspace/coverage/default/3.flash_ctrl_config_regwen.670561815 May 23 01:28:00 PM PDT 24 May 23 01:28:16 PM PDT 24 21112000 ps
T191 /workspace/coverage/default/4.flash_ctrl_sec_cm.4070755271 May 23 01:28:07 PM PDT 24 May 23 02:46:51 PM PDT 24 2694931000 ps
T1092 /workspace/coverage/default/62.flash_ctrl_connect.3356246955 May 23 01:32:52 PM PDT 24 May 23 01:33:10 PM PDT 24 21506000 ps
T1093 /workspace/coverage/default/1.flash_ctrl_phy_arb.2875897670 May 23 01:27:30 PM PDT 24 May 23 01:31:27 PM PDT 24 61806000 ps
T1094 /workspace/coverage/default/15.flash_ctrl_alert_test.1661429308 May 23 01:30:09 PM PDT 24 May 23 01:30:24 PM PDT 24 26807600 ps
T1095 /workspace/coverage/default/0.flash_ctrl_connect.908508463 May 23 01:27:29 PM PDT 24 May 23 01:27:47 PM PDT 24 15369000 ps
T128 /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1667483856 May 23 01:27:27 PM PDT 24 May 23 01:27:50 PM PDT 24 755465300 ps
T1096 /workspace/coverage/default/9.flash_ctrl_rw.3788668999 May 23 01:28:54 PM PDT 24 May 23 01:39:32 PM PDT 24 7808764400 ps
T65 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.940313362 May 23 01:19:58 PM PDT 24 May 23 01:27:45 PM PDT 24 981676100 ps
T1097 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3398134083 May 23 01:20:15 PM PDT 24 May 23 01:20:32 PM PDT 24 47072400 ps
T66 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3435030727 May 23 01:20:14 PM PDT 24 May 23 01:20:32 PM PDT 24 37571300 ps
T242 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3754746031 May 23 01:19:47 PM PDT 24 May 23 01:20:01 PM PDT 24 17921100 ps
T1098 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1135616289 May 23 01:20:01 PM PDT 24 May 23 01:20:18 PM PDT 24 16898100 ps
T243 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1093710482 May 23 01:20:29 PM PDT 24 May 23 01:20:47 PM PDT 24 17809900 ps
T67 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2245987138 May 23 01:20:04 PM PDT 24 May 23 01:27:49 PM PDT 24 443161500 ps
T187 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1742033221 May 23 01:20:04 PM PDT 24 May 23 01:20:24 PM PDT 24 154855200 ps
T221 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4003449202 May 23 01:19:55 PM PDT 24 May 23 01:20:17 PM PDT 24 58064800 ps
T186 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.779872373 May 23 01:19:55 PM PDT 24 May 23 01:20:15 PM PDT 24 46424800 ps
T244 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1390818414 May 23 01:20:19 PM PDT 24 May 23 01:20:34 PM PDT 24 28870200 ps
T339 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2539419314 May 23 01:20:08 PM PDT 24 May 23 01:20:24 PM PDT 24 64658400 ps
T236 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3174952676 May 23 01:20:01 PM PDT 24 May 23 01:27:38 PM PDT 24 181626200 ps
T338 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1416544465 May 23 01:20:01 PM PDT 24 May 23 01:20:17 PM PDT 24 16576200 ps
T340 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1998325816 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 54520200 ps
T344 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2560032594 May 23 01:20:09 PM PDT 24 May 23 01:20:24 PM PDT 24 78454600 ps
T1099 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4101206222 May 23 01:20:11 PM PDT 24 May 23 01:20:26 PM PDT 24 31104500 ps
T1100 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.538496106 May 23 01:20:06 PM PDT 24 May 23 01:20:24 PM PDT 24 13493000 ps
T346 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.663115940 May 23 01:20:20 PM PDT 24 May 23 01:20:35 PM PDT 24 29122500 ps
T343 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3810409216 May 23 01:20:18 PM PDT 24 May 23 01:20:33 PM PDT 24 16849400 ps
T237 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2917427365 May 23 01:20:21 PM PDT 24 May 23 01:20:41 PM PDT 24 153096300 ps
T238 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2058636565 May 23 01:20:08 PM PDT 24 May 23 01:20:28 PM PDT 24 169532800 ps
T240 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3521941824 May 23 01:19:55 PM PDT 24 May 23 01:35:10 PM PDT 24 1767728500 ps
T239 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2773897784 May 23 01:20:03 PM PDT 24 May 23 01:20:26 PM PDT 24 118730400 ps
T1101 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.159852029 May 23 01:20:24 PM PDT 24 May 23 01:20:44 PM PDT 24 14365100 ps
T308 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2051427985 May 23 01:19:53 PM PDT 24 May 23 01:20:54 PM PDT 24 1902299900 ps
T282 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2336716337 May 23 01:20:09 PM PDT 24 May 23 01:20:27 PM PDT 24 34658200 ps
T283 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.738575866 May 23 01:19:51 PM PDT 24 May 23 01:20:27 PM PDT 24 440791300 ps
T1102 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3687168313 May 23 01:20:20 PM PDT 24 May 23 01:20:35 PM PDT 24 14250600 ps
T254 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1731486706 May 23 01:19:58 PM PDT 24 May 23 01:35:10 PM PDT 24 669363500 ps
T284 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.226240567 May 23 01:20:01 PM PDT 24 May 23 01:20:21 PM PDT 24 52070100 ps
T1103 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.591432194 May 23 01:19:50 PM PDT 24 May 23 01:20:13 PM PDT 24 12806100 ps
T1104 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.233549300 May 23 01:20:28 PM PDT 24 May 23 01:20:46 PM PDT 24 49617400 ps
T248 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.457479347 May 23 01:19:59 PM PDT 24 May 23 01:20:47 PM PDT 24 112668800 ps
T341 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.942160504 May 23 01:20:16 PM PDT 24 May 23 01:20:31 PM PDT 24 28237100 ps
T285 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.723893977 May 23 01:20:13 PM PDT 24 May 23 01:20:49 PM PDT 24 114274800 ps
T286 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.42352954 May 23 01:20:13 PM PDT 24 May 23 01:20:32 PM PDT 24 38851700 ps
T345 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1666423591 May 23 01:20:04 PM PDT 24 May 23 01:20:20 PM PDT 24 57313100 ps
T297 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3812043945 May 23 01:19:52 PM PDT 24 May 23 01:20:09 PM PDT 24 72275300 ps
T1105 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1475965804 May 23 01:19:47 PM PDT 24 May 23 01:20:04 PM PDT 24 13818200 ps
T1106 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3614279626 May 23 01:19:53 PM PDT 24 May 23 01:20:29 PM PDT 24 164269500 ps
T1107 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2259292483 May 23 01:19:46 PM PDT 24 May 23 01:20:03 PM PDT 24 13444600 ps
T271 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3360625343 May 23 01:19:57 PM PDT 24 May 23 01:27:49 PM PDT 24 3451399000 ps
T342 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.519323222 May 23 01:20:07 PM PDT 24 May 23 01:20:23 PM PDT 24 73941200 ps
T1108 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3338205730 May 23 01:19:56 PM PDT 24 May 23 01:20:16 PM PDT 24 402774500 ps
T298 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1254698897 May 23 01:20:16 PM PDT 24 May 23 01:20:36 PM PDT 24 168775500 ps
T246 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1737848623 May 23 01:19:54 PM PDT 24 May 23 01:20:13 PM PDT 24 40893000 ps
T272 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3192670572 May 23 01:20:04 PM PDT 24 May 23 01:20:25 PM PDT 24 227544000 ps
T247 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1322548494 May 23 01:20:17 PM PDT 24 May 23 01:27:53 PM PDT 24 1758532400 ps
T1109 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1882701166 May 23 01:19:54 PM PDT 24 May 23 01:20:12 PM PDT 24 48381500 ps
T1110 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1041779619 May 23 01:20:07 PM PDT 24 May 23 01:20:31 PM PDT 24 1219164900 ps
T253 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1675070439 May 23 01:20:09 PM PDT 24 May 23 01:20:29 PM PDT 24 195083100 ps
T1111 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4085348781 May 23 01:19:58 PM PDT 24 May 23 01:20:13 PM PDT 24 68611000 ps
T1112 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2665242023 May 23 01:20:21 PM PDT 24 May 23 01:20:39 PM PDT 24 43775900 ps
T1113 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1756098848 May 23 01:20:13 PM PDT 24 May 23 01:20:30 PM PDT 24 18353700 ps
T1114 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1518761262 May 23 01:20:19 PM PDT 24 May 23 01:20:34 PM PDT 24 30950300 ps
T1115 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3311283068 May 23 01:20:01 PM PDT 24 May 23 01:20:20 PM PDT 24 26228000 ps
T1116 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3398448148 May 23 01:20:03 PM PDT 24 May 23 01:20:22 PM PDT 24 40271800 ps
T299 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1627043063 May 23 01:20:12 PM PDT 24 May 23 01:20:32 PM PDT 24 113470400 ps
T273 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1850999202 May 23 01:20:10 PM PDT 24 May 23 01:20:29 PM PDT 24 413871800 ps
T361 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1113611166 May 23 01:20:13 PM PDT 24 May 23 01:27:57 PM PDT 24 565747400 ps
T1117 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.928061058 May 23 01:20:07 PM PDT 24 May 23 01:20:23 PM PDT 24 17526700 ps
T1118 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2587068217 May 23 01:19:53 PM PDT 24 May 23 01:27:42 PM PDT 24 2637872700 ps
T241 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1827126241 May 23 01:20:01 PM PDT 24 May 23 01:20:24 PM PDT 24 61528700 ps
T1119 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1498663078 May 23 01:20:09 PM PDT 24 May 23 01:20:27 PM PDT 24 50154800 ps
T1120 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3850434845 May 23 01:19:53 PM PDT 24 May 23 01:20:33 PM PDT 24 219264100 ps
T300 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3183920012 May 23 01:19:53 PM PDT 24 May 23 01:20:13 PM PDT 24 119021100 ps
T301 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3275938721 May 23 01:19:55 PM PDT 24 May 23 01:20:13 PM PDT 24 179044500 ps
T1121 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.910908020 May 23 01:19:48 PM PDT 24 May 23 01:20:05 PM PDT 24 15935300 ps
T245 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.868352112 May 23 01:20:03 PM PDT 24 May 23 01:20:23 PM PDT 24 69680000 ps
T1122 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2328849972 May 23 01:19:56 PM PDT 24 May 23 01:20:37 PM PDT 24 4010141200 ps
T1123 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.153409098 May 23 01:19:57 PM PDT 24 May 23 01:20:13 PM PDT 24 52221000 ps
T1124 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2625702870 May 23 01:20:10 PM PDT 24 May 23 01:20:25 PM PDT 24 18477700 ps
T277 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1660540381 May 23 01:20:04 PM PDT 24 May 23 01:20:21 PM PDT 24 66817200 ps
T355 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1906401181 May 23 01:20:01 PM PDT 24 May 23 01:26:18 PM PDT 24 998158300 ps
T1125 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1156595161 May 23 01:19:52 PM PDT 24 May 23 01:20:10 PM PDT 24 19249500 ps
T1126 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3582948247 May 23 01:20:13 PM PDT 24 May 23 01:20:33 PM PDT 24 235626300 ps
T1127 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1330450164 May 23 01:20:18 PM PDT 24 May 23 01:20:33 PM PDT 24 16549600 ps
T1128 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.179034190 May 23 01:19:45 PM PDT 24 May 23 01:20:33 PM PDT 24 25678700 ps
T1129 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2956547198 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 13587600 ps
T1130 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2215957027 May 23 01:20:24 PM PDT 24 May 23 01:20:41 PM PDT 24 37434900 ps
T1131 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4127490954 May 23 01:19:49 PM PDT 24 May 23 01:20:03 PM PDT 24 48324000 ps
T1132 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3401031245 May 23 01:20:12 PM PDT 24 May 23 01:26:36 PM PDT 24 376662600 ps
T302 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.326935400 May 23 01:20:09 PM PDT 24 May 23 01:26:34 PM PDT 24 1532185100 ps
T1133 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3068310320 May 23 01:19:48 PM PDT 24 May 23 01:20:05 PM PDT 24 149615300 ps
T1134 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3916857972 May 23 01:19:53 PM PDT 24 May 23 01:20:10 PM PDT 24 13580100 ps
T303 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1638888673 May 23 01:20:10 PM PDT 24 May 23 01:20:31 PM PDT 24 110334900 ps
T1135 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2183552827 May 23 01:19:54 PM PDT 24 May 23 01:20:13 PM PDT 24 12144100 ps
T1136 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1774058015 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 15869300 ps
T1137 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.817570688 May 23 01:20:10 PM PDT 24 May 23 01:20:45 PM PDT 24 223615400 ps
T1138 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1474932414 May 23 01:20:19 PM PDT 24 May 23 01:20:36 PM PDT 24 15059800 ps
T252 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2202958492 May 23 01:19:44 PM PDT 24 May 23 01:20:02 PM PDT 24 36224700 ps
T1139 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1840302433 May 23 01:20:05 PM PDT 24 May 23 01:27:46 PM PDT 24 371879800 ps
T1140 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2279967954 May 23 01:20:01 PM PDT 24 May 23 01:20:18 PM PDT 24 17380000 ps
T1141 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3305345965 May 23 01:20:22 PM PDT 24 May 23 01:20:38 PM PDT 24 31178700 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2921691355 May 23 01:20:03 PM PDT 24 May 23 01:20:20 PM PDT 24 82594200 ps
T358 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.387669432 May 23 01:19:49 PM PDT 24 May 23 01:34:52 PM PDT 24 357422800 ps
T1143 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3371830770 May 23 01:19:57 PM PDT 24 May 23 01:20:19 PM PDT 24 168517300 ps
T1144 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2950718566 May 23 01:20:02 PM PDT 24 May 23 01:20:23 PM PDT 24 306025900 ps
T1145 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1742650832 May 23 01:20:07 PM PDT 24 May 23 01:20:23 PM PDT 24 58190000 ps
T1146 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3112646365 May 23 01:20:00 PM PDT 24 May 23 01:20:21 PM PDT 24 37258500 ps
T304 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.301927622 May 23 01:19:51 PM PDT 24 May 23 01:20:19 PM PDT 24 262861100 ps
T1147 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2349096920 May 23 01:19:55 PM PDT 24 May 23 01:20:14 PM PDT 24 13877000 ps
T1148 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3571704767 May 23 01:19:50 PM PDT 24 May 23 01:20:05 PM PDT 24 93693800 ps
T305 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1565738864 May 23 01:19:54 PM PDT 24 May 23 01:20:13 PM PDT 24 120049400 ps
T1149 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.287669439 May 23 01:19:57 PM PDT 24 May 23 01:20:12 PM PDT 24 27615100 ps
T1150 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2303565396 May 23 01:19:44 PM PDT 24 May 23 01:19:59 PM PDT 24 16499100 ps
T1151 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4081383005 May 23 01:19:58 PM PDT 24 May 23 01:20:20 PM PDT 24 15799300 ps
T1152 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1685383019 May 23 01:19:55 PM PDT 24 May 23 01:20:15 PM PDT 24 607682100 ps
T1153 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2855450956 May 23 01:19:58 PM PDT 24 May 23 01:20:24 PM PDT 24 43469100 ps
T1154 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1267928387 May 23 01:20:09 PM PDT 24 May 23 01:20:27 PM PDT 24 55315600 ps
T1155 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1469633683 May 23 01:20:22 PM PDT 24 May 23 01:20:39 PM PDT 24 44133300 ps
T1156 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.744064652 May 23 01:19:59 PM PDT 24 May 23 01:20:33 PM PDT 24 19873300 ps
T1157 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2484897566 May 23 01:19:59 PM PDT 24 May 23 01:21:21 PM PDT 24 2384139400 ps
T1158 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.652874002 May 23 01:20:16 PM PDT 24 May 23 01:20:31 PM PDT 24 17162300 ps
T1159 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1060260402 May 23 01:20:11 PM PDT 24 May 23 01:20:26 PM PDT 24 17735500 ps
T1160 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.321745758 May 23 01:20:16 PM PDT 24 May 23 01:20:34 PM PDT 24 30320400 ps
T1161 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4227562466 May 23 01:19:53 PM PDT 24 May 23 01:20:11 PM PDT 24 90612500 ps
T357 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.4173489840 May 23 01:19:57 PM PDT 24 May 23 01:35:00 PM PDT 24 368741700 ps
T306 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4217750291 May 23 01:20:05 PM PDT 24 May 23 01:20:24 PM PDT 24 545763100 ps
T1162 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.192273456 May 23 01:20:23 PM PDT 24 May 23 01:20:40 PM PDT 24 16328200 ps
T249 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1146427735 May 23 01:19:58 PM PDT 24 May 23 01:20:21 PM PDT 24 230071200 ps
T1163 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3448950324 May 23 01:19:45 PM PDT 24 May 23 01:20:37 PM PDT 24 3225893800 ps
T307 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1445708489 May 23 01:19:49 PM PDT 24 May 23 01:20:21 PM PDT 24 205955800 ps
T1164 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1481195805 May 23 01:20:07 PM PDT 24 May 23 01:20:22 PM PDT 24 50086200 ps
T1165 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2102252361 May 23 01:19:52 PM PDT 24 May 23 01:20:12 PM PDT 24 453719500 ps
T1166 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2148851207 May 23 01:20:03 PM PDT 24 May 23 01:20:23 PM PDT 24 67308100 ps
T1167 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4292432447 May 23 01:19:55 PM PDT 24 May 23 01:20:14 PM PDT 24 292342200 ps
T1168 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2572734488 May 23 01:20:23 PM PDT 24 May 23 01:20:39 PM PDT 24 19707000 ps
T1169 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1084136855 May 23 01:20:06 PM PDT 24 May 23 01:20:25 PM PDT 24 102394500 ps
T1170 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2828923536 May 23 01:19:52 PM PDT 24 May 23 01:20:08 PM PDT 24 28091400 ps
T1171 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.96977640 May 23 01:19:55 PM PDT 24 May 23 01:20:15 PM PDT 24 108149200 ps
T360 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1944681582 May 23 01:19:44 PM PDT 24 May 23 01:27:34 PM PDT 24 986581000 ps
T1172 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4183454620 May 23 01:20:17 PM PDT 24 May 23 01:20:40 PM PDT 24 268365100 ps
T1173 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1178240829 May 23 01:19:53 PM PDT 24 May 23 01:20:11 PM PDT 24 13282100 ps
T1174 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3477792704 May 23 01:20:25 PM PDT 24 May 23 01:20:43 PM PDT 24 18013000 ps
T255 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.99317757 May 23 01:19:55 PM PDT 24 May 23 01:35:11 PM PDT 24 1566588300 ps
T1175 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1165813132 May 23 01:20:09 PM PDT 24 May 23 01:20:24 PM PDT 24 25873700 ps
T1176 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.756612926 May 23 01:20:09 PM PDT 24 May 23 01:20:25 PM PDT 24 50855300 ps
T1177 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1992650398 May 23 01:19:59 PM PDT 24 May 23 01:20:21 PM PDT 24 66905200 ps
T1178 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1168374457 May 23 01:19:50 PM PDT 24 May 23 01:20:07 PM PDT 24 65773200 ps
T1179 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2276046370 May 23 01:20:21 PM PDT 24 May 23 01:20:36 PM PDT 24 99211400 ps
T1180 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.435127096 May 23 01:19:57 PM PDT 24 May 23 01:20:13 PM PDT 24 339358800 ps
T1181 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3077292226 May 23 01:20:13 PM PDT 24 May 23 01:20:32 PM PDT 24 428448800 ps
T276 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3293394825 May 23 01:20:02 PM PDT 24 May 23 01:20:19 PM PDT 24 17677200 ps
T278 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3095861233 May 23 01:19:55 PM PDT 24 May 23 01:20:11 PM PDT 24 88012200 ps
T1182 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1088516217 May 23 01:19:51 PM PDT 24 May 23 01:20:39 PM PDT 24 80690000 ps
T1183 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1396243182 May 23 01:20:03 PM PDT 24 May 23 01:20:19 PM PDT 24 23732100 ps
T359 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.167858143 May 23 01:19:59 PM PDT 24 May 23 01:32:40 PM PDT 24 721108100 ps
T1184 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1937166895 May 23 01:20:02 PM PDT 24 May 23 01:20:21 PM PDT 24 44323600 ps
T1185 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.694583730 May 23 01:20:01 PM PDT 24 May 23 01:20:21 PM PDT 24 635062500 ps
T1186 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4219842797 May 23 01:19:53 PM PDT 24 May 23 01:21:00 PM PDT 24 1804804100 ps
T1187 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3244128994 May 23 01:20:16 PM PDT 24 May 23 01:20:34 PM PDT 24 145145300 ps
T1188 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.962878648 May 23 01:20:11 PM PDT 24 May 23 01:20:25 PM PDT 24 67448300 ps
T1189 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4247514799 May 23 01:19:59 PM PDT 24 May 23 01:20:36 PM PDT 24 864740100 ps
T279 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2961356917 May 23 01:19:57 PM PDT 24 May 23 01:20:13 PM PDT 24 54305900 ps
T251 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1071247973 May 23 01:19:56 PM PDT 24 May 23 01:20:18 PM PDT 24 59278000 ps
T250 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2079107724 May 23 01:19:54 PM PDT 24 May 23 01:20:16 PM PDT 24 59339400 ps
T1190 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.244468631 May 23 01:20:03 PM PDT 24 May 23 01:20:21 PM PDT 24 26046500 ps
T1191 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1114301 May 23 01:19:55 PM PDT 24 May 23 01:20:13 PM PDT 24 12019300 ps
T1192 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3677405657 May 23 01:20:12 PM PDT 24 May 23 01:20:29 PM PDT 24 106925600 ps
T1193 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2903880452 May 23 01:19:45 PM PDT 24 May 23 01:20:00 PM PDT 24 15454400 ps
T1194 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2471350973 May 23 01:19:59 PM PDT 24 May 23 01:20:18 PM PDT 24 162224400 ps
T280 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2828905690 May 23 01:20:04 PM PDT 24 May 23 01:20:21 PM PDT 24 107247400 ps
T1195 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.141708426 May 23 01:20:07 PM PDT 24 May 23 01:20:23 PM PDT 24 16603000 ps
T256 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3059498571 May 23 01:19:50 PM PDT 24 May 23 01:26:21 PM PDT 24 1545378500 ps
T1196 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3677510902 May 23 01:19:54 PM PDT 24 May 23 01:20:12 PM PDT 24 19436000 ps
T1197 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2457188778 May 23 01:19:59 PM PDT 24 May 23 01:20:15 PM PDT 24 16873800 ps
T1198 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4073056347 May 23 01:20:03 PM PDT 24 May 23 01:20:22 PM PDT 24 22006800 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1425441982 May 23 01:19:51 PM PDT 24 May 23 01:20:22 PM PDT 24 233486000 ps
T1200 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4272836781 May 23 01:19:56 PM PDT 24 May 23 01:20:14 PM PDT 24 11379000 ps
T356 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4176133352 May 23 01:20:00 PM PDT 24 May 23 01:34:58 PM PDT 24 1390455700 ps
T1201 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2747630217 May 23 01:20:00 PM PDT 24 May 23 01:20:21 PM PDT 24 46135100 ps
T1202 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3529496611 May 23 01:19:56 PM PDT 24 May 23 01:20:17 PM PDT 24 103314700 ps
T1203 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1481872389 May 23 01:20:24 PM PDT 24 May 23 01:20:47 PM PDT 24 463305100 ps
T1204 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2442880485 May 23 01:19:51 PM PDT 24 May 23 01:20:08 PM PDT 24 86744500 ps
T1205 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3019914618 May 23 01:20:06 PM PDT 24 May 23 01:20:22 PM PDT 24 36252100 ps
T1206 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2643800054 May 23 01:20:15 PM PDT 24 May 23 01:20:33 PM PDT 24 27940400 ps
T1207 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1582344474 May 23 01:20:20 PM PDT 24 May 23 01:20:36 PM PDT 24 53244600 ps
T1208 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1812081864 May 23 01:20:20 PM PDT 24 May 23 01:20:38 PM PDT 24 116033700 ps
T1209 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3765214769 May 23 01:20:04 PM PDT 24 May 23 01:20:26 PM PDT 24 83604000 ps
T1210 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.703671356 May 23 01:20:05 PM PDT 24 May 23 01:20:26 PM PDT 24 63596800 ps
T1211 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2842618774 May 23 01:20:03 PM PDT 24 May 23 01:20:20 PM PDT 24 28581300 ps
T1212 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1838905107 May 23 01:19:57 PM PDT 24 May 23 01:20:17 PM PDT 24 35050400 ps
T1213 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1889764657 May 23 01:19:53 PM PDT 24 May 23 01:20:34 PM PDT 24 787269500 ps
T1214 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2135527641 May 23 01:20:03 PM PDT 24 May 23 01:20:20 PM PDT 24 57330500 ps
T1215 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3024011142 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 28377700 ps
T1216 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3073508301 May 23 01:19:50 PM PDT 24 May 23 01:20:05 PM PDT 24 103498100 ps
T1217 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1170954098 May 23 01:20:13 PM PDT 24 May 23 01:20:31 PM PDT 24 59198200 ps
T1218 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3369544528 May 23 01:20:00 PM PDT 24 May 23 01:20:16 PM PDT 24 23122400 ps
T1219 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2186516962 May 23 01:20:03 PM PDT 24 May 23 01:20:22 PM PDT 24 33011600 ps
T1220 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2890495957 May 23 01:20:02 PM PDT 24 May 23 01:20:24 PM PDT 24 314130800 ps
T1221 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4132245705 May 23 01:20:09 PM PDT 24 May 23 01:20:26 PM PDT 24 40221300 ps
T1222 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3396712845 May 23 01:20:09 PM PDT 24 May 23 01:20:28 PM PDT 24 42095700 ps
T1223 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3571149186 May 23 01:19:55 PM PDT 24 May 23 01:20:13 PM PDT 24 20400300 ps
T1224 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3218659649 May 23 01:19:51 PM PDT 24 May 23 01:20:08 PM PDT 24 37302000 ps
T1225 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1259281168 May 23 01:19:52 PM PDT 24 May 23 01:20:07 PM PDT 24 17649700 ps
T1226 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2795090551 May 23 01:20:06 PM PDT 24 May 23 01:20:25 PM PDT 24 65022500 ps
T1227 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1657538972 May 23 01:19:52 PM PDT 24 May 23 01:20:14 PM PDT 24 230936300 ps
T1228 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1573599851 May 23 01:20:01 PM PDT 24 May 23 01:20:21 PM PDT 24 32785500 ps
T1229 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2395830499 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 30461000 ps
T1230 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4294591903 May 23 01:20:13 PM PDT 24 May 23 01:20:28 PM PDT 24 65701200 ps
T1231 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3913351746 May 23 01:19:51 PM PDT 24 May 23 01:20:38 PM PDT 24 80551200 ps
T1232 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4053251018 May 23 01:20:08 PM PDT 24 May 23 01:20:26 PM PDT 24 88416100 ps
T1233 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1606312009 May 23 01:19:40 PM PDT 24 May 23 01:19:55 PM PDT 24 48314300 ps
T1234 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2039586753 May 23 01:19:43 PM PDT 24 May 23 01:20:00 PM PDT 24 30771800 ps
T1235 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3808500030 May 23 01:19:58 PM PDT 24 May 23 01:20:17 PM PDT 24 175149700 ps
T1236 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1504483189 May 23 01:20:16 PM PDT 24 May 23 01:20:32 PM PDT 24 40272500 ps
T1237 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1341005718 May 23 01:19:50 PM PDT 24 May 23 01:21:06 PM PDT 24 2717974200 ps
T1238 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2149882866 May 23 01:20:08 PM PDT 24 May 23 01:20:24 PM PDT 24 91497800 ps
T1239 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.866367941 May 23 01:19:52 PM PDT 24 May 23 01:20:09 PM PDT 24 34020600 ps
T1240 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3939015730 May 23 01:20:08 PM PDT 24 May 23 01:20:26 PM PDT 24 12811000 ps
T1241 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.10179439 May 23 01:19:49 PM PDT 24 May 23 01:20:04 PM PDT 24 77768000 ps
T1242 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.538089756 May 23 01:19:55 PM PDT 24 May 23 01:20:13 PM PDT 24 45604300 ps
T1243 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.217961078 May 23 01:19:55 PM PDT 24 May 23 01:20:15 PM PDT 24 75422800 ps

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.2099639088
Short name T4
Test name
Test status
Simulation time 486316400 ps
CPU time 886.9 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 283756 kb
Host smart-17732d1f-78b1-4a75-ae2f-2ad045d56064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099639088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.2099639088
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2245987138
Short name T67
Test name
Test status
Simulation time 443161500 ps
CPU time 460.72 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:27:49 PM PDT 24
Peak memory 264136 kb
Host smart-c513352e-6b0f-4d2a-ad44-598df3e87ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245987138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2245987138
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.3154528663
Short name T11
Test name
Test status
Simulation time 80144028200 ps
CPU time 908.53 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:44:33 PM PDT 24
Peak memory 263100 kb
Host smart-06e5d308-b71e-4a94-88c5-39cb97c9d04b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154528663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.3154528663
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.661446280
Short name T21
Test name
Test status
Simulation time 1268508000 ps
CPU time 22.28 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:28:20 PM PDT 24
Peak memory 265052 kb
Host smart-cc701958-43c1-4641-856a-25b12f99a9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661446280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.661446280
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2261697010
Short name T1
Test name
Test status
Simulation time 3886320600 ps
CPU time 608.86 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:37:59 PM PDT 24
Peak memory 328776 kb
Host smart-a273c7fb-31df-4f85-aeba-42f81b585819
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261697010 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2261697010
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.83297909
Short name T43
Test name
Test status
Simulation time 5719696400 ps
CPU time 4701.34 seconds
Started May 23 01:27:24 PM PDT 24
Finished May 23 02:45:47 PM PDT 24
Peak memory 288124 kb
Host smart-90e91048-9455-4d09-94b5-b43a48b0a951
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83297909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.83297909
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1796672423
Short name T44
Test name
Test status
Simulation time 3354456800 ps
CPU time 502.52 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:36:26 PM PDT 24
Peak memory 261388 kb
Host smart-7eb4ab60-afad-4f24-9ca3-40d7c6acd0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796672423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1796672423
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.695210070
Short name T105
Test name
Test status
Simulation time 8169938300 ps
CPU time 143.2 seconds
Started May 23 01:28:40 PM PDT 24
Finished May 23 01:31:05 PM PDT 24
Peak memory 265176 kb
Host smart-2d4e49c4-bf46-465a-80f7-49fe2738ae58
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695210070 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_mp_regions.695210070
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2058636565
Short name T238
Test name
Test status
Simulation time 169532800 ps
CPU time 18.54 seconds
Started May 23 01:20:08 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 264172 kb
Host smart-aea8330b-a4cc-4e7e-91c3-7b957dedbde9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058636565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2058636565
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.828568577
Short name T35
Test name
Test status
Simulation time 13632413800 ps
CPU time 248.23 seconds
Started May 23 01:28:15 PM PDT 24
Finished May 23 01:32:24 PM PDT 24
Peak memory 284332 kb
Host smart-22304c18-423e-4cd6-84c6-5d0a279de059
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828568577 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.828568577
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1864186757
Short name T8
Test name
Test status
Simulation time 14822900 ps
CPU time 13.84 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:28:07 PM PDT 24
Peak memory 265340 kb
Host smart-7ab1dd73-dbdf-4987-a455-1e561e374b3d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864186757 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1864186757
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1223660712
Short name T163
Test name
Test status
Simulation time 842576300 ps
CPU time 70.52 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:29:17 PM PDT 24
Peak memory 259928 kb
Host smart-6aaeecd1-66d9-4c5f-b301-341d63ae38a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223660712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1223660712
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2712617312
Short name T70
Test name
Test status
Simulation time 142562400 ps
CPU time 129.72 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 259692 kb
Host smart-569968fc-37db-429c-9134-93a6f2f88b31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712617312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2712617312
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2136750997
Short name T119
Test name
Test status
Simulation time 23369041400 ps
CPU time 122.95 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:34:27 PM PDT 24
Peak memory 262560 kb
Host smart-740a8999-5f15-4a8d-8ef0-3823099ae825
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136750997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.2136750997
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1731486706
Short name T254
Test name
Test status
Simulation time 669363500 ps
CPU time 909.87 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:35:10 PM PDT 24
Peak memory 262232 kb
Host smart-d5102eee-9316-47bc-b8b4-02f769607d20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731486706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1731486706
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1356395487
Short name T141
Test name
Test status
Simulation time 117706100 ps
CPU time 132.48 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:33:52 PM PDT 24
Peak memory 264556 kb
Host smart-92a8fdf5-f81e-45e1-9e44-08b3e7eb4531
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356395487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1356395487
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2539419314
Short name T339
Test name
Test status
Simulation time 64658400 ps
CPU time 13.61 seconds
Started May 23 01:20:08 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 262348 kb
Host smart-9d677a85-df65-46cc-8ae8-d7b044b67243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539419314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2539419314
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3361577908
Short name T147
Test name
Test status
Simulation time 42328100 ps
CPU time 133.85 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:30:17 PM PDT 24
Peak memory 259832 kb
Host smart-436a1dfc-9e90-461a-a4e2-07000f2bab59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361577908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3361577908
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2644097096
Short name T161
Test name
Test status
Simulation time 3616137300 ps
CPU time 71.78 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:28:38 PM PDT 24
Peak memory 264960 kb
Host smart-35c58d09-c12a-44b7-97e6-3b68d69f482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644097096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2644097096
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3766036280
Short name T31
Test name
Test status
Simulation time 1690710600 ps
CPU time 73.49 seconds
Started May 23 01:30:44 PM PDT 24
Finished May 23 01:31:59 PM PDT 24
Peak memory 262856 kb
Host smart-0973fc65-f406-4f5a-bd55-d12bd18657f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766036280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3766036280
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3626301597
Short name T139
Test name
Test status
Simulation time 10055730600 ps
CPU time 49.79 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:28:22 PM PDT 24
Peak memory 272776 kb
Host smart-48a69075-d46c-4763-9603-4fd324eda1a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626301597 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3626301597
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3016472774
Short name T182
Test name
Test status
Simulation time 113753900 ps
CPU time 14.05 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:32:09 PM PDT 24
Peak memory 264500 kb
Host smart-9361dbec-b28b-4b00-8722-3b2b3957db87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016472774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3016472774
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.990469945
Short name T132
Test name
Test status
Simulation time 40389000 ps
CPU time 109.96 seconds
Started May 23 01:31:03 PM PDT 24
Finished May 23 01:32:54 PM PDT 24
Peak memory 259684 kb
Host smart-74684754-064c-4b89-9479-09193c208ab6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990469945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot
p_reset.990469945
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1436369153
Short name T94
Test name
Test status
Simulation time 7333340800 ps
CPU time 617.9 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 334140 kb
Host smart-4137f463-c578-40f9-8e9a-64b904162099
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436369153 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1436369153
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3082721096
Short name T72
Test name
Test status
Simulation time 10475200 ps
CPU time 22.17 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:31:16 PM PDT 24
Peak memory 273184 kb
Host smart-2c5c6a3b-2cff-4ad8-9ace-38b2466dd582
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082721096 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3082721096
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3702339761
Short name T148
Test name
Test status
Simulation time 408682521300 ps
CPU time 2087.69 seconds
Started May 23 01:27:54 PM PDT 24
Finished May 23 02:02:43 PM PDT 24
Peak memory 265112 kb
Host smart-f4ed76a5-df20-4add-adbf-beb011a638db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702339761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3702339761
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.1149254985
Short name T143
Test name
Test status
Simulation time 567130800 ps
CPU time 111.69 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:33:45 PM PDT 24
Peak memory 261160 kb
Host smart-30cc25f0-ebba-4544-9196-d830d619bc04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149254985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.1149254985
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.4083072141
Short name T136
Test name
Test status
Simulation time 81946588500 ps
CPU time 905.24 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:42:53 PM PDT 24
Peak memory 259320 kb
Host smart-2394525e-207f-49df-8e58-367ddfb4ffcd
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083072141 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.4083072141
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3293394825
Short name T276
Test name
Test status
Simulation time 17677200 ps
CPU time 13.55 seconds
Started May 23 01:20:02 PM PDT 24
Finished May 23 01:20:19 PM PDT 24
Peak memory 263992 kb
Host smart-eb98e1c3-1d5e-4e26-b37c-59d9c6170c83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293394825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.3293394825
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.1285687389
Short name T78
Test name
Test status
Simulation time 54574349300 ps
CPU time 403.23 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:35:40 PM PDT 24
Peak memory 273224 kb
Host smart-07c43361-9265-4e7c-916d-cd1d7e2bc5f5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285687389 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.1285687389
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1827126241
Short name T241
Test name
Test status
Simulation time 61528700 ps
CPU time 20.49 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 264176 kb
Host smart-649a24a3-e34b-476c-82f2-71ee7c07cf7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827126241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1827126241
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.2990862774
Short name T62
Test name
Test status
Simulation time 2018640500 ps
CPU time 182.84 seconds
Started May 23 01:28:51 PM PDT 24
Finished May 23 01:31:55 PM PDT 24
Peak memory 292388 kb
Host smart-ea369415-006f-498b-989e-1c60b8570ff9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990862774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.2990862774
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3689852536
Short name T6
Test name
Test status
Simulation time 3217320600 ps
CPU time 2682.18 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 02:12:42 PM PDT 24
Peak memory 265104 kb
Host smart-2a51b192-e328-465a-840b-87762812c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689852536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3689852536
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.4177394154
Short name T131
Test name
Test status
Simulation time 26457500 ps
CPU time 13.42 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 265252 kb
Host smart-60441dee-b8d0-4e74-bc0f-f79f642f939e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177394154 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.4177394154
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3454661501
Short name T25
Test name
Test status
Simulation time 41237800 ps
CPU time 29.46 seconds
Started May 23 01:30:44 PM PDT 24
Finished May 23 01:31:15 PM PDT 24
Peak memory 276336 kb
Host smart-5b3c5333-f45e-4f33-90cc-f773e4f8c745
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454661501 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3454661501
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.942160504
Short name T341
Test name
Test status
Simulation time 28237100 ps
CPU time 13.67 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:31 PM PDT 24
Peak memory 262668 kb
Host smart-ceab2cfc-fd63-4404-b7d0-d98275898f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942160504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.942160504
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1117891577
Short name T93
Test name
Test status
Simulation time 8663923500 ps
CPU time 69.94 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:29:14 PM PDT 24
Peak memory 263072 kb
Host smart-00be7d9d-b41c-4466-a686-9920d1a23e59
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117891577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1117891577
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.171199736
Short name T216
Test name
Test status
Simulation time 53974400 ps
CPU time 31.42 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:29:59 PM PDT 24
Peak memory 273604 kb
Host smart-625364da-b752-4dce-b374-ca27792649d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171199736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.171199736
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.99317757
Short name T255
Test name
Test status
Simulation time 1566588300 ps
CPU time 913.13 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:35:11 PM PDT 24
Peak memory 263824 kb
Host smart-476f059f-7080-41a1-87db-f94c80ad6fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99317757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_t
l_intg_err.99317757
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.1991295901
Short name T9
Test name
Test status
Simulation time 45841000 ps
CPU time 15.14 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 265108 kb
Host smart-ff6412df-5848-4a9f-aa1c-f131c9534561
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991295901 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1991295901
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3482921660
Short name T407
Test name
Test status
Simulation time 1187052100 ps
CPU time 178.15 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:31:03 PM PDT 24
Peak memory 281636 kb
Host smart-a77b0f3b-80d8-4243-9e48-5833e9a24422
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482921660 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3482921660
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4062481768
Short name T55
Test name
Test status
Simulation time 816757600 ps
CPU time 15.84 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:28:21 PM PDT 24
Peak memory 260332 kb
Host smart-bc0fbf8d-ac56-4aa7-9d50-41bef587c7a1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062481768 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.4062481768
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4176133352
Short name T356
Test name
Test status
Simulation time 1390455700 ps
CPU time 895 seconds
Started May 23 01:20:00 PM PDT 24
Finished May 23 01:34:58 PM PDT 24
Peak memory 263260 kb
Host smart-321f7621-907f-4282-99bf-f31cd437960b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176133352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.4176133352
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.1320997771
Short name T74
Test name
Test status
Simulation time 30145400 ps
CPU time 22.44 seconds
Started May 23 01:30:05 PM PDT 24
Finished May 23 01:30:29 PM PDT 24
Peak memory 273564 kb
Host smart-8dabc8ce-f290-4c56-871b-8374246accf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320997771 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.1320997771
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.2701890927
Short name T59
Test name
Test status
Simulation time 44219900 ps
CPU time 13.75 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:28:00 PM PDT 24
Peak memory 279424 kb
Host smart-b8e651d5-f9fc-46b0-bfff-f875e0db18f5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2701890927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2701890927
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2453204794
Short name T84
Test name
Test status
Simulation time 4510038800 ps
CPU time 75.22 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:33:40 PM PDT 24
Peak memory 263280 kb
Host smart-8ec7e520-12b0-4c62-bd54-8ffa322aa766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453204794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2453204794
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.11027970
Short name T350
Test name
Test status
Simulation time 25228836700 ps
CPU time 207.26 seconds
Started May 23 01:28:29 PM PDT 24
Finished May 23 01:31:58 PM PDT 24
Peak memory 293536 kb
Host smart-55cbc6fd-7ad2-4358-b685-2e99ad718792
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027970 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.11027970
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3314885150
Short name T327
Test name
Test status
Simulation time 132757800 ps
CPU time 38.88 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 273480 kb
Host smart-d9031a63-191b-4ba8-aff4-bcbb6e88c1bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314885150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3314885150
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1850999202
Short name T273
Test name
Test status
Simulation time 413871800 ps
CPU time 17.53 seconds
Started May 23 01:20:10 PM PDT 24
Finished May 23 01:20:29 PM PDT 24
Peak memory 270652 kb
Host smart-7d8bf579-08dd-45cc-a3c4-787059c78705
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850999202 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1850999202
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.2790640880
Short name T188
Test name
Test status
Simulation time 16210000 ps
CPU time 15.63 seconds
Started May 23 01:28:12 PM PDT 24
Finished May 23 01:28:28 PM PDT 24
Peak memory 275584 kb
Host smart-36e7a1d6-b911-4310-ad49-b0e6d5f0f24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790640880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2790640880
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3156570735
Short name T18
Test name
Test status
Simulation time 17246800 ps
CPU time 13.42 seconds
Started May 23 01:29:22 PM PDT 24
Finished May 23 01:29:37 PM PDT 24
Peak memory 265084 kb
Host smart-a437db53-649b-4680-8b83-3892d018ddc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156570735 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3156570735
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3664819160
Short name T38
Test name
Test status
Simulation time 364121300 ps
CPU time 38.06 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 01:28:28 PM PDT 24
Peak memory 265192 kb
Host smart-19205d7a-6810-4897-aa09-8c892d37ce53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664819160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3664819160
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.2313763748
Short name T196
Test name
Test status
Simulation time 24497336000 ps
CPU time 325.44 seconds
Started May 23 01:31:12 PM PDT 24
Finished May 23 01:36:39 PM PDT 24
Peak memory 284084 kb
Host smart-4572ce9c-9d02-4d85-ada4-903fe5454fa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313763748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.2313763748
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.443590290
Short name T331
Test name
Test status
Simulation time 126932000 ps
CPU time 32.88 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:29:29 PM PDT 24
Peak memory 276852 kb
Host smart-515ca1f5-0ca3-46b7-b142-39e4dc454af6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443590290 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.443590290
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2993458663
Short name T213
Test name
Test status
Simulation time 15514700 ps
CPU time 14.14 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 01:27:52 PM PDT 24
Peak memory 265340 kb
Host smart-609b7e85-a14b-4064-95b8-14336bb91a04
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993458663 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2993458663
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3995489109
Short name T57
Test name
Test status
Simulation time 534206200 ps
CPU time 21.49 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:28:44 PM PDT 24
Peak memory 265124 kb
Host smart-85593d4d-e4a8-42e2-9f06-a8808d2d690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995489109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3995489109
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4003449202
Short name T221
Test name
Test status
Simulation time 58064800 ps
CPU time 19.45 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 264188 kb
Host smart-17a2ff51-5151-4e13-8c0e-8e9c6b70ab1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003449202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.4
003449202
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3335886997
Short name T50
Test name
Test status
Simulation time 68862500 ps
CPU time 13.95 seconds
Started May 23 01:27:28 PM PDT 24
Finished May 23 01:27:43 PM PDT 24
Peak memory 265312 kb
Host smart-cca23a69-ae55-4341-b181-925d3a72dd70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335886997 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3335886997
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2677869806
Short name T207
Test name
Test status
Simulation time 14539091400 ps
CPU time 560.34 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 313616 kb
Host smart-3489a587-7130-41cc-b895-351a3c32f6df
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677869806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.2677869806
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2875490721
Short name T295
Test name
Test status
Simulation time 47523400 ps
CPU time 13.79 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:24 PM PDT 24
Peak memory 264188 kb
Host smart-6bc7a17a-1ff3-4304-8037-5ce0390ac831
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875490721 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2875490721
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.2126472347
Short name T146
Test name
Test status
Simulation time 144118400 ps
CPU time 134.76 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:34:39 PM PDT 24
Peak memory 264236 kb
Host smart-32eaeed9-a72f-4ea8-9932-27276874aa76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126472347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.2126472347
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1455092298
Short name T592
Test name
Test status
Simulation time 44464000 ps
CPU time 13.64 seconds
Started May 23 01:27:28 PM PDT 24
Finished May 23 01:27:43 PM PDT 24
Peak memory 265352 kb
Host smart-77414256-9567-4a08-a30c-611039ca1430
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455092298 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1455092298
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2842962136
Short name T838
Test name
Test status
Simulation time 10119585500 ps
CPU time 34.58 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:28:27 PM PDT 24
Peak memory 265416 kb
Host smart-7d58ae6a-17a4-4b7c-9090-3ad08ce856ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842962136 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2842962136
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.146443044
Short name T134
Test name
Test status
Simulation time 10052369400 ps
CPU time 79.5 seconds
Started May 23 01:30:45 PM PDT 24
Finished May 23 01:32:06 PM PDT 24
Peak memory 266364 kb
Host smart-4d6aeb95-d5c2-486d-a3c1-e9bd295c4bda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146443044 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.146443044
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1322548494
Short name T247
Test name
Test status
Simulation time 1758532400 ps
CPU time 454.5 seconds
Started May 23 01:20:17 PM PDT 24
Finished May 23 01:27:53 PM PDT 24
Peak memory 260604 kb
Host smart-71d604ca-e771-4cab-ad28-5d2fbaab1557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322548494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1322548494
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.153409098
Short name T1123
Test name
Test status
Simulation time 52221000 ps
CPU time 13.49 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 262600 kb
Host smart-c20e28e4-3203-401c-906c-39ea65932df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153409098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.153409098
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3867253849
Short name T394
Test name
Test status
Simulation time 869248700 ps
CPU time 58.27 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:28:25 PM PDT 24
Peak memory 262376 kb
Host smart-1d72d3fb-f1e9-49fb-abd2-16ab98206f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867253849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3867253849
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.3720354719
Short name T411
Test name
Test status
Simulation time 6789234600 ps
CPU time 68.87 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:31:07 PM PDT 24
Peak memory 259932 kb
Host smart-6b9a656f-b310-40f3-b461-211c96472c5d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720354719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3
720354719
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3563198293
Short name T383
Test name
Test status
Simulation time 126115600 ps
CPU time 112.03 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:34:41 PM PDT 24
Peak memory 259720 kb
Host smart-97acd5f8-ea89-441e-9a71-1c37596b9e79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563198293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3563198293
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.2674023861
Short name T210
Test name
Test status
Simulation time 1185346900 ps
CPU time 151.79 seconds
Started May 23 01:28:27 PM PDT 24
Finished May 23 01:31:01 PM PDT 24
Peak memory 282120 kb
Host smart-7d9133f2-ba7d-45ab-88a6-2a9c2f9036c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2674023861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2674023861
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.2276407867
Short name T73
Test name
Test status
Simulation time 575201948600 ps
CPU time 2169.16 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 02:03:41 PM PDT 24
Peak memory 265180 kb
Host smart-6580d8f5-0ec9-4d8e-a414-5eb767336784
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276407867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.2276407867
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3418146219
Short name T822
Test name
Test status
Simulation time 29669100 ps
CPU time 31.75 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:30:42 PM PDT 24
Peak memory 275512 kb
Host smart-07f82ad4-0cae-4dc9-919b-18cc600778e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418146219 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3418146219
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1667483856
Short name T128
Test name
Test status
Simulation time 755465300 ps
CPU time 21 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:27:50 PM PDT 24
Peak memory 265428 kb
Host smart-62bdcda1-304c-4ab8-9dfe-d4c7ab9c99ef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667483856 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1667483856
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.519829140
Short name T42
Test name
Test status
Simulation time 5235190300 ps
CPU time 4706.37 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 02:46:04 PM PDT 24
Peak memory 287556 kb
Host smart-d664a19a-f884-414b-ad60-23d4dbf17401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519829140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.519829140
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2490720170
Short name T46
Test name
Test status
Simulation time 25433400 ps
CPU time 20.91 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:27:49 PM PDT 24
Peak memory 273520 kb
Host smart-e2a2c39d-685d-49c2-8cce-4687c8bd82cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490720170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2490720170
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.3486319282
Short name T330
Test name
Test status
Simulation time 346277800 ps
CPU time 42.31 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:28:15 PM PDT 24
Peak memory 265156 kb
Host smart-a87afd05-9765-49b7-aff4-5e732c7105dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486319282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.3486319282
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1587664355
Short name T412
Test name
Test status
Simulation time 3139744600 ps
CPU time 60.13 seconds
Started May 23 01:27:21 PM PDT 24
Finished May 23 01:28:22 PM PDT 24
Peak memory 262684 kb
Host smart-e5401be2-313f-4d98-991a-be9432ce7105
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587664355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1587664355
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.792425863
Short name T387
Test name
Test status
Simulation time 16250100 ps
CPU time 21.79 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 01:28:00 PM PDT 24
Peak memory 265248 kb
Host smart-ba626fb9-c3fd-4e66-a0c2-bd548b9e828e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792425863 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.792425863
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.3432217746
Short name T267
Test name
Test status
Simulation time 4276923200 ps
CPU time 205.34 seconds
Started May 23 01:29:10 PM PDT 24
Finished May 23 01:32:37 PM PDT 24
Peak memory 289920 kb
Host smart-06f77c7b-1e86-430f-859c-80a7008f96f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432217746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.3432217746
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1444329265
Short name T390
Test name
Test status
Simulation time 23835039500 ps
CPU time 85.28 seconds
Started May 23 01:29:27 PM PDT 24
Finished May 23 01:30:53 PM PDT 24
Peak memory 263528 kb
Host smart-85305231-f7cc-44c4-bb76-abdbf2e8882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444329265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1444329265
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.2641420388
Short name T400
Test name
Test status
Simulation time 1282585000 ps
CPU time 68.77 seconds
Started May 23 01:30:22 PM PDT 24
Finished May 23 01:31:33 PM PDT 24
Peak memory 263276 kb
Host smart-89d1ebb2-b7c1-4405-a20f-9cb72c083a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641420388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2641420388
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1640462930
Short name T379
Test name
Test status
Simulation time 60128468200 ps
CPU time 882.24 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:45:06 PM PDT 24
Peak memory 263468 kb
Host smart-3d846463-a819-43f2-9804-eb0dc9f4680a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640462930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1640462930
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3652050108
Short name T395
Test name
Test status
Simulation time 1281448600 ps
CPU time 61.96 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:37 PM PDT 24
Peak memory 263124 kb
Host smart-1bf53fa6-1154-4e73-992f-7e83f9857875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652050108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3652050108
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3712737438
Short name T364
Test name
Test status
Simulation time 10780800 ps
CPU time 21.9 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:11 PM PDT 24
Peak memory 273436 kb
Host smart-f9593a6b-a5ac-4aa6-81d7-e25928a6abb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712737438 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3712737438
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.287647919
Short name T335
Test name
Test status
Simulation time 40177800 ps
CPU time 31.51 seconds
Started May 23 01:27:54 PM PDT 24
Finished May 23 01:28:26 PM PDT 24
Peak memory 273560 kb
Host smart-13edec08-853a-4281-8b10-967d02e9222d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287647919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_rw_evict.287647919
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.4261482992
Short name T1038
Test name
Test status
Simulation time 43713800 ps
CPU time 20.77 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:31:33 PM PDT 24
Peak memory 265324 kb
Host smart-31769d60-8596-4b99-8e47-afc2b49d37e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261482992 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.4261482992
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.670561815
Short name T363
Test name
Test status
Simulation time 21112000 ps
CPU time 13.74 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 265036 kb
Host smart-47879f63-693c-4476-83fa-be276317eeec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670561815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.670561815
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.4139519753
Short name T367
Test name
Test status
Simulation time 10915000 ps
CPU time 22.08 seconds
Started May 23 01:31:43 PM PDT 24
Finished May 23 01:32:06 PM PDT 24
Peak memory 280716 kb
Host smart-ece982d8-8d53-46a7-8ca7-988d80bfea94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139519753 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.4139519753
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.990856002
Short name T398
Test name
Test status
Simulation time 4124523800 ps
CPU time 75.38 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:33:40 PM PDT 24
Peak memory 264552 kb
Host smart-580bf09b-fbca-430a-8aaf-f30c4119f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990856002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.990856002
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.724302042
Short name T388
Test name
Test status
Simulation time 2533088200 ps
CPU time 61.7 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:33:41 PM PDT 24
Peak memory 263176 kb
Host smart-e30974f3-2a1f-4a70-a420-fc4bbef8e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724302042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.724302042
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1458487675
Short name T393
Test name
Test status
Simulation time 1415696700 ps
CPU time 59.12 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:55 PM PDT 24
Peak memory 264000 kb
Host smart-58545cd8-0964-4b6f-8957-4c83d8e56c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458487675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1458487675
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3868990185
Short name T446
Test name
Test status
Simulation time 10259666300 ps
CPU time 64.67 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:53 PM PDT 24
Peak memory 259628 kb
Host smart-3c3d53d2-96a9-4f0d-9a9f-df02f4d6f286
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868990185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3868990185
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1657538972
Short name T1227
Test name
Test status
Simulation time 230936300 ps
CPU time 19.8 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:14 PM PDT 24
Peak memory 264248 kb
Host smart-acd9e71d-879c-42aa-ae57-7182be42406b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657538972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
657538972
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.538620852
Short name T125
Test name
Test status
Simulation time 147209200 ps
CPU time 205.66 seconds
Started May 23 01:30:34 PM PDT 24
Finished May 23 01:34:01 PM PDT 24
Peak memory 281516 kb
Host smart-90b9a847-ee8c-43e5-88d2-2f1c22bd49bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538620852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.538620852
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2419241459
Short name T223
Test name
Test status
Simulation time 94601400 ps
CPU time 13.58 seconds
Started May 23 01:28:15 PM PDT 24
Finished May 23 01:28:29 PM PDT 24
Peak memory 265444 kb
Host smart-d6a20321-69c9-4f87-ae07-8a540387de44
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2419241459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.2419241459
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3718292301
Short name T180
Test name
Test status
Simulation time 27723779000 ps
CPU time 294.06 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:33:50 PM PDT 24
Peak memory 292296 kb
Host smart-f832f71a-a358-4299-93b6-c2515e4a5f0f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718292301 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3718292301
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3059498571
Short name T256
Test name
Test status
Simulation time 1545378500 ps
CPU time 389.09 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:26:21 PM PDT 24
Peak memory 262756 kb
Host smart-2c2a4a77-d7b6-4aee-8fa6-a57c03fe1720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059498571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3059498571
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2575220732
Short name T935
Test name
Test status
Simulation time 8710636400 ps
CPU time 2384.67 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 02:07:13 PM PDT 24
Peak memory 264764 kb
Host smart-c2749c5f-bbaf-45f4-b06a-80a1cfed42d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575220732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2575220732
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.771726031
Short name T946
Test name
Test status
Simulation time 1051356500 ps
CPU time 965.37 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 273268 kb
Host smart-9cb38089-4372-4930-8ec7-dffe38595587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771726031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.771726031
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2777059302
Short name T264
Test name
Test status
Simulation time 9281912300 ps
CPU time 555.79 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:36:49 PM PDT 24
Peak memory 338064 kb
Host smart-ed00c228-1882-46c5-8f4d-464f62e26a68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777059302 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2777059302
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2107170858
Short name T64
Test name
Test status
Simulation time 923671800 ps
CPU time 17.01 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 265400 kb
Host smart-e1101605-e5fd-4a72-984a-a7a228238986
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107170858 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2107170858
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3610609923
Short name T231
Test name
Test status
Simulation time 164539400 ps
CPU time 15.17 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:27:41 PM PDT 24
Peak memory 265032 kb
Host smart-2eade7b1-0034-492b-b6eb-463f5061cc03
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610609923 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3610609923
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.640467376
Short name T260
Test name
Test status
Simulation time 503914400 ps
CPU time 97.06 seconds
Started May 23 01:27:34 PM PDT 24
Finished May 23 01:29:12 PM PDT 24
Peak memory 281664 kb
Host smart-ab1cc7ba-2474-4852-95d7-2619a889552a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640467376 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_ro.640467376
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1889764657
Short name T1213
Test name
Test status
Simulation time 787269500 ps
CPU time 39.33 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:34 PM PDT 24
Peak memory 260452 kb
Host smart-abf64df5-a67f-49fa-9f0d-cbae1b6106a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889764657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1889764657
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2328849972
Short name T1122
Test name
Test status
Simulation time 4010141200 ps
CPU time 38.73 seconds
Started May 23 01:19:56 PM PDT 24
Finished May 23 01:20:37 PM PDT 24
Peak memory 260500 kb
Host smart-9d15ea08-a21f-475a-9c62-fbf911e02b66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328849972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.2328849972
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1088516217
Short name T1182
Test name
Test status
Simulation time 80690000 ps
CPU time 46.05 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:39 PM PDT 24
Peak memory 260420 kb
Host smart-704f767d-1e76-4657-b5b7-78ff9a9ed285
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088516217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1088516217
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3068310320
Short name T1133
Test name
Test status
Simulation time 149615300 ps
CPU time 16.66 seconds
Started May 23 01:19:48 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 279460 kb
Host smart-4362104a-a251-4ab6-ab10-cf316e637bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068310320 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3068310320
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3812043945
Short name T297
Test name
Test status
Simulation time 72275300 ps
CPU time 14.1 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:09 PM PDT 24
Peak memory 260400 kb
Host smart-d617e570-42b2-4a8e-bd1f-5ed182c302b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812043945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3812043945
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2303565396
Short name T1150
Test name
Test status
Simulation time 16499100 ps
CPU time 13.31 seconds
Started May 23 01:19:44 PM PDT 24
Finished May 23 01:19:59 PM PDT 24
Peak memory 262468 kb
Host smart-63142a71-0f05-4a72-b6c1-0e04ec500a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303565396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2
303565396
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2961356917
Short name T279
Test name
Test status
Simulation time 54305900 ps
CPU time 13.34 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 264040 kb
Host smart-014514f8-c114-46d2-aeb1-db5c15671112
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961356917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2961356917
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1606312009
Short name T1233
Test name
Test status
Simulation time 48314300 ps
CPU time 13.17 seconds
Started May 23 01:19:40 PM PDT 24
Finished May 23 01:19:55 PM PDT 24
Peak memory 262716 kb
Host smart-5a8d852f-c675-44fc-a4ce-7e509c3e3a03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606312009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1606312009
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3614279626
Short name T1106
Test name
Test status
Simulation time 164269500 ps
CPU time 34.27 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:29 PM PDT 24
Peak memory 260476 kb
Host smart-fd186d12-3ebf-4b1a-8f58-ae58ccb17eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614279626 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3614279626
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2039586753
Short name T1234
Test name
Test status
Simulation time 30771800 ps
CPU time 15.39 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 260452 kb
Host smart-a3617d1a-bcee-46bb-b24c-eccec9146631
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039586753 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2039586753
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4073056347
Short name T1198
Test name
Test status
Simulation time 22006800 ps
CPU time 15.64 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 260272 kb
Host smart-edbc4aa9-c0fe-4aa2-a786-e61633c8374c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073056347 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.4073056347
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.4173489840
Short name T357
Test name
Test status
Simulation time 368741700 ps
CPU time 900.79 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:35:00 PM PDT 24
Peak memory 264220 kb
Host smart-74e26ffd-7e0f-4eed-a6c4-ed4cd897c797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173489840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.4173489840
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4247514799
Short name T1189
Test name
Test status
Simulation time 864740100 ps
CPU time 34.11 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:36 PM PDT 24
Peak memory 260480 kb
Host smart-cd39c0cf-8348-417d-8556-0f400d7a95b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247514799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.4247514799
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3448950324
Short name T1163
Test name
Test status
Simulation time 3225893800 ps
CPU time 50.73 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:20:37 PM PDT 24
Peak memory 260496 kb
Host smart-dfb212e1-c2fe-4db9-a99f-e0f927cfcd98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448950324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3448950324
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.179034190
Short name T1128
Test name
Test status
Simulation time 25678700 ps
CPU time 46.39 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 260532 kb
Host smart-d0ce3076-762c-415e-9c10-e32a4c76744a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179034190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.179034190
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3371830770
Short name T1143
Test name
Test status
Simulation time 168517300 ps
CPU time 19.39 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:19 PM PDT 24
Peak memory 272236 kb
Host smart-fed9606c-232d-4055-8cb4-60c50458e202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371830770 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3371830770
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.10179439
Short name T1241
Test name
Test status
Simulation time 77768000 ps
CPU time 14.16 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:20:04 PM PDT 24
Peak memory 260428 kb
Host smart-cf712100-8574-4795-8083-71d4a2699051
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10179439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_csr_rw.10179439
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3754746031
Short name T242
Test name
Test status
Simulation time 17921100 ps
CPU time 13.55 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:20:01 PM PDT 24
Peak memory 262820 kb
Host smart-7e64dc60-199d-4043-a7a0-929ee78c83a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754746031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
754746031
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2903880452
Short name T1193
Test name
Test status
Simulation time 15454400 ps
CPU time 13.65 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 262556 kb
Host smart-142d61f8-e5a8-430e-884f-251cdae538c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903880452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2903880452
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4217750291
Short name T306
Test name
Test status
Simulation time 545763100 ps
CPU time 15.53 seconds
Started May 23 01:20:05 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 260588 kb
Host smart-01b2e899-4094-481b-8c03-44e972b6d6db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217750291 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.4217750291
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2183552827
Short name T1135
Test name
Test status
Simulation time 12144100 ps
CPU time 15.94 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260504 kb
Host smart-afb39034-a1dd-4fea-b025-5dd9234d8eba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183552827 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2183552827
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1475965804
Short name T1105
Test name
Test status
Simulation time 13818200 ps
CPU time 16.1 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:20:04 PM PDT 24
Peak memory 260472 kb
Host smart-246aa53d-fa9d-4ec8-8f0b-4806d1dfb602
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475965804 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1475965804
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1168374457
Short name T1178
Test name
Test status
Simulation time 65773200 ps
CPU time 16.05 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:20:07 PM PDT 24
Peak memory 264176 kb
Host smart-a9b77a16-806d-4f0b-a31e-f8438af4844a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168374457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1
168374457
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1481872389
Short name T1203
Test name
Test status
Simulation time 463305100 ps
CPU time 19.5 seconds
Started May 23 01:20:24 PM PDT 24
Finished May 23 01:20:47 PM PDT 24
Peak memory 278408 kb
Host smart-eaa1506a-ed78-453e-8b22-a68e21b21755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481872389 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1481872389
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1685383019
Short name T1152
Test name
Test status
Simulation time 607682100 ps
CPU time 17.32 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 260604 kb
Host smart-0195f563-fa0c-48b1-85fc-44be6384873e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685383019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.1685383019
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2149882866
Short name T1238
Test name
Test status
Simulation time 91497800 ps
CPU time 13.65 seconds
Started May 23 01:20:08 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 262896 kb
Host smart-98bc7073-6d26-4298-a215-101fd814d7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149882866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2149882866
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2442880485
Short name T1204
Test name
Test status
Simulation time 86744500 ps
CPU time 15.36 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:08 PM PDT 24
Peak memory 260572 kb
Host smart-5847c576-b480-451b-92db-94b9d4b2b474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442880485 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2442880485
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3398448148
Short name T1116
Test name
Test status
Simulation time 40271800 ps
CPU time 15.5 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 260448 kb
Host smart-4dc1eced-01ad-4a09-a775-44d0c7e49057
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398448148 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3398448148
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2349096920
Short name T1147
Test name
Test status
Simulation time 13877000 ps
CPU time 16.07 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:14 PM PDT 24
Peak memory 260432 kb
Host smart-e0530395-e233-4814-80bd-2c85b9cfef28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349096920 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2349096920
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3396712845
Short name T1222
Test name
Test status
Simulation time 42095700 ps
CPU time 17.43 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 264148 kb
Host smart-e8a291e6-1897-4ae9-b8ac-f57e45d8061a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396712845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
3396712845
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.167858143
Short name T359
Test name
Test status
Simulation time 721108100 ps
CPU time 758.5 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 261864 kb
Host smart-d2a6a514-5353-4af2-a28d-0b5e0e390770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167858143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.167858143
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3192670572
Short name T272
Test name
Test status
Simulation time 227544000 ps
CPU time 17.28 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 262584 kb
Host smart-8b105e60-819c-4410-9374-c114567757c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192670572 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3192670572
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3435030727
Short name T66
Test name
Test status
Simulation time 37571300 ps
CPU time 16.02 seconds
Started May 23 01:20:14 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 260540 kb
Host smart-07eae691-1ff8-4b29-bd23-aa911e970536
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435030727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3435030727
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2921691355
Short name T1142
Test name
Test status
Simulation time 82594200 ps
CPU time 13.43 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 262624 kb
Host smart-8f5dfe52-a5a1-4714-ae01-785da4927c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921691355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
2921691355
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3112646365
Short name T1146
Test name
Test status
Simulation time 37258500 ps
CPU time 17.75 seconds
Started May 23 01:20:00 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 263776 kb
Host smart-51993a4e-f1cd-47c1-b40b-cb042ea9026e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112646365 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3112646365
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1259281168
Short name T1225
Test name
Test status
Simulation time 17649700 ps
CPU time 13.16 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:07 PM PDT 24
Peak memory 260244 kb
Host smart-830e0635-fbac-4dd1-a9bb-0f103904e1ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259281168 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1259281168
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3939015730
Short name T1240
Test name
Test status
Simulation time 12811000 ps
CPU time 16.02 seconds
Started May 23 01:20:08 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 260388 kb
Host smart-a9e817dc-dd6a-45c7-bef1-9a074ab1ded0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939015730 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3939015730
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1146427735
Short name T249
Test name
Test status
Simulation time 230071200 ps
CPU time 20.49 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 264148 kb
Host smart-4058bd6c-3905-4c88-a6bf-0d0214f96ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146427735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
1146427735
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1084136855
Short name T1169
Test name
Test status
Simulation time 102394500 ps
CPU time 17.07 seconds
Started May 23 01:20:06 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 272292 kb
Host smart-c004db57-8989-47ef-9d2a-3415e92a9ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084136855 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1084136855
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2148851207
Short name T1166
Test name
Test status
Simulation time 67308100 ps
CPU time 16.23 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 260552 kb
Host smart-86d76426-23f2-4cf1-86ce-4f517ec44863
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148851207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.2148851207
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2279967954
Short name T1140
Test name
Test status
Simulation time 17380000 ps
CPU time 13.81 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:18 PM PDT 24
Peak memory 262876 kb
Host smart-549c5abe-b9d1-47f0-800b-a395f25384a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279967954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2279967954
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1638888673
Short name T303
Test name
Test status
Simulation time 110334900 ps
CPU time 18.85 seconds
Started May 23 01:20:10 PM PDT 24
Finished May 23 01:20:31 PM PDT 24
Peak memory 260452 kb
Host smart-2c007a46-5a8e-49ab-a388-ea80a9cf5f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638888673 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1638888673
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1170954098
Short name T1217
Test name
Test status
Simulation time 59198200 ps
CPU time 15.71 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:31 PM PDT 24
Peak memory 260288 kb
Host smart-316cf43c-c253-466d-903b-7546e36974ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170954098 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1170954098
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4272836781
Short name T1200
Test name
Test status
Simulation time 11379000 ps
CPU time 15.72 seconds
Started May 23 01:19:56 PM PDT 24
Finished May 23 01:20:14 PM PDT 24
Peak memory 260464 kb
Host smart-8b922856-7fe5-4c69-a03f-b46258492857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272836781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.4272836781
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1071247973
Short name T251
Test name
Test status
Simulation time 59278000 ps
CPU time 19.64 seconds
Started May 23 01:19:56 PM PDT 24
Finished May 23 01:20:18 PM PDT 24
Peak memory 264192 kb
Host smart-140299f4-5d9c-4bb1-a992-85b2c180fae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071247973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1071247973
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3401031245
Short name T1132
Test name
Test status
Simulation time 376662600 ps
CPU time 382.8 seconds
Started May 23 01:20:12 PM PDT 24
Finished May 23 01:26:36 PM PDT 24
Peak memory 264224 kb
Host smart-911b9578-c5b0-4015-b37d-bbaa80bad526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401031245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3401031245
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1675070439
Short name T253
Test name
Test status
Simulation time 195083100 ps
CPU time 18.04 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:29 PM PDT 24
Peak memory 272356 kb
Host smart-2fece14c-12bf-49f5-bf82-ea9d963a1482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675070439 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1675070439
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3338205730
Short name T1108
Test name
Test status
Simulation time 402774500 ps
CPU time 17.26 seconds
Started May 23 01:19:56 PM PDT 24
Finished May 23 01:20:16 PM PDT 24
Peak memory 260508 kb
Host smart-7c454607-5451-4d56-a3dc-64d7a0086146
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338205730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.3338205730
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3024011142
Short name T1215
Test name
Test status
Simulation time 28377700 ps
CPU time 13.44 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 262764 kb
Host smart-53f57f2e-1c4c-423f-84d4-050580eed9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024011142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
3024011142
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1041779619
Short name T1110
Test name
Test status
Simulation time 1219164900 ps
CPU time 21.74 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:31 PM PDT 24
Peak memory 262328 kb
Host smart-0d0d3dfa-8924-40ce-a54e-2d26b0f0bbc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041779619 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1041779619
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.538089756
Short name T1242
Test name
Test status
Simulation time 45604300 ps
CPU time 16.09 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260424 kb
Host smart-46fe8cb0-10d0-4d8f-a95e-578cff03e83d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538089756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.538089756
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1178240829
Short name T1173
Test name
Test status
Simulation time 13282100 ps
CPU time 15.48 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:11 PM PDT 24
Peak memory 260292 kb
Host smart-a7c19c09-9f86-4ddb-832b-f2c34a91acb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178240829 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1178240829
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2890495957
Short name T1220
Test name
Test status
Simulation time 314130800 ps
CPU time 19.75 seconds
Started May 23 01:20:02 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 264188 kb
Host smart-fa161fb0-803d-4667-941f-a6858cafa9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890495957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2890495957
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2587068217
Short name T1118
Test name
Test status
Simulation time 2637872700 ps
CPU time 467.03 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:27:42 PM PDT 24
Peak memory 264136 kb
Host smart-d66c9259-0b03-4d0f-b12c-86274cc8bd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587068217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2587068217
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3765214769
Short name T1209
Test name
Test status
Simulation time 83604000 ps
CPU time 19.11 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 270520 kb
Host smart-1eee41a7-741f-4224-9c2f-bd307a83a971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765214769 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3765214769
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1937166895
Short name T1184
Test name
Test status
Simulation time 44323600 ps
CPU time 16.58 seconds
Started May 23 01:20:02 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260472 kb
Host smart-60e0f7c8-ff1b-4a34-942a-a1798ef8b93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937166895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1937166895
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2560032594
Short name T344
Test name
Test status
Simulation time 78454600 ps
CPU time 13.46 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 262788 kb
Host smart-4c5c1aac-5d3e-44bf-a193-c98020cf15d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560032594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2560032594
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3677405657
Short name T1192
Test name
Test status
Simulation time 106925600 ps
CPU time 15.58 seconds
Started May 23 01:20:12 PM PDT 24
Finished May 23 01:20:29 PM PDT 24
Peak memory 260392 kb
Host smart-f51dc90b-6c49-4504-83c9-924985da0305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677405657 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.3677405657
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1756098848
Short name T1113
Test name
Test status
Simulation time 18353700 ps
CPU time 15.89 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:30 PM PDT 24
Peak memory 260424 kb
Host smart-9a4c2a37-fc4d-4f60-aa61-31b979354765
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756098848 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1756098848
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.159852029
Short name T1101
Test name
Test status
Simulation time 14365100 ps
CPU time 15.94 seconds
Started May 23 01:20:24 PM PDT 24
Finished May 23 01:20:44 PM PDT 24
Peak memory 260424 kb
Host smart-a9f7aeda-313b-4b4f-b00c-4441cab7ef2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159852029 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.159852029
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3521941824
Short name T240
Test name
Test status
Simulation time 1767728500 ps
CPU time 912.73 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:35:10 PM PDT 24
Peak memory 264100 kb
Host smart-01abd2dd-756d-4913-95f2-ebe875e5698d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521941824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3521941824
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3077292226
Short name T1181
Test name
Test status
Simulation time 428448800 ps
CPU time 16.89 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 270616 kb
Host smart-778897cc-54be-45e5-b698-9095c40a6f11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077292226 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3077292226
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.42352954
Short name T286
Test name
Test status
Simulation time 38851700 ps
CPU time 17.42 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 260476 kb
Host smart-87d728ea-d5ab-43e0-9ff7-487de45313c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.flash_ctrl_csr_rw.42352954
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.244468631
Short name T1190
Test name
Test status
Simulation time 26046500 ps
CPU time 13.74 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 262656 kb
Host smart-109ca138-9dc0-4a57-8374-737b1a70e931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244468631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.244468631
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.96977640
Short name T1171
Test name
Test status
Simulation time 108149200 ps
CPU time 18.25 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 260524 kb
Host smart-970079ae-298a-4eeb-8084-b31ec5ed546c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96977640 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.96977640
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2643800054
Short name T1206
Test name
Test status
Simulation time 27940400 ps
CPU time 16.55 seconds
Started May 23 01:20:15 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 260488 kb
Host smart-fb60a3c6-465d-465b-883f-6c8d18c973c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643800054 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2643800054
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4132245705
Short name T1221
Test name
Test status
Simulation time 40221300 ps
CPU time 15.58 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 260368 kb
Host smart-cf6aa7ef-6900-40c1-9018-267997048d96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132245705 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.4132245705
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1267928387
Short name T1154
Test name
Test status
Simulation time 55315600 ps
CPU time 15.47 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:27 PM PDT 24
Peak memory 264180 kb
Host smart-512dbf5e-5024-4b34-9922-8d2e0aad8d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267928387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1267928387
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1840302433
Short name T1139
Test name
Test status
Simulation time 371879800 ps
CPU time 458 seconds
Started May 23 01:20:05 PM PDT 24
Finished May 23 01:27:46 PM PDT 24
Peak memory 260576 kb
Host smart-642d4c64-19ef-44a2-be68-e77f3c0f77c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840302433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1840302433
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3582948247
Short name T1126
Test name
Test status
Simulation time 235626300 ps
CPU time 18.27 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 272096 kb
Host smart-55617525-a17f-4e68-a16f-04db7cc9b1ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582948247 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3582948247
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.703671356
Short name T1210
Test name
Test status
Simulation time 63596800 ps
CPU time 17.96 seconds
Started May 23 01:20:05 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 260600 kb
Host smart-43a5be98-9332-4213-b21f-52924c0ae932
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703671356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_csr_rw.703671356
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.519323222
Short name T342
Test name
Test status
Simulation time 73941200 ps
CPU time 13.54 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 262804 kb
Host smart-d8b7bcfa-da67-4075-8680-1d846119019e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519323222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.519323222
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1627043063
Short name T299
Test name
Test status
Simulation time 113470400 ps
CPU time 17.91 seconds
Started May 23 01:20:12 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 262020 kb
Host smart-f2d99d2f-febe-4ecf-b6f2-e5ecb0a1f0e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627043063 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1627043063
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4101206222
Short name T1099
Test name
Test status
Simulation time 31104500 ps
CPU time 13.26 seconds
Started May 23 01:20:11 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 260340 kb
Host smart-8d712df4-d186-4a31-9a5b-c3446b33a150
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101206222 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.4101206222
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.321745758
Short name T1160
Test name
Test status
Simulation time 30320400 ps
CPU time 15.98 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:34 PM PDT 24
Peak memory 260472 kb
Host smart-dab6e9aa-d488-4638-bd8e-b43131cbf16d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321745758 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.321745758
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2186516962
Short name T1219
Test name
Test status
Simulation time 33011600 ps
CPU time 15.94 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 264140 kb
Host smart-e9249c97-4ca8-46d0-94f0-7b1b99054f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186516962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2186516962
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1113611166
Short name T361
Test name
Test status
Simulation time 565747400 ps
CPU time 462.51 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:27:57 PM PDT 24
Peak memory 264168 kb
Host smart-664d5f05-1251-43c8-80ae-698c54fc35ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113611166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.1113611166
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2917427365
Short name T237
Test name
Test status
Simulation time 153096300 ps
CPU time 17.01 seconds
Started May 23 01:20:21 PM PDT 24
Finished May 23 01:20:41 PM PDT 24
Peak memory 278816 kb
Host smart-b72deabd-637c-46e8-9342-a1c055c3df7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917427365 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2917427365
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2795090551
Short name T1226
Test name
Test status
Simulation time 65022500 ps
CPU time 16.1 seconds
Started May 23 01:20:06 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 260428 kb
Host smart-ca190564-5050-4aea-a3ff-c0801d8f8d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795090551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2795090551
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1254698897
Short name T298
Test name
Test status
Simulation time 168775500 ps
CPU time 18.79 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:36 PM PDT 24
Peak memory 262040 kb
Host smart-c1802a4a-7b92-4057-a353-50f956205d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254698897 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1254698897
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2956547198
Short name T1129
Test name
Test status
Simulation time 13587600 ps
CPU time 13.5 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 260512 kb
Host smart-52375677-e5b7-4272-a900-64265a8f14a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956547198 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2956547198
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3687168313
Short name T1102
Test name
Test status
Simulation time 14250600 ps
CPU time 13.03 seconds
Started May 23 01:20:20 PM PDT 24
Finished May 23 01:20:35 PM PDT 24
Peak memory 260420 kb
Host smart-52dd3e2c-fac3-4195-b090-08f8f578773b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687168313 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3687168313
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3244128994
Short name T1187
Test name
Test status
Simulation time 145145300 ps
CPU time 16.27 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:34 PM PDT 24
Peak memory 278276 kb
Host smart-ef5dc672-7652-4089-9045-621ed376c536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244128994 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3244128994
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1498663078
Short name T1119
Test name
Test status
Simulation time 50154800 ps
CPU time 16.54 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:27 PM PDT 24
Peak memory 260452 kb
Host smart-d0de5591-e127-4769-af48-5beb64c35490
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498663078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1498663078
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2625702870
Short name T1124
Test name
Test status
Simulation time 18477700 ps
CPU time 13.42 seconds
Started May 23 01:20:10 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 262756 kb
Host smart-8baa1bbd-2037-4f43-80c3-320200b51989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625702870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2625702870
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4183454620
Short name T1172
Test name
Test status
Simulation time 268365100 ps
CPU time 21.38 seconds
Started May 23 01:20:17 PM PDT 24
Finished May 23 01:20:40 PM PDT 24
Peak memory 260372 kb
Host smart-c65f722a-6993-4fbf-820b-25e2dcbfcaa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183454620 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.4183454620
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1396243182
Short name T1183
Test name
Test status
Simulation time 23732100 ps
CPU time 13.23 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:19 PM PDT 24
Peak memory 260480 kb
Host smart-44cfb77b-18b7-4a29-a3ba-26121b774bc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396243182 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1396243182
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2665242023
Short name T1112
Test name
Test status
Simulation time 43775900 ps
CPU time 15.83 seconds
Started May 23 01:20:21 PM PDT 24
Finished May 23 01:20:39 PM PDT 24
Peak memory 260448 kb
Host smart-622b0901-4f4a-40b5-aa2d-50e57c920e40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665242023 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.2665242023
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2773897784
Short name T239
Test name
Test status
Simulation time 118730400 ps
CPU time 19.37 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 264108 kb
Host smart-d75cf141-cb85-4441-a8bc-b00e1a0eb3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773897784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2773897784
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.326935400
Short name T302
Test name
Test status
Simulation time 1532185100 ps
CPU time 383.03 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:26:34 PM PDT 24
Peak memory 262636 kb
Host smart-29f5bc83-1c0e-46cf-bbc3-c5e7d29d391a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326935400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_tl_intg_err.326935400
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2336716337
Short name T282
Test name
Test status
Simulation time 34658200 ps
CPU time 16.32 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:27 PM PDT 24
Peak memory 260448 kb
Host smart-9a2b1e76-0953-45fb-bf48-7c6b42edd8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336716337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2336716337
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4081383005
Short name T1151
Test name
Test status
Simulation time 15799300 ps
CPU time 13.67 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 262956 kb
Host smart-36103b1a-c631-480a-9c5a-7cadfcbe64c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081383005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
4081383005
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.723893977
Short name T285
Test name
Test status
Simulation time 114274800 ps
CPU time 34.53 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:49 PM PDT 24
Peak memory 262160 kb
Host smart-f9f22641-c96d-48d6-a3ba-6edcc5fd62af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723893977 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.723893977
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3019914618
Short name T1205
Test name
Test status
Simulation time 36252100 ps
CPU time 13.31 seconds
Started May 23 01:20:06 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 260428 kb
Host smart-7f7f0b87-316b-46b3-85ed-eea1a1bfa427
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019914618 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3019914618
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.538496106
Short name T1100
Test name
Test status
Simulation time 13493000 ps
CPU time 15.64 seconds
Started May 23 01:20:06 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 260476 kb
Host smart-68e41dc1-98eb-4ac8-a0a3-240c2fc68016
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538496106 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.538496106
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1812081864
Short name T1208
Test name
Test status
Simulation time 116033700 ps
CPU time 15.99 seconds
Started May 23 01:20:20 PM PDT 24
Finished May 23 01:20:38 PM PDT 24
Peak memory 264152 kb
Host smart-94963044-d33e-4a1b-99e9-a4970c7e884c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812081864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
1812081864
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.940313362
Short name T65
Test name
Test status
Simulation time 981676100 ps
CPU time 464.36 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:27:45 PM PDT 24
Peak memory 260476 kb
Host smart-2c7d2a97-a1ef-416a-b959-519fd157fa48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940313362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_tl_intg_err.940313362
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.817570688
Short name T1137
Test name
Test status
Simulation time 223615400 ps
CPU time 33.34 seconds
Started May 23 01:20:10 PM PDT 24
Finished May 23 01:20:45 PM PDT 24
Peak memory 260472 kb
Host smart-3a396f30-fd4a-4d3f-a880-d5e94274d2bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817570688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_aliasing.817570688
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4219842797
Short name T1186
Test name
Test status
Simulation time 1804804100 ps
CPU time 64.97 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:21:00 PM PDT 24
Peak memory 262368 kb
Host smart-ea14a2e2-c3d4-4e24-8710-cf43edaa8d4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219842797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.4219842797
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.457479347
Short name T248
Test name
Test status
Simulation time 112668800 ps
CPU time 45.75 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:47 PM PDT 24
Peak memory 260540 kb
Host smart-3c593b79-d907-4e03-b347-425476fd9c8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457479347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.457479347
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3808500030
Short name T1235
Test name
Test status
Simulation time 175149700 ps
CPU time 17.24 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 270436 kb
Host smart-a8111229-b0c1-4ce6-81e2-bd576bd07be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808500030 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3808500030
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.694583730
Short name T1185
Test name
Test status
Simulation time 635062500 ps
CPU time 16.92 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260500 kb
Host smart-4cd21a04-51fd-4b24-b490-12195f3322b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694583730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.694583730
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2828905690
Short name T280
Test name
Test status
Simulation time 107247400 ps
CPU time 13.84 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 261124 kb
Host smart-5de21e3c-d5ff-429c-9f4d-640117ae30af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828905690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2828905690
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1135616289
Short name T1098
Test name
Test status
Simulation time 16898100 ps
CPU time 13.74 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:18 PM PDT 24
Peak memory 262796 kb
Host smart-aa7c4d89-d8bd-4ba3-883b-bffbef8caf81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135616289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1135616289
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.301927622
Short name T304
Test name
Test status
Simulation time 262861100 ps
CPU time 20.64 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:19 PM PDT 24
Peak memory 262236 kb
Host smart-0eb40061-90cf-4d15-bfeb-a7adc0c1ad81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301927622 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.301927622
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2259292483
Short name T1107
Test name
Test status
Simulation time 13444600 ps
CPU time 15.73 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:20:03 PM PDT 24
Peak memory 260536 kb
Host smart-dcbc744b-2d04-4e6b-8cdc-cd8c10bba641
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259292483 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2259292483
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4085348781
Short name T1111
Test name
Test status
Simulation time 68611000 ps
CPU time 13.2 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260384 kb
Host smart-3e4cb98f-43e4-4974-ad3e-dbc4a8c74dd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085348781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.4085348781
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2202958492
Short name T252
Test name
Test status
Simulation time 36224700 ps
CPU time 16.48 seconds
Started May 23 01:19:44 PM PDT 24
Finished May 23 01:20:02 PM PDT 24
Peak memory 264164 kb
Host smart-8c9379b7-a81e-4b7d-9ed8-644062f64baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202958492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
202958492
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3360625343
Short name T271
Test name
Test status
Simulation time 3451399000 ps
CPU time 470.44 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:27:49 PM PDT 24
Peak memory 264204 kb
Host smart-b7dea0b1-b9a7-4173-8150-173203b31b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360625343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3360625343
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2457188778
Short name T1197
Test name
Test status
Simulation time 16873800 ps
CPU time 13.63 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 262676 kb
Host smart-11c60eaf-e485-4aed-8a06-02d72a9b95d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457188778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2457188778
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1165813132
Short name T1175
Test name
Test status
Simulation time 25873700 ps
CPU time 13.37 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 262524 kb
Host smart-41d6c16a-f76c-4e5f-8039-e254882561e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165813132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
1165813132
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.141708426
Short name T1195
Test name
Test status
Simulation time 16603000 ps
CPU time 13.37 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 262672 kb
Host smart-832c230a-8623-4e04-86c2-6c2b9c91d9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141708426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.141708426
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2842618774
Short name T1211
Test name
Test status
Simulation time 28581300 ps
CPU time 13.71 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 262564 kb
Host smart-a63f10f7-76b4-4fd4-8dfc-11f39803b418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842618774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2842618774
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.928061058
Short name T1117
Test name
Test status
Simulation time 17526700 ps
CPU time 13.5 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 262620 kb
Host smart-b39d18fa-b5c3-4af9-ba74-fa0d485fd19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928061058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.928061058
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.652874002
Short name T1158
Test name
Test status
Simulation time 17162300 ps
CPU time 13.46 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:31 PM PDT 24
Peak memory 262424 kb
Host smart-3fd81514-7685-42fa-8c74-6dcbba8329f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652874002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.652874002
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2276046370
Short name T1179
Test name
Test status
Simulation time 99211400 ps
CPU time 13.26 seconds
Started May 23 01:20:21 PM PDT 24
Finished May 23 01:20:36 PM PDT 24
Peak memory 262612 kb
Host smart-23e326e7-15a0-43a4-8ebd-994ee52c2ac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276046370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2276046370
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1060260402
Short name T1159
Test name
Test status
Simulation time 17735500 ps
CPU time 13.4 seconds
Started May 23 01:20:11 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 262632 kb
Host smart-b941e0b9-fdfc-4196-b038-d0a2ef91fead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060260402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1060260402
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.233549300
Short name T1104
Test name
Test status
Simulation time 49617400 ps
CPU time 13.6 seconds
Started May 23 01:20:28 PM PDT 24
Finished May 23 01:20:46 PM PDT 24
Peak memory 261108 kb
Host smart-7ee13f77-c0b5-4a77-b8b5-ab70d776cda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233549300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.233549300
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2572734488
Short name T1168
Test name
Test status
Simulation time 19707000 ps
CPU time 13.77 seconds
Started May 23 01:20:23 PM PDT 24
Finished May 23 01:20:39 PM PDT 24
Peak memory 262756 kb
Host smart-a18389ba-7fd3-42b2-a8d3-8efeb1e48a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572734488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2572734488
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2051427985
Short name T308
Test name
Test status
Simulation time 1902299900 ps
CPU time 59.44 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:54 PM PDT 24
Peak memory 260464 kb
Host smart-099d423a-b208-4189-a344-969e860865b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051427985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2051427985
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1341005718
Short name T1237
Test name
Test status
Simulation time 2717974200 ps
CPU time 73.52 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:21:06 PM PDT 24
Peak memory 261932 kb
Host smart-fbb45eb9-4248-43fc-858c-1d753c86090c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341005718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1341005718
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3913351746
Short name T1231
Test name
Test status
Simulation time 80551200 ps
CPU time 45.19 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:38 PM PDT 24
Peak memory 260460 kb
Host smart-d1b32d5a-de72-457c-b9ca-02301b2bffb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913351746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3913351746
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1838905107
Short name T1212
Test name
Test status
Simulation time 35050400 ps
CPU time 17.48 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 277488 kb
Host smart-daa12c3c-99d0-45d6-a2dd-fb2a65e28f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838905107 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1838905107
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.435127096
Short name T1180
Test name
Test status
Simulation time 339358800 ps
CPU time 14.29 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260468 kb
Host smart-a65ea336-0f9c-49d2-8109-e61dcb0351c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435127096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_csr_rw.435127096
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2135527641
Short name T1214
Test name
Test status
Simulation time 57330500 ps
CPU time 13.48 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 262392 kb
Host smart-b4715a6d-73f6-491b-a1d4-f0ea753e0b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135527641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
135527641
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1660540381
Short name T277
Test name
Test status
Simulation time 66817200 ps
CPU time 13.32 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 261084 kb
Host smart-39719a53-273d-4ea8-8247-782bc2a32103
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660540381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1660540381
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.287669439
Short name T1149
Test name
Test status
Simulation time 27615100 ps
CPU time 13.19 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 262672 kb
Host smart-e8d46353-8ee7-46c3-852c-a400bf155eaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287669439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.287669439
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1565738864
Short name T305
Test name
Test status
Simulation time 120049400 ps
CPU time 16.3 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 262308 kb
Host smart-d87ba0ad-3d95-4f8f-8d0a-62c1ea844ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565738864 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1565738864
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1156595161
Short name T1125
Test name
Test status
Simulation time 19249500 ps
CPU time 15.45 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:10 PM PDT 24
Peak memory 260468 kb
Host smart-3dc44d90-8ead-4273-81bd-c8982b58d71b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156595161 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1156595161
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4053251018
Short name T1232
Test name
Test status
Simulation time 88416100 ps
CPU time 16.06 seconds
Started May 23 01:20:08 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 260436 kb
Host smart-9b325707-5a0d-44d9-895c-dc2ef2d09f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053251018 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.4053251018
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.868352112
Short name T245
Test name
Test status
Simulation time 69680000 ps
CPU time 15.93 seconds
Started May 23 01:20:03 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 264128 kb
Host smart-c9710ed2-c14d-407d-b95d-ef8ef4e04f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868352112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.868352112
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1906401181
Short name T355
Test name
Test status
Simulation time 998158300 ps
CPU time 374.89 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:26:18 PM PDT 24
Peak memory 264136 kb
Host smart-5dc7f850-1769-4a84-806e-8381769c57e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906401181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1906401181
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.962878648
Short name T1188
Test name
Test status
Simulation time 67448300 ps
CPU time 13.48 seconds
Started May 23 01:20:11 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 262740 kb
Host smart-61bf10af-9265-4e7f-8b7d-26d0509773fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962878648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.962878648
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1504483189
Short name T1236
Test name
Test status
Simulation time 40272500 ps
CPU time 13.78 seconds
Started May 23 01:20:16 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 262680 kb
Host smart-abd173c7-6e92-49d8-991a-3e3f4ef624a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504483189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1504483189
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1774058015
Short name T1136
Test name
Test status
Simulation time 15869300 ps
CPU time 13.43 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 262824 kb
Host smart-898ffe48-c28d-44ab-b355-4c76e9467faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774058015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
1774058015
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1330450164
Short name T1127
Test name
Test status
Simulation time 16549600 ps
CPU time 13.38 seconds
Started May 23 01:20:18 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 262652 kb
Host smart-ee787c9d-8bd7-4c86-a166-5cf2c3595a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330450164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1330450164
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2395830499
Short name T1229
Test name
Test status
Simulation time 30461000 ps
CPU time 13.36 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 262560 kb
Host smart-c3d00b94-e926-4224-be27-0d6e5a80c27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395830499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2395830499
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1469633683
Short name T1155
Test name
Test status
Simulation time 44133300 ps
CPU time 13.37 seconds
Started May 23 01:20:22 PM PDT 24
Finished May 23 01:20:39 PM PDT 24
Peak memory 262508 kb
Host smart-0f257969-85a8-4cae-a27f-58f8510df3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469633683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1469633683
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1582344474
Short name T1207
Test name
Test status
Simulation time 53244600 ps
CPU time 13.5 seconds
Started May 23 01:20:20 PM PDT 24
Finished May 23 01:20:36 PM PDT 24
Peak memory 262848 kb
Host smart-5908a348-53f6-4d0b-ac45-59aeb6eaa245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582344474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1582344474
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1998325816
Short name T340
Test name
Test status
Simulation time 54520200 ps
CPU time 13.52 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 261056 kb
Host smart-b79f0388-387e-4f9d-a62a-6fd2dc3b73b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998325816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1998325816
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1093710482
Short name T243
Test name
Test status
Simulation time 17809900 ps
CPU time 13.64 seconds
Started May 23 01:20:29 PM PDT 24
Finished May 23 01:20:47 PM PDT 24
Peak memory 262780 kb
Host smart-8c55de25-16e5-4560-bbee-44e7c687c098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093710482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1093710482
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.756612926
Short name T1176
Test name
Test status
Simulation time 50855300 ps
CPU time 13.87 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:25 PM PDT 24
Peak memory 262552 kb
Host smart-11d1da11-42fb-47dc-999b-ef048b8395ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756612926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.756612926
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.738575866
Short name T283
Test name
Test status
Simulation time 440791300 ps
CPU time 34.05 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:27 PM PDT 24
Peak memory 260552 kb
Host smart-fd504cdc-5542-45ac-b46b-01a21c89ebb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738575866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.738575866
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2484897566
Short name T1157
Test name
Test status
Simulation time 2384139400 ps
CPU time 79.4 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:21:21 PM PDT 24
Peak memory 260376 kb
Host smart-d4cf2258-fd63-4971-b322-8af691dad5d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484897566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2484897566
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.744064652
Short name T1156
Test name
Test status
Simulation time 19873300 ps
CPU time 31.25 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 260400 kb
Host smart-53bd1247-49a3-4965-ba81-97b98cd6258c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744064652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.744064652
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.779872373
Short name T186
Test name
Test status
Simulation time 46424800 ps
CPU time 17.59 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 270596 kb
Host smart-ab7b8426-6785-47f7-a7ba-d82b7498f2fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779872373 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.779872373
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.217961078
Short name T1243
Test name
Test status
Simulation time 75422800 ps
CPU time 17.39 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 260396 kb
Host smart-4aefc196-651f-4688-ad0f-5162e9510d8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217961078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.217961078
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2828923536
Short name T1170
Test name
Test status
Simulation time 28091400 ps
CPU time 13.36 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:08 PM PDT 24
Peak memory 262796 kb
Host smart-55cb8aca-d86c-4797-9ea7-2aabc1649df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828923536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
828923536
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3095861233
Short name T278
Test name
Test status
Simulation time 88012200 ps
CPU time 13.76 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:11 PM PDT 24
Peak memory 264008 kb
Host smart-238e82a5-b4e1-4aff-8903-7af08ac62d6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095861233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.3095861233
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1518761262
Short name T1114
Test name
Test status
Simulation time 30950300 ps
CPU time 13.41 seconds
Started May 23 01:20:19 PM PDT 24
Finished May 23 01:20:34 PM PDT 24
Peak memory 262740 kb
Host smart-6d28f654-80ba-40f9-8c0d-2159434ad79b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518761262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.1518761262
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2950718566
Short name T1144
Test name
Test status
Simulation time 306025900 ps
CPU time 17.8 seconds
Started May 23 01:20:02 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 260500 kb
Host smart-42978e02-e573-4821-8e92-f1417da7b6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950718566 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.2950718566
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1882701166
Short name T1109
Test name
Test status
Simulation time 48381500 ps
CPU time 16.11 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 260364 kb
Host smart-60bb4f1e-eb49-4a35-9951-2c5db0b176d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882701166 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.1882701166
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1114301
Short name T1191
Test name
Test status
Simulation time 12019300 ps
CPU time 15.48 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260312 kb
Host smart-13e72d95-46b1-44c0-8a5a-c066c1f52919
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114301 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1114301
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2471350973
Short name T1194
Test name
Test status
Simulation time 162224400 ps
CPU time 16.41 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:18 PM PDT 24
Peak memory 264116 kb
Host smart-6ebdd9e6-b0f9-4b63-83ab-d9d1915b87ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471350973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
471350973
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.663115940
Short name T346
Test name
Test status
Simulation time 29122500 ps
CPU time 13.48 seconds
Started May 23 01:20:20 PM PDT 24
Finished May 23 01:20:35 PM PDT 24
Peak memory 262832 kb
Host smart-bf5589f7-2b86-4376-a677-77de06674813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663115940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.663115940
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1742650832
Short name T1145
Test name
Test status
Simulation time 58190000 ps
CPU time 13.99 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:23 PM PDT 24
Peak memory 262472 kb
Host smart-a8ccdffc-9773-49d9-a1fb-ce18d4837d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742650832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
1742650832
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3810409216
Short name T343
Test name
Test status
Simulation time 16849400 ps
CPU time 13.41 seconds
Started May 23 01:20:18 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 262448 kb
Host smart-ca1cd66d-2ef6-4f34-a76e-ece11c5979f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810409216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3810409216
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.192273456
Short name T1162
Test name
Test status
Simulation time 16328200 ps
CPU time 13.42 seconds
Started May 23 01:20:23 PM PDT 24
Finished May 23 01:20:40 PM PDT 24
Peak memory 262448 kb
Host smart-04913927-4831-4064-9651-6b00c66d4853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192273456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.192273456
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4294591903
Short name T1230
Test name
Test status
Simulation time 65701200 ps
CPU time 13.51 seconds
Started May 23 01:20:13 PM PDT 24
Finished May 23 01:20:28 PM PDT 24
Peak memory 262832 kb
Host smart-119b0f65-4f5f-483b-831b-1d19e5e7ba89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294591903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
4294591903
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2215957027
Short name T1130
Test name
Test status
Simulation time 37434900 ps
CPU time 13.2 seconds
Started May 23 01:20:24 PM PDT 24
Finished May 23 01:20:41 PM PDT 24
Peak memory 262660 kb
Host smart-0497f065-d9d9-4a89-9114-09f2d5794554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215957027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2215957027
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3477792704
Short name T1174
Test name
Test status
Simulation time 18013000 ps
CPU time 13.45 seconds
Started May 23 01:20:25 PM PDT 24
Finished May 23 01:20:43 PM PDT 24
Peak memory 262444 kb
Host smart-7af4339f-87ff-4129-a7a6-b3370160337b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477792704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
3477792704
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1390818414
Short name T244
Test name
Test status
Simulation time 28870200 ps
CPU time 13.57 seconds
Started May 23 01:20:19 PM PDT 24
Finished May 23 01:20:34 PM PDT 24
Peak memory 262744 kb
Host smart-873af2f9-ca33-4e9e-a0f8-a05f3e4cc3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390818414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1390818414
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3305345965
Short name T1141
Test name
Test status
Simulation time 31178700 ps
CPU time 13.29 seconds
Started May 23 01:20:22 PM PDT 24
Finished May 23 01:20:38 PM PDT 24
Peak memory 262664 kb
Host smart-65d0916c-221a-4db5-a0e4-d979c8c08e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305345965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3305345965
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.866367941
Short name T1239
Test name
Test status
Simulation time 34020600 ps
CPU time 16.06 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:09 PM PDT 24
Peak memory 272344 kb
Host smart-bc51993b-b130-4647-8729-b585438c2fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866367941 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.866367941
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4227562466
Short name T1161
Test name
Test status
Simulation time 90612500 ps
CPU time 16.26 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:11 PM PDT 24
Peak memory 260280 kb
Host smart-566dc818-51d3-4e73-8151-dcd392537f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227562466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.4227562466
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3571704767
Short name T1148
Test name
Test status
Simulation time 93693800 ps
CPU time 13.63 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 262776 kb
Host smart-17c7a00f-965a-42fa-b787-48538ac20be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571704767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3
571704767
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1992650398
Short name T1177
Test name
Test status
Simulation time 66905200 ps
CPU time 19.66 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260352 kb
Host smart-c332687b-c42a-4bc8-a973-1a8df99725e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992650398 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1992650398
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3311283068
Short name T1115
Test name
Test status
Simulation time 26228000 ps
CPU time 15.82 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 260576 kb
Host smart-863bf6bd-efdc-4a76-9a21-1c4d9dcda782
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311283068 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3311283068
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3571149186
Short name T1223
Test name
Test status
Simulation time 20400300 ps
CPU time 15.59 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260532 kb
Host smart-0817f66f-6ce4-42af-aa4d-6cb0a76ffbde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571149186 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3571149186
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2079107724
Short name T250
Test name
Test status
Simulation time 59339400 ps
CPU time 18.95 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:16 PM PDT 24
Peak memory 264116 kb
Host smart-49a87d6a-adfb-4e89-a9ff-b5250cae0845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079107724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
079107724
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4292432447
Short name T1167
Test name
Test status
Simulation time 292342200 ps
CPU time 16.53 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:14 PM PDT 24
Peak memory 272300 kb
Host smart-17166ff7-6d3d-41b1-bbcd-e1b00007043c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292432447 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.4292432447
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1573599851
Short name T1228
Test name
Test status
Simulation time 32785500 ps
CPU time 17.08 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260552 kb
Host smart-a781606d-02b6-4f9d-8133-bda5e4730f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573599851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1573599851
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1416544465
Short name T338
Test name
Test status
Simulation time 16576200 ps
CPU time 13.73 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 262672 kb
Host smart-38bd756a-9f23-4fcf-9ea6-1b838e546ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416544465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
416544465
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1425441982
Short name T1199
Test name
Test status
Simulation time 233486000 ps
CPU time 29.52 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 260572 kb
Host smart-e1de4393-e985-44fb-877f-5e51e783053d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425441982 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1425441982
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.910908020
Short name T1121
Test name
Test status
Simulation time 15935300 ps
CPU time 15.6 seconds
Started May 23 01:19:48 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 260464 kb
Host smart-6cd61dee-5b16-4d9c-8f0f-4dc5ca1ee128
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910908020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.910908020
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3218659649
Short name T1224
Test name
Test status
Simulation time 37302000 ps
CPU time 15.28 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:08 PM PDT 24
Peak memory 260504 kb
Host smart-6265f170-42b3-4d32-a275-374476273e3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218659649 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3218659649
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.387669432
Short name T358
Test name
Test status
Simulation time 357422800 ps
CPU time 902.22 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:34:52 PM PDT 24
Peak memory 264092 kb
Host smart-d4b40a42-ea2c-48b9-a875-93813caf6650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387669432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.387669432
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2102252361
Short name T1165
Test name
Test status
Simulation time 453719500 ps
CPU time 18.57 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 271468 kb
Host smart-93523e9f-e62c-480d-8915-b0601a3a21ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102252361 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2102252361
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2855450956
Short name T1153
Test name
Test status
Simulation time 43469100 ps
CPU time 17.3 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 260456 kb
Host smart-76c882aa-8c97-459b-90f7-d9307cb6bd2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855450956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2855450956
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3073508301
Short name T1216
Test name
Test status
Simulation time 103498100 ps
CPU time 13.39 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 261184 kb
Host smart-242f68db-cd2f-4923-8f69-357e32022c88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073508301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
073508301
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1445708489
Short name T307
Test name
Test status
Simulation time 205955800 ps
CPU time 30.55 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260400 kb
Host smart-0ea6dc29-32fc-49f0-bed1-a6249fd2a930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445708489 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1445708489
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3916857972
Short name T1134
Test name
Test status
Simulation time 13580100 ps
CPU time 15.73 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:10 PM PDT 24
Peak memory 260508 kb
Host smart-34e332d1-a1a8-4ca1-b311-af4b3e0d9229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916857972 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.3916857972
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4127490954
Short name T1131
Test name
Test status
Simulation time 48324000 ps
CPU time 13.02 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:20:03 PM PDT 24
Peak memory 260448 kb
Host smart-2668b3b1-8faa-44a6-a23b-bfebcf429fc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127490954 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.4127490954
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2747630217
Short name T1201
Test name
Test status
Simulation time 46135100 ps
CPU time 18.18 seconds
Started May 23 01:20:00 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 264148 kb
Host smart-a8f3fb6d-95b1-4847-9c44-99c627edc4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747630217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
747630217
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1944681582
Short name T360
Test name
Test status
Simulation time 986581000 ps
CPU time 468 seconds
Started May 23 01:19:44 PM PDT 24
Finished May 23 01:27:34 PM PDT 24
Peak memory 261756 kb
Host smart-4937d98f-e8cc-4885-9635-25d32234536d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944681582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1944681582
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3183920012
Short name T300
Test name
Test status
Simulation time 119021100 ps
CPU time 17.31 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 271292 kb
Host smart-9a55f984-c717-426a-98f2-d6bf1c2c3f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183920012 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3183920012
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3677510902
Short name T1196
Test name
Test status
Simulation time 19436000 ps
CPU time 16.21 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 260244 kb
Host smart-50a059a1-1069-4940-ab60-238b73744939
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677510902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3677510902
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3369544528
Short name T1218
Test name
Test status
Simulation time 23122400 ps
CPU time 13.46 seconds
Started May 23 01:20:00 PM PDT 24
Finished May 23 01:20:16 PM PDT 24
Peak memory 262516 kb
Host smart-795d57c7-dd77-45e3-9e41-f56f6eb82d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369544528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
369544528
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3850434845
Short name T1120
Test name
Test status
Simulation time 219264100 ps
CPU time 33.21 seconds
Started May 23 01:19:53 PM PDT 24
Finished May 23 01:20:33 PM PDT 24
Peak memory 263920 kb
Host smart-3d8adc45-4e2f-48b6-bb14-b4c8128e4bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850434845 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3850434845
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.591432194
Short name T1103
Test name
Test status
Simulation time 12806100 ps
CPU time 15.64 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 260360 kb
Host smart-c153d096-b516-4381-ac84-af47afec9c4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591432194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.591432194
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1481195805
Short name T1164
Test name
Test status
Simulation time 50086200 ps
CPU time 13.23 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 260352 kb
Host smart-3c22e265-70da-4969-a4d3-cd112f640f80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481195805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1481195805
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1742033221
Short name T187
Test name
Test status
Simulation time 154855200 ps
CPU time 16.37 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:24 PM PDT 24
Peak memory 264152 kb
Host smart-0de52c52-8100-4c90-835b-14cf0975587f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742033221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
742033221
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3529496611
Short name T1202
Test name
Test status
Simulation time 103314700 ps
CPU time 18.31 seconds
Started May 23 01:19:56 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 272284 kb
Host smart-5b279b87-ea2d-447d-b81c-ca554ebef1ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529496611 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3529496611
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.226240567
Short name T284
Test name
Test status
Simulation time 52070100 ps
CPU time 16.9 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:21 PM PDT 24
Peak memory 260448 kb
Host smart-85c79c5b-dc4a-40fd-a937-0ad124cc1833
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226240567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.226240567
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1666423591
Short name T345
Test name
Test status
Simulation time 57313100 ps
CPU time 13.36 seconds
Started May 23 01:20:04 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 262652 kb
Host smart-a442e468-7252-465f-95e5-a041bdad8c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666423591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
666423591
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3275938721
Short name T301
Test name
Test status
Simulation time 179044500 ps
CPU time 15.86 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 262036 kb
Host smart-960fb7df-fbde-49c1-bbb9-b050a41244ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275938721 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3275938721
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1474932414
Short name T1138
Test name
Test status
Simulation time 15059800 ps
CPU time 15.18 seconds
Started May 23 01:20:19 PM PDT 24
Finished May 23 01:20:36 PM PDT 24
Peak memory 260552 kb
Host smart-64ea0b01-164d-4603-9617-7b65bcc10dcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474932414 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1474932414
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3398134083
Short name T1097
Test name
Test status
Simulation time 47072400 ps
CPU time 15.77 seconds
Started May 23 01:20:15 PM PDT 24
Finished May 23 01:20:32 PM PDT 24
Peak memory 260516 kb
Host smart-b540c92c-8260-48b0-a428-1de71e825c1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398134083 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3398134083
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1737848623
Short name T246
Test name
Test status
Simulation time 40893000 ps
CPU time 16.47 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:20:13 PM PDT 24
Peak memory 264248 kb
Host smart-f3bcbaef-9adb-4a22-bedd-b3547d00133c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737848623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
737848623
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3174952676
Short name T236
Test name
Test status
Simulation time 181626200 ps
CPU time 454.66 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:27:38 PM PDT 24
Peak memory 263844 kb
Host smart-8f7b00e9-f2c7-45bc-aa30-07d89ee03841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174952676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3174952676
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2864756632
Short name T480
Test name
Test status
Simulation time 172695900 ps
CPU time 13.82 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 265136 kb
Host smart-abd5d1d2-c85a-48ea-ad98-597d380bb2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864756632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
864756632
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.908508463
Short name T1095
Test name
Test status
Simulation time 15369000 ps
CPU time 16.34 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 275112 kb
Host smart-fbb9c53a-9457-4f79-80a2-ea44047a5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908508463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.908508463
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1873721694
Short name T168
Test name
Test status
Simulation time 123077000 ps
CPU time 101.92 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:29:20 PM PDT 24
Peak memory 272408 kb
Host smart-871c948f-6cea-4199-b59c-918314fb1e20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873721694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.1873721694
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3038759104
Short name T172
Test name
Test status
Simulation time 1539376500 ps
CPU time 298.17 seconds
Started May 23 01:27:21 PM PDT 24
Finished May 23 01:32:20 PM PDT 24
Peak memory 261288 kb
Host smart-a72fd2e1-501c-45b6-84ae-5679ab76c048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038759104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3038759104
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1581644011
Short name T179
Test name
Test status
Simulation time 2193034400 ps
CPU time 2481.57 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 02:08:53 PM PDT 24
Peak memory 265048 kb
Host smart-a4c3d5b0-aef5-42ac-a437-28f668316890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581644011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1581644011
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.131042612
Short name T827
Test name
Test status
Simulation time 995531100 ps
CPU time 27.96 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:27:56 PM PDT 24
Peak memory 261976 kb
Host smart-f93611a7-6d5a-4076-ae20-521100dd5516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131042612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.131042612
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1915601282
Short name T115
Test name
Test status
Simulation time 193788713700 ps
CPU time 2515.24 seconds
Started May 23 01:27:18 PM PDT 24
Finished May 23 02:09:16 PM PDT 24
Peak memory 264884 kb
Host smart-9556d403-204e-4d87-a63a-be71f9b22343
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915601282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1915601282
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1181299783
Short name T160
Test name
Test status
Simulation time 379541084600 ps
CPU time 2438.34 seconds
Started May 23 01:27:18 PM PDT 24
Finished May 23 02:07:59 PM PDT 24
Peak memory 265212 kb
Host smart-c203da24-385b-4aee-b590-1ece8c0612be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181299783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1181299783
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1085131678
Short name T741
Test name
Test status
Simulation time 24303200 ps
CPU time 37.33 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:28:04 PM PDT 24
Peak memory 262592 kb
Host smart-86e2d8bf-ff0a-4f5c-b6ee-7ec5b8324e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085131678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1085131678
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1130998816
Short name T68
Test name
Test status
Simulation time 340423542600 ps
CPU time 1804.24 seconds
Started May 23 01:27:20 PM PDT 24
Finished May 23 01:57:26 PM PDT 24
Peak memory 263348 kb
Host smart-f6771395-bf16-4fe9-8296-209def53704f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130998816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1130998816
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1752062757
Short name T159
Test name
Test status
Simulation time 320255790100 ps
CPU time 886.53 seconds
Started May 23 01:27:16 PM PDT 24
Finished May 23 01:42:05 PM PDT 24
Peak memory 264420 kb
Host smart-0f7cfad0-0027-403a-a472-1367304ce36b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752062757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1752062757
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2819849606
Short name T1064
Test name
Test status
Simulation time 3957670700 ps
CPU time 93.4 seconds
Started May 23 01:27:16 PM PDT 24
Finished May 23 01:28:53 PM PDT 24
Peak memory 262480 kb
Host smart-c56c90ca-96ee-4e05-a610-2c4bb23e123e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819849606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2819849606
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.1698611336
Short name T974
Test name
Test status
Simulation time 2441848300 ps
CPU time 133.99 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:29:46 PM PDT 24
Peak memory 293172 kb
Host smart-55e37754-c7f0-4970-aa84-550c44b9c849
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698611336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.1698611336
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3702104840
Short name T778
Test name
Test status
Simulation time 5881960800 ps
CPU time 159.27 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:30:08 PM PDT 24
Peak memory 291992 kb
Host smart-64dcbdf3-8d7b-428d-b030-a85e95729fb7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702104840 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3702104840
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2720431112
Short name T971
Test name
Test status
Simulation time 8334034900 ps
CPU time 65.21 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:28:39 PM PDT 24
Peak memory 259916 kb
Host smart-797ce76c-1441-418e-822b-7ced8d4d5f17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720431112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2720431112
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.496102216
Short name T621
Test name
Test status
Simulation time 23890939400 ps
CPU time 189.53 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 260252 kb
Host smart-bf93b933-3d38-4a14-8603-b23331aaf2c9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496
102216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.496102216
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3566764432
Short name T106
Test name
Test status
Simulation time 5529915100 ps
CPU time 446.22 seconds
Started May 23 01:27:16 PM PDT 24
Finished May 23 01:34:46 PM PDT 24
Peak memory 273300 kb
Host smart-52861583-b5c8-48ed-b899-07643895a26d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566764432 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3566764432
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2597344810
Short name T588
Test name
Test status
Simulation time 301165400 ps
CPU time 133.58 seconds
Started May 23 01:27:28 PM PDT 24
Finished May 23 01:29:43 PM PDT 24
Peak memory 260996 kb
Host smart-d617ee48-81bf-4e12-8f5f-d5b4db1e8d1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597344810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2597344810
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2653258225
Short name T60
Test name
Test status
Simulation time 16367800 ps
CPU time 14.16 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:27:45 PM PDT 24
Peak memory 276968 kb
Host smart-24e1e38d-18b9-4656-b6d8-535215622900
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2653258225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2653258225
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3381935995
Short name T682
Test name
Test status
Simulation time 395909300 ps
CPU time 444.16 seconds
Started May 23 01:27:17 PM PDT 24
Finished May 23 01:34:44 PM PDT 24
Peak memory 262500 kb
Host smart-1b3bae0b-b647-4adb-ac84-59d1bc57ce2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381935995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3381935995
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.185610972
Short name T524
Test name
Test status
Simulation time 18333100 ps
CPU time 13.92 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:27:48 PM PDT 24
Peak memory 264780 kb
Host smart-460f9196-4022-4e96-afab-4c81acf39619
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185610972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_rese
t.185610972
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3278696909
Short name T758
Test name
Test status
Simulation time 300836300 ps
CPU time 685.63 seconds
Started May 23 01:27:13 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 283184 kb
Host smart-3ffed928-e441-4c69-9fc8-9d4e5cf85c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278696909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3278696909
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2407214097
Short name T610
Test name
Test status
Simulation time 718409700 ps
CPU time 149.57 seconds
Started May 23 01:27:17 PM PDT 24
Finished May 23 01:29:49 PM PDT 24
Peak memory 265124 kb
Host smart-2afda899-c2cb-4142-85cd-badb9738a647
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407214097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2407214097
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.4194149793
Short name T1061
Test name
Test status
Simulation time 453900500 ps
CPU time 32.59 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:28:04 PM PDT 24
Peak memory 276052 kb
Host smart-5bb8623a-49ef-4a0f-ac1e-e5b4620649a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194149793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.4194149793
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3192118570
Short name T833
Test name
Test status
Simulation time 220363000 ps
CPU time 46.09 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 273720 kb
Host smart-a3b9e59d-bc66-45f8-9bdb-4a886e19f566
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192118570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3192118570
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2793012287
Short name T316
Test name
Test status
Simulation time 90041900 ps
CPU time 35.99 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:28:02 PM PDT 24
Peak memory 273448 kb
Host smart-60d842b6-d6e3-4aa7-ad30-7e603c3f219c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793012287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2793012287
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1849675062
Short name T1006
Test name
Test status
Simulation time 74149500 ps
CPU time 14.04 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:27:42 PM PDT 24
Peak memory 265064 kb
Host smart-c7831039-0133-4896-83a8-96cd82442f04
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1849675062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1849675062
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1250866576
Short name T1007
Test name
Test status
Simulation time 21644200 ps
CPU time 23.12 seconds
Started May 23 01:27:17 PM PDT 24
Finished May 23 01:27:43 PM PDT 24
Peak memory 265156 kb
Host smart-9d9470f7-59c0-4fcd-9f99-11a02b5ed916
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250866576 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1250866576
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3427367463
Short name T451
Test name
Test status
Simulation time 73483200 ps
CPU time 22.56 seconds
Started May 23 01:27:18 PM PDT 24
Finished May 23 01:27:43 PM PDT 24
Peak memory 264872 kb
Host smart-06727247-d34e-4dbb-8abd-1c197f5dd992
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427367463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3427367463
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.3830402528
Short name T137
Test name
Test status
Simulation time 78638392700 ps
CPU time 1324.36 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:49:33 PM PDT 24
Peak memory 496996 kb
Host smart-9fd49796-2f63-49cb-a171-62b7a8ccae52
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830402528 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.3830402528
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.168518018
Short name T816
Test name
Test status
Simulation time 1124650700 ps
CPU time 120.34 seconds
Started May 23 01:27:21 PM PDT 24
Finished May 23 01:29:23 PM PDT 24
Peak memory 281636 kb
Host smart-42879edf-d86f-4355-8a88-c4b95e2c5af0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168518018 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_ro.168518018
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.2966421595
Short name T803
Test name
Test status
Simulation time 1072039800 ps
CPU time 141.46 seconds
Started May 23 01:27:24 PM PDT 24
Finished May 23 01:29:47 PM PDT 24
Peak memory 281744 kb
Host smart-e5574b23-9ff0-4f1f-979b-260bf7d7197b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2966421595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2966421595
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.1401535745
Short name T616
Test name
Test status
Simulation time 1325668000 ps
CPU time 135.96 seconds
Started May 23 01:27:18 PM PDT 24
Finished May 23 01:29:37 PM PDT 24
Peak memory 294468 kb
Host smart-6d1a202b-49f0-47b9-abe2-8f3c8eeda6ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401535745 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.1401535745
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1422721503
Short name T775
Test name
Test status
Simulation time 8008811800 ps
CPU time 571.34 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 309428 kb
Host smart-aca987a1-2835-470d-8b5a-5a2d0f0c82a2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422721503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1422721503
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.2995025501
Short name T430
Test name
Test status
Simulation time 38286500 ps
CPU time 29 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:27:56 PM PDT 24
Peak memory 274628 kb
Host smart-c7efaf8d-4ef4-43e1-82cf-7616ac2ee5da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995025501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.2995025501
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1128001825
Short name T851
Test name
Test status
Simulation time 44819900 ps
CPU time 31.83 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:28:02 PM PDT 24
Peak memory 276012 kb
Host smart-67265ce9-7676-46b8-8195-52dd1c8525a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128001825 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1128001825
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.1315451410
Short name T801
Test name
Test status
Simulation time 17812595300 ps
CPU time 602.47 seconds
Started May 23 01:27:17 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 320220 kb
Host smart-bdbf49fc-b7ec-4689-9f72-0d190e304930
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315451410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.1315451410
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.1003972062
Short name T615
Test name
Test status
Simulation time 473229600 ps
CPU time 61.35 seconds
Started May 23 01:27:16 PM PDT 24
Finished May 23 01:28:21 PM PDT 24
Peak memory 264928 kb
Host smart-601e451f-24a8-40fa-acc1-a9fddd334051
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003972062 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.1003972062
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.1288133054
Short name T551
Test name
Test status
Simulation time 622180100 ps
CPU time 69.33 seconds
Started May 23 01:27:13 PM PDT 24
Finished May 23 01:28:24 PM PDT 24
Peak memory 273432 kb
Host smart-89994022-7339-44c8-afe2-19434fdc9165
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288133054 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.1288133054
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3271442008
Short name T375
Test name
Test status
Simulation time 160563100 ps
CPU time 96.09 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:29:02 PM PDT 24
Peak memory 275356 kb
Host smart-d66547e6-01dd-4532-a67a-084bb95ae8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271442008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3271442008
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.437336857
Short name T222
Test name
Test status
Simulation time 20700900 ps
CPU time 26.28 seconds
Started May 23 01:27:22 PM PDT 24
Finished May 23 01:27:50 PM PDT 24
Peak memory 259056 kb
Host smart-271df8e8-a2e2-4a6f-8a3a-f857d330ec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437336857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.437336857
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2633662978
Short name T1002
Test name
Test status
Simulation time 810907700 ps
CPU time 815.6 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:41:07 PM PDT 24
Peak memory 283524 kb
Host smart-afdcf57c-b0a3-4fcf-90f1-b49486ecbfcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633662978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2633662978
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.257614626
Short name T861
Test name
Test status
Simulation time 35481400 ps
CPU time 26.56 seconds
Started May 23 01:27:24 PM PDT 24
Finished May 23 01:27:52 PM PDT 24
Peak memory 261856 kb
Host smart-e3b7c4b2-5271-4133-8b2f-9016e60312d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257614626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.257614626
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.3992478635
Short name T979
Test name
Test status
Simulation time 4598688100 ps
CPU time 163.77 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:30:10 PM PDT 24
Peak memory 265108 kb
Host smart-9b448f70-12e5-4fd4-b0db-936c9724ced8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992478635 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.3992478635
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2835932721
Short name T713
Test name
Test status
Simulation time 136791700 ps
CPU time 15.18 seconds
Started May 23 01:27:18 PM PDT 24
Finished May 23 01:27:36 PM PDT 24
Peak memory 264736 kb
Host smart-828efe9e-0508-4713-a423-189b6f4ec239
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2835932721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2835932721
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3682197341
Short name T49
Test name
Test status
Simulation time 13636400 ps
CPU time 13.67 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:27:44 PM PDT 24
Peak memory 265212 kb
Host smart-ffc84a30-bded-4a86-a268-e046f42c7d33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682197341 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3682197341
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2983886061
Short name T436
Test name
Test status
Simulation time 21390700 ps
CPU time 13.66 seconds
Started May 23 01:27:43 PM PDT 24
Finished May 23 01:27:57 PM PDT 24
Peak memory 265164 kb
Host smart-05d0d5fe-6d1e-4e7b-bf2e-f6e16d1f9fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983886061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
983886061
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3314662565
Short name T810
Test name
Test status
Simulation time 42012500 ps
CPU time 16.03 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:27:48 PM PDT 24
Peak memory 275788 kb
Host smart-2796c911-d255-41f4-8f7d-5b9722a8c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314662565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3314662565
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1936301242
Short name T786
Test name
Test status
Simulation time 139369300 ps
CPU time 102.92 seconds
Started May 23 01:27:37 PM PDT 24
Finished May 23 01:29:22 PM PDT 24
Peak memory 281616 kb
Host smart-3bf80586-b67b-4f98-852d-b3d37e57f271
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936301242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1936301242
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1267040847
Short name T167
Test name
Test status
Simulation time 3422976300 ps
CPU time 497.38 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:35:48 PM PDT 24
Peak memory 261404 kb
Host smart-6503bad6-f8a5-4a07-a003-a20a7d6035fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267040847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1267040847
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.4229222681
Short name T986
Test name
Test status
Simulation time 4541767100 ps
CPU time 2477.12 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 02:08:51 PM PDT 24
Peak memory 264188 kb
Host smart-a7c43584-6a86-4e5f-ad73-66140dc7ab00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229222681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.4229222681
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2611194329
Short name T997
Test name
Test status
Simulation time 599630700 ps
CPU time 1837.32 seconds
Started May 23 01:27:37 PM PDT 24
Finished May 23 01:58:16 PM PDT 24
Peak memory 265156 kb
Host smart-460abf8b-a8a0-4242-8525-3a158ff4e60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611194329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2611194329
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3859412047
Short name T828
Test name
Test status
Simulation time 1120639400 ps
CPU time 745.43 seconds
Started May 23 01:27:35 PM PDT 24
Finished May 23 01:40:01 PM PDT 24
Peak memory 265144 kb
Host smart-33c5fd28-8c15-401b-af49-26b4a553dbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859412047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3859412047
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2496898811
Short name T954
Test name
Test status
Simulation time 430638900 ps
CPU time 23.02 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:27:51 PM PDT 24
Peak memory 265084 kb
Host smart-57e43623-1f38-48ab-bbc2-3d6a1576c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496898811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2496898811
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2625520721
Short name T959
Test name
Test status
Simulation time 338955400 ps
CPU time 40.89 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:28:12 PM PDT 24
Peak memory 264284 kb
Host smart-581ef09d-672f-4070-bc4a-af93e61768dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625520721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2625520721
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.216672841
Short name T112
Test name
Test status
Simulation time 49893090500 ps
CPU time 3648.07 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 02:28:26 PM PDT 24
Peak memory 276044 kb
Host smart-0deb82a3-3b29-4032-a849-ef910e49bd19
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216672841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_full_mem_access.216672841
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.4092343035
Short name T714
Test name
Test status
Simulation time 40367600 ps
CPU time 57.05 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:28:30 PM PDT 24
Peak memory 265112 kb
Host smart-02760b9f-350f-4efe-b3e4-59823e300a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092343035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4092343035
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2516011338
Short name T563
Test name
Test status
Simulation time 15158100 ps
CPU time 13.47 seconds
Started May 23 01:27:52 PM PDT 24
Finished May 23 01:28:07 PM PDT 24
Peak memory 265352 kb
Host smart-ad42a364-0f2f-4619-8aa4-e9e23b780c3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516011338 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2516011338
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1593001593
Short name T510
Test name
Test status
Simulation time 340570075400 ps
CPU time 1869.21 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:58:42 PM PDT 24
Peak memory 263880 kb
Host smart-031a2776-9f4d-457b-98e1-1d640af90874
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593001593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1593001593
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2174457623
Short name T158
Test name
Test status
Simulation time 540433408200 ps
CPU time 974.74 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 264264 kb
Host smart-dfe13459-eaad-4390-9c87-0ccceeebbc81
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174457623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2174457623
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3329604217
Short name T309
Test name
Test status
Simulation time 8016770800 ps
CPU time 146.57 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:29:58 PM PDT 24
Peak memory 262480 kb
Host smart-d767a263-8803-40b5-bea3-c1f4c4248697
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329604217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.3329604217
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.2320831210
Short name T281
Test name
Test status
Simulation time 3774824200 ps
CPU time 682.18 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 312836 kb
Host smart-2aed4589-eb38-4441-ae57-615f721f9ad1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320831210 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.2320831210
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.3689931590
Short name T32
Test name
Test status
Simulation time 2106693300 ps
CPU time 218.79 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:31:07 PM PDT 24
Peak memory 291600 kb
Host smart-f4dcbd68-a7fc-4aa4-bb68-729e23afd4e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689931590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.3689931590
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2469374728
Short name T961
Test name
Test status
Simulation time 37456859900 ps
CPU time 314.17 seconds
Started May 23 01:27:41 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 292048 kb
Host smart-8d2a5e88-8e06-461d-a078-9327667d227b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469374728 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2469374728
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.3373924409
Short name T963
Test name
Test status
Simulation time 1971601500 ps
CPU time 65.49 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 01:28:43 PM PDT 24
Peak memory 259776 kb
Host smart-7b92a71e-a2cf-496f-85bd-5ab8f3315f43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373924409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.3373924409
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1831421741
Short name T700
Test name
Test status
Simulation time 176603929500 ps
CPU time 323.93 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:32:52 PM PDT 24
Peak memory 260140 kb
Host smart-ffe7b797-15f3-4e60-9298-e7c9c9fcfcee
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183
1421741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1831421741
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.49205401
Short name T639
Test name
Test status
Simulation time 6859569200 ps
CPU time 66.42 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:28:34 PM PDT 24
Peak memory 260588 kb
Host smart-17e6d6b2-3d77-4890-8862-3506f7b0cbe4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49205401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.49205401
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1097641957
Short name T478
Test name
Test status
Simulation time 25809600 ps
CPU time 13.4 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:02 PM PDT 24
Peak memory 265200 kb
Host smart-cacdb892-2f82-4a1b-94d4-263bfba6ce55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097641957 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1097641957
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.3520993812
Short name T164
Test name
Test status
Simulation time 992453400 ps
CPU time 68.25 seconds
Started May 23 01:27:33 PM PDT 24
Finished May 23 01:28:42 PM PDT 24
Peak memory 259828 kb
Host smart-a3952d9f-3bf4-4bf9-8ff7-d57541980303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520993812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3520993812
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3791011384
Short name T113
Test name
Test status
Simulation time 10923324800 ps
CPU time 268.48 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:32:02 PM PDT 24
Peak memory 274444 kb
Host smart-af14bbc5-8753-43a8-8e3b-03d869c00e7d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791011384 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.3791011384
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3536242018
Short name T821
Test name
Test status
Simulation time 73101600 ps
CPU time 132.34 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:29:44 PM PDT 24
Peak memory 259576 kb
Host smart-abef0510-3185-42eb-a78b-5d9082a6bfec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536242018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3536242018
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3723471939
Short name T854
Test name
Test status
Simulation time 2787089500 ps
CPU time 196.65 seconds
Started May 23 01:27:41 PM PDT 24
Finished May 23 01:30:59 PM PDT 24
Peak memory 281736 kb
Host smart-0ba21a40-6f6b-4266-9731-943b08c655c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723471939 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3723471939
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2875897670
Short name T1093
Test name
Test status
Simulation time 61806000 ps
CPU time 234.52 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:31:27 PM PDT 24
Peak memory 262348 kb
Host smart-cec6a9f2-d927-4a58-a65e-67d8c9ab07d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875897670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2875897670
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2634837516
Short name T10
Test name
Test status
Simulation time 24049900 ps
CPU time 13.59 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 01:28:04 PM PDT 24
Peak memory 265388 kb
Host smart-ad83ee69-f472-4dea-a755-49058e5fadb7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634837516 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2634837516
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.748819638
Short name T659
Test name
Test status
Simulation time 19107300 ps
CPU time 13.23 seconds
Started May 23 01:27:40 PM PDT 24
Finished May 23 01:27:54 PM PDT 24
Peak memory 265192 kb
Host smart-316723fc-30de-4b41-8132-c0e4813b9313
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748819638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_rese
t.748819638
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.4030989513
Short name T685
Test name
Test status
Simulation time 329642800 ps
CPU time 1257.61 seconds
Started May 23 01:27:25 PM PDT 24
Finished May 23 01:48:24 PM PDT 24
Peak memory 286948 kb
Host smart-a9a84250-3c5c-4258-ad9d-4edfa89b1bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030989513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.4030989513
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.1970692259
Short name T802
Test name
Test status
Simulation time 2714036900 ps
CPU time 184.09 seconds
Started May 23 01:27:32 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 265044 kb
Host smart-e9a1a857-b898-4116-bff3-b90729fa9b67
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1970692259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.1970692259
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2375128158
Short name T92
Test name
Test status
Simulation time 297796300 ps
CPU time 32.54 seconds
Started May 23 01:27:28 PM PDT 24
Finished May 23 01:28:01 PM PDT 24
Peak memory 276144 kb
Host smart-f56e3a81-d817-4c05-a1e8-075864133315
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375128158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2375128158
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2147494414
Short name T432
Test name
Test status
Simulation time 107284500 ps
CPU time 38.21 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:28:09 PM PDT 24
Peak memory 274512 kb
Host smart-120ac203-f8a8-4a0f-b863-948c3dea806c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147494414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2147494414
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.189713897
Short name T313
Test name
Test status
Simulation time 69893100 ps
CPU time 22.68 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:27:54 PM PDT 24
Peak memory 264624 kb
Host smart-f02d6958-a6c8-454c-9974-af98fcd5c7fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189713897 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.189713897
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.968991721
Short name T729
Test name
Test status
Simulation time 46306800 ps
CPU time 22.29 seconds
Started May 23 01:27:31 PM PDT 24
Finished May 23 01:27:55 PM PDT 24
Peak memory 265228 kb
Host smart-2749ff1b-26fc-40a7-bed0-3412366e7316
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968991721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.968991721
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2444173665
Short name T151
Test name
Test status
Simulation time 41106546300 ps
CPU time 904.45 seconds
Started May 23 01:27:56 PM PDT 24
Finished May 23 01:43:01 PM PDT 24
Peak memory 259356 kb
Host smart-d4fe00c2-da49-4978-b8be-35b5d3778409
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444173665 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2444173665
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.3363445753
Short name T86
Test name
Test status
Simulation time 772178100 ps
CPU time 117.59 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:29:29 PM PDT 24
Peak memory 281584 kb
Host smart-a7b0900e-f4b8-4d3f-ae57-8c4bafec1fc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3363445753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3363445753
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2331228260
Short name T36
Test name
Test status
Simulation time 1728032900 ps
CPU time 106.01 seconds
Started May 23 01:27:26 PM PDT 24
Finished May 23 01:29:13 PM PDT 24
Peak memory 294384 kb
Host smart-5053b2d6-5991-4a8d-a558-fbbba94a5d69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331228260 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2331228260
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.2958916457
Short name T329
Test name
Test status
Simulation time 66347200 ps
CPU time 28.33 seconds
Started May 23 01:27:38 PM PDT 24
Finished May 23 01:28:08 PM PDT 24
Peak memory 273556 kb
Host smart-ed1d9d5d-9f73-4c93-8f77-901ab9792e05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958916457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.2958916457
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2698051720
Short name T505
Test name
Test status
Simulation time 77161500 ps
CPU time 31.35 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:28:18 PM PDT 24
Peak memory 274784 kb
Host smart-5b57e08d-b7ef-41b6-9fc6-3da94a3285d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698051720 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2698051720
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.4099617289
Short name T205
Test name
Test status
Simulation time 4973964300 ps
CPU time 628.52 seconds
Started May 23 01:27:38 PM PDT 24
Finished May 23 01:38:08 PM PDT 24
Peak memory 320196 kb
Host smart-95ca7cee-aeb4-4cf7-b8d1-16466912d0d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099617289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.4099617289
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3190201745
Short name T230
Test name
Test status
Simulation time 1514898800 ps
CPU time 53.3 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 01:28:31 PM PDT 24
Peak memory 263164 kb
Host smart-fe70e4ca-ae14-449d-8f60-bf0938af9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190201745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3190201745
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.768718625
Short name T538
Test name
Test status
Simulation time 1016225900 ps
CPU time 108.83 seconds
Started May 23 01:27:29 PM PDT 24
Finished May 23 01:29:19 PM PDT 24
Peak memory 265200 kb
Host smart-1eb5fea9-1189-4145-b326-e6cb248f4267
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768718625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_address.768718625
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.484444419
Short name T787
Test name
Test status
Simulation time 577097700 ps
CPU time 58.84 seconds
Started May 23 01:27:36 PM PDT 24
Finished May 23 01:28:36 PM PDT 24
Peak memory 273556 kb
Host smart-8d013ab6-715b-432a-a805-635aeb0b2c80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484444419 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_counter.484444419
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3709467367
Short name T200
Test name
Test status
Simulation time 22539200 ps
CPU time 51.68 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:28:23 PM PDT 24
Peak memory 270604 kb
Host smart-04e446cb-1920-403d-9026-57d1f90e18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709467367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3709467367
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2555887771
Short name T759
Test name
Test status
Simulation time 50462500 ps
CPU time 25.3 seconds
Started May 23 01:27:40 PM PDT 24
Finished May 23 01:28:06 PM PDT 24
Peak memory 259084 kb
Host smart-963fd5fb-2692-42ab-8215-f5c0230fa467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555887771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2555887771
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.2634781229
Short name T61
Test name
Test status
Simulation time 628210000 ps
CPU time 746.9 seconds
Started May 23 01:27:27 PM PDT 24
Finished May 23 01:39:55 PM PDT 24
Peak memory 289784 kb
Host smart-f2f1cfd7-eaf2-41df-aeea-e918b3f3d662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634781229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.2634781229
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.1130036541
Short name T427
Test name
Test status
Simulation time 83661300 ps
CPU time 26.66 seconds
Started May 23 01:27:30 PM PDT 24
Finished May 23 01:27:58 PM PDT 24
Peak memory 259008 kb
Host smart-dc6bb981-e8eb-489f-a8d1-1d0dbd258ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130036541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1130036541
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.4196754928
Short name T953
Test name
Test status
Simulation time 27862976400 ps
CPU time 195.54 seconds
Started May 23 01:27:41 PM PDT 24
Finished May 23 01:30:57 PM PDT 24
Peak memory 259464 kb
Host smart-28ad13eb-3ede-4987-b07c-e90f5bd0a787
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196754928 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.4196754928
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.2593539970
Short name T464
Test name
Test status
Simulation time 136686900 ps
CPU time 14.52 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:24 PM PDT 24
Peak memory 258184 kb
Host smart-2bde65b1-b883-4400-a088-d3ff5c91d3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593539970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
2593539970
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1349399448
Short name T488
Test name
Test status
Simulation time 159590500 ps
CPU time 15.95 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:29:25 PM PDT 24
Peak memory 275104 kb
Host smart-e2d02e78-cc85-4345-a036-43a488e455fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349399448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1349399448
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.756791727
Short name T45
Test name
Test status
Simulation time 29880600 ps
CPU time 22.3 seconds
Started May 23 01:29:11 PM PDT 24
Finished May 23 01:29:35 PM PDT 24
Peak memory 273556 kb
Host smart-6eb0c416-d1cf-42a8-80a1-295f2c06cf8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756791727 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.756791727
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.230813377
Short name T794
Test name
Test status
Simulation time 10094793600 ps
CPU time 43.58 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:29:53 PM PDT 24
Peak memory 265824 kb
Host smart-232ef0ae-d5e8-48da-a801-a641bfcd8751
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230813377 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.230813377
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1122711724
Short name T1033
Test name
Test status
Simulation time 26940800 ps
CPU time 13.33 seconds
Started May 23 01:29:12 PM PDT 24
Finished May 23 01:29:27 PM PDT 24
Peak memory 265112 kb
Host smart-9a4270b7-ca42-45d4-aa49-437b6c773b70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122711724 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1122711724
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3269745116
Short name T903
Test name
Test status
Simulation time 260240692500 ps
CPU time 920.85 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:44:29 PM PDT 24
Peak memory 263272 kb
Host smart-c93981db-47ba-4728-92ec-1ad7bb176304
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269745116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3269745116
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2197976604
Short name T888
Test name
Test status
Simulation time 4018309700 ps
CPU time 96.24 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:30:44 PM PDT 24
Peak memory 262584 kb
Host smart-38104cb9-ac3e-4d6a-83df-59b8d3904acf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197976604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2197976604
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2651053110
Short name T581
Test name
Test status
Simulation time 28570739600 ps
CPU time 154.88 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:31:43 PM PDT 24
Peak memory 292300 kb
Host smart-9862a8cd-0f10-484f-a3ed-9936b8d5ddaf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651053110 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2651053110
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.4258660031
Short name T814
Test name
Test status
Simulation time 1704832200 ps
CPU time 62.25 seconds
Started May 23 01:29:12 PM PDT 24
Finished May 23 01:30:16 PM PDT 24
Peak memory 260752 kb
Host smart-1d8496ca-8b49-432d-9b01-bc9a1dfc285c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258660031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.4
258660031
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.2508400207
Short name T109
Test name
Test status
Simulation time 114236157500 ps
CPU time 569.43 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 274324 kb
Host smart-258eda13-99cb-4d08-beba-8a785474232f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508400207 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.2508400207
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.4151786647
Short name T515
Test name
Test status
Simulation time 73068600 ps
CPU time 110.27 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:31:01 PM PDT 24
Peak memory 259808 kb
Host smart-e6686bd8-6715-43b6-9ffc-d6c92de3b482
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151786647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.4151786647
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.1437464996
Short name T1073
Test name
Test status
Simulation time 67332200 ps
CPU time 320.57 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:34:30 PM PDT 24
Peak memory 265208 kb
Host smart-c143141c-be8c-4f54-9c41-772392c0dc33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437464996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1437464996
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.1737675965
Short name T1084
Test name
Test status
Simulation time 48710400 ps
CPU time 14.1 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:29:24 PM PDT 24
Peak memory 258640 kb
Host smart-734c12db-ad6d-45e1-bc8f-c91049dbcf52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737675965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.1737675965
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2450766288
Short name T126
Test name
Test status
Simulation time 156452700 ps
CPU time 604.13 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:39:15 PM PDT 24
Peak memory 282464 kb
Host smart-f1e1bb47-d0c8-4b56-bab0-706e5e3f7290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450766288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2450766288
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1347023503
Short name T790
Test name
Test status
Simulation time 73021100 ps
CPU time 33.72 seconds
Started May 23 01:29:06 PM PDT 24
Finished May 23 01:29:41 PM PDT 24
Peak memory 273624 kb
Host smart-60e23429-a556-4872-ac96-934aff5c72b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347023503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1347023503
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1961018709
Short name T999
Test name
Test status
Simulation time 3297621200 ps
CPU time 112.92 seconds
Started May 23 01:29:12 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 296740 kb
Host smart-aad7fcb7-1270-479d-a957-3bcae4a988ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961018709 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.1961018709
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.416794844
Short name T928
Test name
Test status
Simulation time 16185127500 ps
CPU time 547.32 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:38:17 PM PDT 24
Peak memory 309392 kb
Host smart-de48ded2-5c33-4186-bde8-9d1e18508624
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416794844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_rw.416794844
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.4172566016
Short name T715
Test name
Test status
Simulation time 722931400 ps
CPU time 56.27 seconds
Started May 23 01:29:12 PM PDT 24
Finished May 23 01:30:09 PM PDT 24
Peak memory 263068 kb
Host smart-4cf10c6f-8ad3-4859-a556-0d0c6c591f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172566016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.4172566016
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.519449731
Short name T580
Test name
Test status
Simulation time 59735800 ps
CPU time 122.54 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:31:10 PM PDT 24
Peak memory 275940 kb
Host smart-83a6abda-9c7d-46f0-814e-dba2ff29b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519449731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.519449731
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.2574264962
Short name T774
Test name
Test status
Simulation time 3906500700 ps
CPU time 172.58 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:32:01 PM PDT 24
Peak memory 265184 kb
Host smart-46c12d75-3894-441e-8450-018e54fa01a2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574264962 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.2574264962
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.4226856847
Short name T654
Test name
Test status
Simulation time 38630600 ps
CPU time 13.93 seconds
Started May 23 01:29:25 PM PDT 24
Finished May 23 01:29:40 PM PDT 24
Peak memory 265044 kb
Host smart-35489e97-18fe-4901-b241-7781533fd99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226856847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
4226856847
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2846217916
Short name T648
Test name
Test status
Simulation time 42078800 ps
CPU time 13.39 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:29:41 PM PDT 24
Peak memory 275060 kb
Host smart-066df999-2215-4e2d-bdb1-e6840e41cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846217916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2846217916
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3598564403
Short name T1020
Test name
Test status
Simulation time 16451200 ps
CPU time 22.4 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:29:45 PM PDT 24
Peak memory 265396 kb
Host smart-5f5e54f9-e568-4a3c-bd36-4d7dbb1e7d4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598564403 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3598564403
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3510177687
Short name T289
Test name
Test status
Simulation time 10028600700 ps
CPU time 58.14 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 276292 kb
Host smart-7661ae3c-d622-4794-b90a-c0f09720fe33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510177687 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3510177687
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3822661455
Short name T938
Test name
Test status
Simulation time 100145406500 ps
CPU time 849.08 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:43:17 PM PDT 24
Peak memory 263308 kb
Host smart-47ec05a5-3e95-4f7e-a4c6-a6ee56af963e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822661455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3822661455
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2764844202
Short name T602
Test name
Test status
Simulation time 1706002500 ps
CPU time 38.26 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:48 PM PDT 24
Peak memory 262380 kb
Host smart-c13464a2-8d3e-4b1b-985e-72062a6a0d4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764844202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.2764844202
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3118086181
Short name T1027
Test name
Test status
Simulation time 1301373800 ps
CPU time 190.71 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:32:22 PM PDT 24
Peak memory 284032 kb
Host smart-d038409a-57de-48ec-8bb7-934ba67cae91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118086181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3118086181
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3635488313
Short name T878
Test name
Test status
Simulation time 5784199700 ps
CPU time 128.43 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:31:19 PM PDT 24
Peak memory 292412 kb
Host smart-362d3f23-80a3-4a07-89ad-a93013f139c4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635488313 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3635488313
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.487979162
Short name T548
Test name
Test status
Simulation time 1003192100 ps
CPU time 87.96 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 262476 kb
Host smart-ea5cdf0b-0290-489e-b23b-8e6d58836077
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487979162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.487979162
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2244602043
Short name T294
Test name
Test status
Simulation time 15553300 ps
CPU time 13.33 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:29:41 PM PDT 24
Peak memory 265168 kb
Host smart-526bff47-fa97-4fdb-bbac-505541a37f5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244602043 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2244602043
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2404566702
Short name T81
Test name
Test status
Simulation time 19118601900 ps
CPU time 309.89 seconds
Started May 23 01:29:10 PM PDT 24
Finished May 23 01:34:21 PM PDT 24
Peak memory 273444 kb
Host smart-d272cfed-7d19-4feb-8daa-8ac2aff2a812
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404566702 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.2404566702
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.999343585
Short name T516
Test name
Test status
Simulation time 37374100 ps
CPU time 131.23 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:31:19 PM PDT 24
Peak memory 259700 kb
Host smart-bb0252c9-bbe9-4ad0-ae30-8cc8291888e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999343585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot
p_reset.999343585
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1044196008
Short name T201
Test name
Test status
Simulation time 63029800 ps
CPU time 194.4 seconds
Started May 23 01:29:10 PM PDT 24
Finished May 23 01:32:25 PM PDT 24
Peak memory 262472 kb
Host smart-70498613-98be-4872-87ab-f3e4aeede016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044196008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1044196008
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2046136280
Short name T541
Test name
Test status
Simulation time 251243800 ps
CPU time 15.12 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:26 PM PDT 24
Peak memory 265196 kb
Host smart-63002f50-60f4-4680-884f-a9fb78d8f43f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046136280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2046136280
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.3683213498
Short name T1024
Test name
Test status
Simulation time 136648300 ps
CPU time 1037.47 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:46:26 PM PDT 24
Peak memory 286520 kb
Host smart-234d1e90-b3d9-4018-9909-411dfae1a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683213498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3683213498
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.380199082
Short name T855
Test name
Test status
Simulation time 180072400 ps
CPU time 38 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:30:00 PM PDT 24
Peak memory 273476 kb
Host smart-701dc83a-1ef4-474c-9f40-e06e0c151f83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380199082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.380199082
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.2494324645
Short name T1079
Test name
Test status
Simulation time 1991223700 ps
CPU time 99.75 seconds
Started May 23 01:29:06 PM PDT 24
Finished May 23 01:30:46 PM PDT 24
Peak memory 289124 kb
Host smart-5787955e-a10e-4f00-9a53-7a9eea664c2f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494324645 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.2494324645
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.68943105
Short name T75
Test name
Test status
Simulation time 16006565500 ps
CPU time 531.18 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:38:01 PM PDT 24
Peak memory 314484 kb
Host smart-947a21dc-8e80-4f02-bc22-70f4228ae407
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68943105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_rw.68943105
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.3351477090
Short name T825
Test name
Test status
Simulation time 69140700 ps
CPU time 32.28 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:43 PM PDT 24
Peak memory 273540 kb
Host smart-e8321f81-f130-46e5-90e0-20c418a9040a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351477090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.3351477090
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2158983450
Short name T614
Test name
Test status
Simulation time 65751600 ps
CPU time 29.19 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:29:55 PM PDT 24
Peak memory 274776 kb
Host smart-3402256a-98aa-4251-bef6-04276be27400
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158983450 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2158983450
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.743009720
Short name T676
Test name
Test status
Simulation time 8221498300 ps
CPU time 72.38 seconds
Started May 23 01:29:25 PM PDT 24
Finished May 23 01:30:39 PM PDT 24
Peak memory 263024 kb
Host smart-37f0fbcb-fd16-46a6-9a70-78f3ffc80485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743009720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.743009720
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.4264486596
Short name T506
Test name
Test status
Simulation time 42332100 ps
CPU time 73.24 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:30:23 PM PDT 24
Peak memory 274856 kb
Host smart-88a39e73-b764-472a-a902-8b402e8782f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264486596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4264486596
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.373758999
Short name T849
Test name
Test status
Simulation time 3618057400 ps
CPU time 137.52 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:31:28 PM PDT 24
Peak memory 259488 kb
Host smart-de4c4f89-488c-4d48-ad82-090dee3a32f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373758999 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.373758999
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1115463895
Short name T562
Test name
Test status
Simulation time 151149300 ps
CPU time 13.9 seconds
Started May 23 01:29:25 PM PDT 24
Finished May 23 01:29:40 PM PDT 24
Peak memory 265040 kb
Host smart-9c617232-1e10-4ea0-a2e5-a85a69c323d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115463895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1115463895
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.580185702
Short name T600
Test name
Test status
Simulation time 62983500 ps
CPU time 15.73 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:29:42 PM PDT 24
Peak memory 274916 kb
Host smart-776f763b-c051-4f31-82b8-3807ac42b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580185702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.580185702
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.404039979
Short name T789
Test name
Test status
Simulation time 26671000 ps
CPU time 22.25 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:29:48 PM PDT 24
Peak memory 265100 kb
Host smart-5cbefb1e-aa29-4a28-acb2-89e0d3c1ed44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404039979 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.404039979
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.368214636
Short name T977
Test name
Test status
Simulation time 10040295500 ps
CPU time 42.99 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:30:08 PM PDT 24
Peak memory 266388 kb
Host smart-34c3c17c-d6c2-4820-9837-d782816aa331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368214636 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.368214636
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.806964220
Short name T1008
Test name
Test status
Simulation time 124800400 ps
CPU time 13.76 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:29:39 PM PDT 24
Peak memory 265252 kb
Host smart-1e8dd2de-a2f0-4ee8-bee9-04315afa2f94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806964220 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.806964220
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2778666166
Short name T914
Test name
Test status
Simulation time 40123574300 ps
CPU time 821.8 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:43:05 PM PDT 24
Peak memory 263436 kb
Host smart-0c74f040-dc4b-44dd-8f54-8f293fbe2223
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778666166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.2778666166
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3662127768
Short name T856
Test name
Test status
Simulation time 4872539300 ps
CPU time 144.46 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:31:50 PM PDT 24
Peak memory 262548 kb
Host smart-8334ed38-a192-4636-adbf-5028ddb3f36f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662127768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.3662127768
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1364885471
Short name T755
Test name
Test status
Simulation time 1344842700 ps
CPU time 139.94 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:31:48 PM PDT 24
Peak memory 289960 kb
Host smart-11459035-9317-43b6-a1e1-8a1a504796d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364885471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1364885471
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.293752256
Short name T656
Test name
Test status
Simulation time 5556120800 ps
CPU time 127.22 seconds
Started May 23 01:29:22 PM PDT 24
Finished May 23 01:31:31 PM PDT 24
Peak memory 291784 kb
Host smart-62a4ae36-50a6-4099-86c7-0da45cf69f29
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293752256 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.293752256
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.521776222
Short name T110
Test name
Test status
Simulation time 16109227900 ps
CPU time 97.24 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:31:02 PM PDT 24
Peak memory 260696 kb
Host smart-9d021371-2fc4-4c15-9041-3389e0ad237e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521776222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.521776222
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3394690898
Short name T956
Test name
Test status
Simulation time 15473200 ps
CPU time 13.84 seconds
Started May 23 01:29:22 PM PDT 24
Finished May 23 01:29:38 PM PDT 24
Peak memory 265172 kb
Host smart-9a478c3a-c9e8-45dd-ad3a-d2cbf4ed83b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394690898 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3394690898
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.2137402421
Short name T905
Test name
Test status
Simulation time 20786154700 ps
CPU time 434.69 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:36:42 PM PDT 24
Peak memory 274284 kb
Host smart-ba24d4f6-daf2-4ccd-a8e3-b4b7189556f8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137402421 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.2137402421
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1519201063
Short name T499
Test name
Test status
Simulation time 150826800 ps
CPU time 111.19 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:31:14 PM PDT 24
Peak memory 264392 kb
Host smart-c19757da-572c-482e-a127-8124648dec06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519201063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1519201063
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2552931999
Short name T957
Test name
Test status
Simulation time 58061100 ps
CPU time 237.08 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 262272 kb
Host smart-45e7d121-fafa-400d-b79a-c640b706f1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552931999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2552931999
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3346939048
Short name T415
Test name
Test status
Simulation time 361534800 ps
CPU time 41 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:30:03 PM PDT 24
Peak memory 265200 kb
Host smart-5f035275-bb0c-4eb4-8ffa-205911e0e2a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346939048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3346939048
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.700215550
Short name T793
Test name
Test status
Simulation time 448236000 ps
CPU time 1175.6 seconds
Started May 23 01:29:22 PM PDT 24
Finished May 23 01:48:59 PM PDT 24
Peak memory 285880 kb
Host smart-acb80775-1ace-47b8-bce6-72a5d4ee7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700215550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.700215550
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1645569616
Short name T26
Test name
Test status
Simulation time 256955800 ps
CPU time 36.25 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:30:01 PM PDT 24
Peak memory 273556 kb
Host smart-a510c594-a8e6-45ba-96e6-6810101cc72d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645569616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1645569616
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.3394142264
Short name T268
Test name
Test status
Simulation time 476202500 ps
CPU time 108.23 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:31:16 PM PDT 24
Peak memory 281636 kb
Host smart-8c9e035a-46a2-45a8-8e00-8ad8f8b40e82
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394142264 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.3394142264
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2289568648
Short name T924
Test name
Test status
Simulation time 7362514500 ps
CPU time 560.44 seconds
Started May 23 01:29:26 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 309436 kb
Host smart-22f52b81-02e2-495d-bf84-18640c10b18f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289568648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.2289568648
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2236280892
Short name T559
Test name
Test status
Simulation time 171407100 ps
CPU time 29.35 seconds
Started May 23 01:29:24 PM PDT 24
Finished May 23 01:29:56 PM PDT 24
Peak memory 274664 kb
Host smart-643a5f07-8ecd-48d6-9491-8b2980814403
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236280892 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2236280892
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.4094983555
Short name T869
Test name
Test status
Simulation time 280765100 ps
CPU time 145.12 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 276348 kb
Host smart-d2bad8fd-d07a-4831-b703-7f0744aa2c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094983555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.4094983555
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.721999334
Short name T651
Test name
Test status
Simulation time 14520793500 ps
CPU time 256.43 seconds
Started May 23 01:29:25 PM PDT 24
Finished May 23 01:33:43 PM PDT 24
Peak memory 265208 kb
Host smart-ef5f1cbc-c97a-452c-9bc7-514058400743
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721999334 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.flash_ctrl_wo.721999334
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.37408470
Short name T405
Test name
Test status
Simulation time 391274300 ps
CPU time 13.96 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 265108 kb
Host smart-5fa5417f-8518-497b-a715-10e7d3ef9d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37408470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.37408470
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3573094850
Short name T418
Test name
Test status
Simulation time 41419600 ps
CPU time 15.54 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:29:55 PM PDT 24
Peak memory 275932 kb
Host smart-4dc9a069-edab-4e58-9cdc-43d53d38ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573094850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3573094850
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3773194029
Short name T195
Test name
Test status
Simulation time 25355000 ps
CPU time 22 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:30:01 PM PDT 24
Peak memory 265336 kb
Host smart-9b5b6236-45b8-45de-a8f9-2565ced5aa45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773194029 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3773194029
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1211659271
Short name T1071
Test name
Test status
Simulation time 10050364800 ps
CPU time 52.57 seconds
Started May 23 01:29:35 PM PDT 24
Finished May 23 01:30:30 PM PDT 24
Peak memory 277132 kb
Host smart-91ec12c0-788a-417d-8993-a2bf68fb09c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211659271 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1211659271
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.406440973
Short name T101
Test name
Test status
Simulation time 25445900 ps
CPU time 13.22 seconds
Started May 23 01:29:42 PM PDT 24
Finished May 23 01:29:56 PM PDT 24
Peak memory 265356 kb
Host smart-75618666-befd-40cd-bdb5-46781348e2bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406440973 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.406440973
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3640763990
Short name T932
Test name
Test status
Simulation time 7492105600 ps
CPU time 133.34 seconds
Started May 23 01:29:25 PM PDT 24
Finished May 23 01:31:40 PM PDT 24
Peak memory 262632 kb
Host smart-656b7326-d8a1-45f2-852c-34d9cbcd5d76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640763990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3640763990
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.1057588179
Short name T166
Test name
Test status
Simulation time 2038137500 ps
CPU time 121.16 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 297932 kb
Host smart-e0a145d8-ed6d-446c-a763-07708af1c65f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057588179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.1057588179
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2259797137
Short name T1046
Test name
Test status
Simulation time 5843516500 ps
CPU time 146.57 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:32:05 PM PDT 24
Peak memory 291832 kb
Host smart-f3caefb7-902d-47e5-87e8-5d7df7d2fc8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259797137 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2259797137
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.510753376
Short name T413
Test name
Test status
Simulation time 1811859600 ps
CPU time 87.95 seconds
Started May 23 01:29:41 PM PDT 24
Finished May 23 01:31:11 PM PDT 24
Peak memory 260800 kb
Host smart-d4f73936-aa31-4a83-b88a-1444df5657e8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510753376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.510753376
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2476332263
Short name T512
Test name
Test status
Simulation time 15839200 ps
CPU time 13.72 seconds
Started May 23 01:29:38 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 264300 kb
Host smart-7fb06e94-8348-45ea-bbc3-f6348a94fd09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476332263 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2476332263
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.541990050
Short name T479
Test name
Test status
Simulation time 1788376300 ps
CPU time 160.04 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:32:19 PM PDT 24
Peak memory 265232 kb
Host smart-a5d473e6-ea32-4647-93c8-aa7ed13513d1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541990050 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.541990050
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.965589106
Short name T319
Test name
Test status
Simulation time 279274100 ps
CPU time 133.32 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:31:38 PM PDT 24
Peak memory 260984 kb
Host smart-87a6bdea-26f4-47f4-94b0-9ee91734d2dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965589106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.965589106
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.1739132472
Short name T525
Test name
Test status
Simulation time 772032600 ps
CPU time 511.12 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:37:55 PM PDT 24
Peak memory 262452 kb
Host smart-b317d372-0360-4fd1-8442-d65c68a44312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739132472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.1739132472
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.304140259
Short name T1089
Test name
Test status
Simulation time 19707300 ps
CPU time 13.56 seconds
Started May 23 01:29:38 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 265156 kb
Host smart-28267c81-85dd-4e91-83c8-c6785c00ff36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304140259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_res
et.304140259
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.3428181466
Short name T686
Test name
Test status
Simulation time 2536576500 ps
CPU time 519.87 seconds
Started May 23 01:29:23 PM PDT 24
Finished May 23 01:38:04 PM PDT 24
Peak memory 284564 kb
Host smart-efbf0b27-7507-4dab-84bb-e061041e2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428181466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3428181466
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.1925852168
Short name T837
Test name
Test status
Simulation time 275788800 ps
CPU time 33.42 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 274640 kb
Host smart-08787ed6-2288-4e7e-bb56-cfebceb592a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925852168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.1925852168
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3822302249
Short name T1004
Test name
Test status
Simulation time 1005258300 ps
CPU time 99.82 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:31:18 PM PDT 24
Peak memory 297012 kb
Host smart-0e548576-9c1b-41c9-a076-773031557e6e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822302249 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.3822302249
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.798439943
Short name T17
Test name
Test status
Simulation time 93667000 ps
CPU time 31.47 seconds
Started May 23 01:29:42 PM PDT 24
Finished May 23 01:30:14 PM PDT 24
Peak memory 267416 kb
Host smart-729b37ba-3d8b-4860-b523-ae778881bb35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798439943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_rw_evict.798439943
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1736753795
Short name T492
Test name
Test status
Simulation time 43930300 ps
CPU time 31.7 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:30:11 PM PDT 24
Peak memory 274872 kb
Host smart-8e18ee31-f333-4378-9b42-d7d3ff01cc9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736753795 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1736753795
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2258319009
Short name T1088
Test name
Test status
Simulation time 1132702500 ps
CPU time 60.56 seconds
Started May 23 01:29:40 PM PDT 24
Finished May 23 01:30:42 PM PDT 24
Peak memory 263600 kb
Host smart-3098cef7-ef3d-49e4-9b5b-51490d8ab935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258319009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2258319009
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.1109364336
Short name T439
Test name
Test status
Simulation time 23343500 ps
CPU time 73.95 seconds
Started May 23 01:29:21 PM PDT 24
Finished May 23 01:30:37 PM PDT 24
Peak memory 274992 kb
Host smart-246768d7-d00e-4b4b-9928-1572b0304cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109364336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1109364336
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3030087582
Short name T728
Test name
Test status
Simulation time 8544914900 ps
CPU time 189.49 seconds
Started May 23 01:29:41 PM PDT 24
Finished May 23 01:32:52 PM PDT 24
Peak memory 265092 kb
Host smart-4f5a23c7-ffe6-47ad-ba60-82124d1808b2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030087582 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.3030087582
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.1830084778
Short name T433
Test name
Test status
Simulation time 178627200 ps
CPU time 13.84 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:30:13 PM PDT 24
Peak memory 265212 kb
Host smart-955675f8-d7f5-4f99-8ae7-bc71805efdd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830084778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
1830084778
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.4241840175
Short name T972
Test name
Test status
Simulation time 15557800 ps
CPU time 15.72 seconds
Started May 23 01:29:54 PM PDT 24
Finished May 23 01:30:13 PM PDT 24
Peak memory 275596 kb
Host smart-ca9368b9-4763-4d6d-b141-6d5f4caec5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241840175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.4241840175
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.132000739
Short name T845
Test name
Test status
Simulation time 15090700 ps
CPU time 20.45 seconds
Started May 23 01:29:54 PM PDT 24
Finished May 23 01:30:17 PM PDT 24
Peak memory 265236 kb
Host smart-b5e35827-7f47-4b1b-9d33-271bad03e857
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132000739 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.132000739
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.408074306
Short name T664
Test name
Test status
Simulation time 10033172500 ps
CPU time 41.44 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:30:40 PM PDT 24
Peak memory 265288 kb
Host smart-faecda64-60fd-4bf9-b758-0313b54e5fca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408074306 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.408074306
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2433826874
Short name T312
Test name
Test status
Simulation time 131939800 ps
CPU time 13.37 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 265148 kb
Host smart-13b8c832-a0be-476f-959c-68120ebd2a0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433826874 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2433826874
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3209644615
Short name T157
Test name
Test status
Simulation time 80137199400 ps
CPU time 881.57 seconds
Started May 23 01:29:35 PM PDT 24
Finished May 23 01:44:19 PM PDT 24
Peak memory 264436 kb
Host smart-3142402f-8c4c-4e83-9766-65badf6ed73b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209644615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.3209644615
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2741469862
Short name T443
Test name
Test status
Simulation time 8245498600 ps
CPU time 100.13 seconds
Started May 23 01:29:41 PM PDT 24
Finished May 23 01:31:22 PM PDT 24
Peak memory 262500 kb
Host smart-c092aade-e2bc-40d4-bedc-521275763513
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741469862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2741469862
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1060646495
Short name T354
Test name
Test status
Simulation time 8080904000 ps
CPU time 137.96 seconds
Started May 23 01:29:54 PM PDT 24
Finished May 23 01:32:14 PM PDT 24
Peak memory 293012 kb
Host smart-51f4086b-d318-4b48-aeae-4c70cb6065f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060646495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1060646495
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3737461670
Short name T945
Test name
Test status
Simulation time 107045087400 ps
CPU time 298.06 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:34:56 PM PDT 24
Peak memory 291060 kb
Host smart-ff5bde7e-1136-442b-a731-8e6c7294ae4c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737461670 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3737461670
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.2471981763
Short name T468
Test name
Test status
Simulation time 3265368300 ps
CPU time 71.69 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:30:51 PM PDT 24
Peak memory 260640 kb
Host smart-b48bba0a-0710-4311-8af6-fd9120bf255a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471981763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2
471981763
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1401755930
Short name T293
Test name
Test status
Simulation time 47078300 ps
CPU time 13.4 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 265096 kb
Host smart-0c7c811f-359f-48f3-966c-4ec7273277cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401755930 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1401755930
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.4122406444
Short name T80
Test name
Test status
Simulation time 68839159700 ps
CPU time 656.22 seconds
Started May 23 01:29:36 PM PDT 24
Finished May 23 01:40:35 PM PDT 24
Peak memory 273352 kb
Host smart-cacda3e7-eaf6-45e7-8a61-0707f1709fb3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122406444 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.4122406444
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3935374757
Short name T658
Test name
Test status
Simulation time 70848200 ps
CPU time 131.29 seconds
Started May 23 01:29:35 PM PDT 24
Finished May 23 01:31:48 PM PDT 24
Peak memory 259784 kb
Host smart-c034791f-945d-48d4-b234-d897e85a3984
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935374757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3935374757
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.4034567050
Short name T203
Test name
Test status
Simulation time 1421366300 ps
CPU time 377.93 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:35:57 PM PDT 24
Peak memory 262476 kb
Host smart-cb27a72c-3560-44af-b991-cfe8d85e9dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034567050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.4034567050
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.337327865
Short name T725
Test name
Test status
Simulation time 7693790300 ps
CPU time 166.77 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:32:45 PM PDT 24
Peak memory 259876 kb
Host smart-564f5f91-7a69-46ac-86ec-8307521bcfe6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337327865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.337327865
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.862692381
Short name T127
Test name
Test status
Simulation time 72864700 ps
CPU time 248.43 seconds
Started May 23 01:29:42 PM PDT 24
Finished May 23 01:33:51 PM PDT 24
Peak memory 276984 kb
Host smart-828b4f0e-ea6d-457f-94c0-5f3089356cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862692381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.862692381
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3476706392
Short name T549
Test name
Test status
Simulation time 9160059400 ps
CPU time 126.9 seconds
Started May 23 01:29:57 PM PDT 24
Finished May 23 01:32:06 PM PDT 24
Peak memory 297048 kb
Host smart-4ed4919f-8189-458d-b256-3ea55f83a3d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476706392 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.3476706392
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3598559872
Short name T529
Test name
Test status
Simulation time 6324933100 ps
CPU time 504.62 seconds
Started May 23 01:29:54 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 309720 kb
Host smart-727628c1-4645-450b-9f38-ffa2f91fc107
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598559872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.3598559872
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.4293886279
Short name T333
Test name
Test status
Simulation time 28835100 ps
CPU time 32.28 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:30:31 PM PDT 24
Peak memory 273600 kb
Host smart-1dc5a879-571d-48a1-b2d7-c956da698c8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293886279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.4293886279
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3067324959
Short name T501
Test name
Test status
Simulation time 48179400 ps
CPU time 31.83 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:30:30 PM PDT 24
Peak memory 269376 kb
Host smart-96ee6b0d-8de8-4ad9-87ed-b731def946f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067324959 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3067324959
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.857304157
Short name T527
Test name
Test status
Simulation time 1495570300 ps
CPU time 54.74 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:30:52 PM PDT 24
Peak memory 262724 kb
Host smart-98dff7fe-bc7b-4a1d-9844-11a5c26bd30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857304157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.857304157
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3973628537
Short name T736
Test name
Test status
Simulation time 26328300 ps
CPU time 50.6 seconds
Started May 23 01:29:38 PM PDT 24
Finished May 23 01:30:31 PM PDT 24
Peak memory 270680 kb
Host smart-1d42255c-cbe4-4f7b-becf-fe3f9b3825e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973628537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3973628537
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3320648397
Short name T98
Test name
Test status
Simulation time 3850672700 ps
CPU time 186.31 seconds
Started May 23 01:29:37 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 265120 kb
Host smart-3c117d6a-da64-414b-92a8-e99b2dc5e81a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320648397 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3320648397
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1661429308
Short name T1094
Test name
Test status
Simulation time 26807600 ps
CPU time 13.66 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:30:24 PM PDT 24
Peak memory 265144 kb
Host smart-67d43007-cfa2-434c-90b5-89282c2960c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661429308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1661429308
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3106809428
Short name T900
Test name
Test status
Simulation time 47257600 ps
CPU time 15.62 seconds
Started May 23 01:30:06 PM PDT 24
Finished May 23 01:30:23 PM PDT 24
Peak memory 275884 kb
Host smart-0b52780c-dfce-43be-b9d0-83f4244bf775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106809428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3106809428
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2549211688
Short name T290
Test name
Test status
Simulation time 10019887100 ps
CPU time 64.34 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:31:15 PM PDT 24
Peak memory 265404 kb
Host smart-5320fece-7727-4929-a072-0e30d07d73fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549211688 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2549211688
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2237436132
Short name T912
Test name
Test status
Simulation time 15993400 ps
CPU time 13.74 seconds
Started May 23 01:30:10 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 265152 kb
Host smart-d3d1bcf4-a252-47a5-ad06-d6d53f4a7f86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237436132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2237436132
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.721946061
Short name T1055
Test name
Test status
Simulation time 40125693100 ps
CPU time 828.82 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:43:47 PM PDT 24
Peak memory 263060 kb
Host smart-a4286b00-a090-44de-bef0-69938eb2a796
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721946061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.flash_ctrl_hw_rma_reset.721946061
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1306804826
Short name T624
Test name
Test status
Simulation time 2936430100 ps
CPU time 114.15 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:31:52 PM PDT 24
Peak memory 262084 kb
Host smart-0728a07e-1a63-4c96-bfbf-58ee79116cf9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306804826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1306804826
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.819050940
Short name T351
Test name
Test status
Simulation time 50869916700 ps
CPU time 267.52 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:34:37 PM PDT 24
Peak memory 290944 kb
Host smart-c2073838-80d2-4093-9876-4d9c094fcbad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819050940 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.819050940
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3004353509
Short name T732
Test name
Test status
Simulation time 15331000 ps
CPU time 13.45 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:30:21 PM PDT 24
Peak memory 265204 kb
Host smart-f841616a-1ba2-438e-b9d5-eeceaf39fa5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004353509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3004353509
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.358648694
Short name T885
Test name
Test status
Simulation time 4120708400 ps
CPU time 173.26 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:32:51 PM PDT 24
Peak memory 265116 kb
Host smart-43ffb511-81b5-4b0e-8fc0-c1ba16d2f976
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358648694 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_mp_regions.358648694
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.838898118
Short name T489
Test name
Test status
Simulation time 156590600 ps
CPU time 135.79 seconds
Started May 23 01:29:57 PM PDT 24
Finished May 23 01:32:15 PM PDT 24
Peak memory 263412 kb
Host smart-f02dd405-c23a-410c-afd5-0218e70274e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838898118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.838898118
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.3105602956
Short name T943
Test name
Test status
Simulation time 38125300 ps
CPU time 110.61 seconds
Started May 23 01:29:56 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 262396 kb
Host smart-b37057b6-f0f3-4faf-b25b-e3a5c2e4fba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105602956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.3105602956
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.184666487
Short name T967
Test name
Test status
Simulation time 21251200 ps
CPU time 13.71 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 264660 kb
Host smart-f7bf20f3-2469-493f-b059-f85a324116ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184666487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.184666487
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.2949305130
Short name T111
Test name
Test status
Simulation time 398136600 ps
CPU time 725.97 seconds
Started May 23 01:29:54 PM PDT 24
Finished May 23 01:42:03 PM PDT 24
Peak memory 284224 kb
Host smart-03b8595b-2222-4963-a32b-929747edc4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949305130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2949305130
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1563682959
Short name T973
Test name
Test status
Simulation time 166249600 ps
CPU time 37.57 seconds
Started May 23 01:30:11 PM PDT 24
Finished May 23 01:30:50 PM PDT 24
Peak memory 274592 kb
Host smart-8073e02c-7fd2-4a41-8e99-261f71999c90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563682959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1563682959
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2541846553
Short name T995
Test name
Test status
Simulation time 479254400 ps
CPU time 112.57 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:32:01 PM PDT 24
Peak memory 289232 kb
Host smart-4b466777-e289-41c1-be3d-640eda6d2c45
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541846553 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2541846553
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1954045560
Short name T960
Test name
Test status
Simulation time 14055585500 ps
CPU time 507.39 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:38:37 PM PDT 24
Peak memory 313572 kb
Host smart-09c5532e-7def-469f-91e5-1bcc187fbb75
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954045560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.1954045560
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2582557772
Short name T530
Test name
Test status
Simulation time 30936000 ps
CPU time 31.37 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:30:39 PM PDT 24
Peak memory 273612 kb
Host smart-a0509d3f-ad99-47b2-878f-f73d857eb8cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582557772 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.2582557772
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1410920770
Short name T996
Test name
Test status
Simulation time 1444232700 ps
CPU time 65.65 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:31:14 PM PDT 24
Peak memory 263040 kb
Host smart-fa3aaeaa-3509-4cd1-b9fe-272bb22dfcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410920770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1410920770
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.802419578
Short name T552
Test name
Test status
Simulation time 20858000 ps
CPU time 52.02 seconds
Started May 23 01:29:55 PM PDT 24
Finished May 23 01:30:50 PM PDT 24
Peak memory 270512 kb
Host smart-5e10e048-8e86-4725-9fa2-596d72c9b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802419578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.802419578
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2456230375
Short name T902
Test name
Test status
Simulation time 10552426100 ps
CPU time 213.36 seconds
Started May 23 01:30:10 PM PDT 24
Finished May 23 01:33:45 PM PDT 24
Peak memory 265064 kb
Host smart-37f1f8cb-9f03-4506-a390-f8ca823a2fe2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456230375 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.2456230375
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.1420600464
Short name T102
Test name
Test status
Simulation time 75335200 ps
CPU time 14.17 seconds
Started May 23 01:30:05 PM PDT 24
Finished May 23 01:30:21 PM PDT 24
Peak memory 265232 kb
Host smart-d369e6f6-5f9c-46eb-8275-18b9de8bcb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420600464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
1420600464
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.3549872529
Short name T862
Test name
Test status
Simulation time 199979100 ps
CPU time 15.6 seconds
Started May 23 01:30:11 PM PDT 24
Finished May 23 01:30:28 PM PDT 24
Peak memory 275684 kb
Host smart-b7971d52-1023-449a-8c20-52b330bc944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549872529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3549872529
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2285839338
Short name T740
Test name
Test status
Simulation time 25502900 ps
CPU time 21.95 seconds
Started May 23 01:30:06 PM PDT 24
Finished May 23 01:30:29 PM PDT 24
Peak memory 265140 kb
Host smart-827f265a-4d25-40fd-97db-a72dcafbf94b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285839338 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2285839338
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.274752741
Short name T918
Test name
Test status
Simulation time 10019929400 ps
CPU time 64.41 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:31:15 PM PDT 24
Peak memory 268332 kb
Host smart-ea3c09fa-6f96-4834-b564-d776be606570
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274752741 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.274752741
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.964106896
Short name T692
Test name
Test status
Simulation time 46538000 ps
CPU time 13.52 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:30:23 PM PDT 24
Peak memory 265112 kb
Host smart-f08f7118-2572-43ab-ab27-32c0fe4b56c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964106896 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.964106896
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2035647942
Short name T493
Test name
Test status
Simulation time 170189424000 ps
CPU time 995.56 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:46:44 PM PDT 24
Peak memory 263968 kb
Host smart-c0b8f212-0c01-455e-b334-4beedd3c216a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035647942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.2035647942
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3679278147
Short name T48
Test name
Test status
Simulation time 25618471600 ps
CPU time 107.71 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:31:58 PM PDT 24
Peak memory 262604 kb
Host smart-26a8f764-7b0a-4c87-bb9c-34cf0fe82dce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679278147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3679278147
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.1545597351
Short name T799
Test name
Test status
Simulation time 1623671500 ps
CPU time 136.81 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:32:27 PM PDT 24
Peak memory 291872 kb
Host smart-752737f0-88f5-4fb0-81fe-85873ab2c72a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545597351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.1545597351
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2798638697
Short name T719
Test name
Test status
Simulation time 23839630400 ps
CPU time 438.88 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 292044 kb
Host smart-c9c96684-612d-4288-a7ed-7a34202fa93e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798638697 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2798638697
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3454277579
Short name T747
Test name
Test status
Simulation time 7044717000 ps
CPU time 72.93 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:31:22 PM PDT 24
Peak memory 259768 kb
Host smart-db48a7df-43a9-4884-9a7b-16cb36ca19b5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454277579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
454277579
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2318789156
Short name T896
Test name
Test status
Simulation time 181587500 ps
CPU time 14.03 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:30:23 PM PDT 24
Peak memory 265196 kb
Host smart-a8bfa437-3ea8-4c66-97e9-9f9ca5571378
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318789156 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2318789156
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.4082412875
Short name T79
Test name
Test status
Simulation time 19323391900 ps
CPU time 246.45 seconds
Started May 23 01:30:06 PM PDT 24
Finished May 23 01:34:14 PM PDT 24
Peak memory 274324 kb
Host smart-dae4b1d1-d335-4ea3-9423-8764e300abc6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082412875 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.4082412875
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1649494205
Short name T145
Test name
Test status
Simulation time 39015600 ps
CPU time 133.81 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:32:23 PM PDT 24
Peak memory 261164 kb
Host smart-dd7a7d67-ffeb-4350-8a79-0500bc9231b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649494205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1649494205
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.2345438673
Short name T619
Test name
Test status
Simulation time 202089600 ps
CPU time 237.59 seconds
Started May 23 01:30:06 PM PDT 24
Finished May 23 01:34:05 PM PDT 24
Peak memory 262348 kb
Host smart-89bcf3ff-48a2-44ad-9155-1bbab6c10caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345438673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2345438673
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2929911054
Short name T377
Test name
Test status
Simulation time 2123571800 ps
CPU time 158.24 seconds
Started May 23 01:30:11 PM PDT 24
Finished May 23 01:32:51 PM PDT 24
Peak memory 259608 kb
Host smart-32843f3f-caad-4ae9-91e5-1a4a102b3995
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929911054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2929911054
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1891630863
Short name T951
Test name
Test status
Simulation time 46559700 ps
CPU time 295.7 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:35:06 PM PDT 24
Peak memory 281512 kb
Host smart-f012aa23-aa9a-4761-8cee-27a0d72226b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891630863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1891630863
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2461594034
Short name T531
Test name
Test status
Simulation time 100858700 ps
CPU time 37.5 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:30:48 PM PDT 24
Peak memory 275640 kb
Host smart-ae12a5bb-7888-4eab-a82d-5796a898856f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461594034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2461594034
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2371994534
Short name T751
Test name
Test status
Simulation time 1058378900 ps
CPU time 112.15 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:32:02 PM PDT 24
Peak memory 281640 kb
Host smart-9054397e-68f8-4ae7-83b6-237f0ae233a2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371994534 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2371994534
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2668643800
Short name T968
Test name
Test status
Simulation time 3588748600 ps
CPU time 461.47 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:37:52 PM PDT 24
Peak memory 309432 kb
Host smart-6579e229-e658-4b92-8937-3c4946e18283
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668643800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2668643800
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.2840451963
Short name T402
Test name
Test status
Simulation time 12287151000 ps
CPU time 79.33 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:31:30 PM PDT 24
Peak memory 262300 kb
Host smart-aa7707de-a188-4d49-b10f-4106d2e53a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840451963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2840451963
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1652174608
Short name T579
Test name
Test status
Simulation time 34866100 ps
CPU time 51.67 seconds
Started May 23 01:30:10 PM PDT 24
Finished May 23 01:31:04 PM PDT 24
Peak memory 270516 kb
Host smart-a560fbfa-0db6-453b-9c74-a7601f24314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652174608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1652174608
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1261236356
Short name T534
Test name
Test status
Simulation time 2662237500 ps
CPU time 227.78 seconds
Started May 23 01:30:07 PM PDT 24
Finished May 23 01:33:56 PM PDT 24
Peak memory 265180 kb
Host smart-305ac6ba-901b-4c2d-8070-d3382378a59e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261236356 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.1261236356
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.2483082395
Short name T994
Test name
Test status
Simulation time 216446000 ps
CPU time 14.89 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 265076 kb
Host smart-cce9b590-a4e3-4251-8c7b-2c89db25a60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483082395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
2483082395
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2468639868
Short name T852
Test name
Test status
Simulation time 50569000 ps
CPU time 13.55 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:30:34 PM PDT 24
Peak memory 275588 kb
Host smart-5952f59b-1ec3-477c-be2d-24032bdb2149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468639868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2468639868
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.3530023609
Short name T100
Test name
Test status
Simulation time 40062300 ps
CPU time 22.25 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:30:43 PM PDT 24
Peak memory 280268 kb
Host smart-719a52b3-1ab4-4373-95f3-22213f06fe64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530023609 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.3530023609
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3548905267
Short name T560
Test name
Test status
Simulation time 10018916400 ps
CPU time 66.98 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:31:29 PM PDT 24
Peak memory 265416 kb
Host smart-21924090-2d0c-41aa-b6e1-2f93165644b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548905267 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3548905267
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2890765210
Short name T569
Test name
Test status
Simulation time 15668700 ps
CPU time 13.65 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:30:33 PM PDT 24
Peak memory 265072 kb
Host smart-8b4f957b-fb04-4724-9de1-04c108f88cb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890765210 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.2890765210
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3173227472
Short name T606
Test name
Test status
Simulation time 100162886200 ps
CPU time 923.92 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:45:34 PM PDT 24
Peak memory 264224 kb
Host smart-f9e56010-6cca-45f6-b97e-a9fa8cb7eb67
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173227472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.3173227472
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4130688436
Short name T683
Test name
Test status
Simulation time 3682491700 ps
CPU time 120.05 seconds
Started May 23 01:30:09 PM PDT 24
Finished May 23 01:32:10 PM PDT 24
Peak memory 262524 kb
Host smart-accc2bb0-2f9f-4eeb-b8d5-d983db96a2d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130688436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.4130688436
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3067992432
Short name T746
Test name
Test status
Simulation time 1535868500 ps
CPU time 126.61 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:32:29 PM PDT 24
Peak memory 293068 kb
Host smart-94c28623-c510-40f4-ba83-8741408d769c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067992432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3067992432
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3224838149
Short name T599
Test name
Test status
Simulation time 11331246800 ps
CPU time 150.03 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:32:53 PM PDT 24
Peak memory 292112 kb
Host smart-14e85a1f-e203-4aae-ae83-9b3f8eb08e2a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224838149 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3224838149
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.2286915835
Short name T410
Test name
Test status
Simulation time 7468008100 ps
CPU time 85.9 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:31:48 PM PDT 24
Peak memory 259816 kb
Host smart-3830fdf4-6ace-4dd1-ba23-b19eabe779e3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286915835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2
286915835
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.208375931
Short name T570
Test name
Test status
Simulation time 74781600 ps
CPU time 13.4 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:30:36 PM PDT 24
Peak memory 265164 kb
Host smart-e96bbc1d-eefe-4437-9757-7d4369f2262a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208375931 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.208375931
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.284419245
Short name T607
Test name
Test status
Simulation time 24366969000 ps
CPU time 129.25 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:32:29 PM PDT 24
Peak memory 261656 kb
Host smart-1da1d60f-b1ad-49ec-b951-e35d48bd752d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284419245 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_mp_regions.284419245
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3591637079
Short name T630
Test name
Test status
Simulation time 95827100 ps
CPU time 133.88 seconds
Started May 23 01:30:22 PM PDT 24
Finished May 23 01:32:38 PM PDT 24
Peak memory 259900 kb
Host smart-feb5ea5a-5e5a-4fc9-84fb-29762c9f54a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591637079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3591637079
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.2198034384
Short name T22
Test name
Test status
Simulation time 227115200 ps
CPU time 323.72 seconds
Started May 23 01:30:11 PM PDT 24
Finished May 23 01:35:36 PM PDT 24
Peak memory 262376 kb
Host smart-342b5054-3aad-4dda-b52e-1d7fbd454fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198034384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2198034384
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.4277148398
Short name T1011
Test name
Test status
Simulation time 27422900 ps
CPU time 13.34 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:30:37 PM PDT 24
Peak memory 258692 kb
Host smart-f06930cf-2fc1-4ee2-86e2-920e7f8cf97a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277148398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.4277148398
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.674253083
Short name T863
Test name
Test status
Simulation time 4280512300 ps
CPU time 501.31 seconds
Started May 23 01:30:08 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 282560 kb
Host smart-5c27206c-8358-4b71-af8a-50b8c404127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674253083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.674253083
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.3138595284
Short name T328
Test name
Test status
Simulation time 87513400 ps
CPU time 36.4 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:30:58 PM PDT 24
Peak memory 267372 kb
Host smart-9dcdc3b4-8f21-4550-aaaf-a1cff8799523
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138595284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.3138595284
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.4294612958
Short name T1035
Test name
Test status
Simulation time 1543205300 ps
CPU time 128.74 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:32:29 PM PDT 24
Peak memory 281524 kb
Host smart-da9478a0-5132-4c25-9d00-b972d0ba0c0a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294612958 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.4294612958
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.780347352
Short name T194
Test name
Test status
Simulation time 23343056700 ps
CPU time 539.14 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:39:21 PM PDT 24
Peak memory 314508 kb
Host smart-8f4866f5-86bf-4eb1-bd40-3aa2bc36eb2c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780347352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_rw.780347352
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.327867467
Short name T507
Test name
Test status
Simulation time 91398500 ps
CPU time 28.83 seconds
Started May 23 01:30:22 PM PDT 24
Finished May 23 01:30:53 PM PDT 24
Peak memory 273580 kb
Host smart-db25cc9e-0e13-4fca-afc5-9d283403fd98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327867467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.327867467
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.3621214075
Short name T211
Test name
Test status
Simulation time 59125300 ps
CPU time 31.85 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:30:55 PM PDT 24
Peak memory 274776 kb
Host smart-f6eb480e-27c5-45fc-bf4a-4a66a72cfad8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621214075 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.3621214075
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.3167337268
Short name T1028
Test name
Test status
Simulation time 176495100 ps
CPU time 143.42 seconds
Started May 23 01:30:10 PM PDT 24
Finished May 23 01:32:36 PM PDT 24
Peak memory 277796 kb
Host smart-b911f9b3-330d-4c6b-ae6a-f5a4db3506fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167337268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3167337268
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2138478839
Short name T519
Test name
Test status
Simulation time 8592644200 ps
CPU time 156.07 seconds
Started May 23 01:30:18 PM PDT 24
Finished May 23 01:32:55 PM PDT 24
Peak memory 265124 kb
Host smart-312d1348-939f-4396-bfb1-1e04675f159d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138478839 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.2138478839
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2328033745
Short name T452
Test name
Test status
Simulation time 118158300 ps
CPU time 14.01 seconds
Started May 23 01:30:32 PM PDT 24
Finished May 23 01:30:48 PM PDT 24
Peak memory 264376 kb
Host smart-e04d6a48-a2c8-497d-a4d1-5213c324bf6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328033745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2328033745
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.1458438476
Short name T673
Test name
Test status
Simulation time 29417800 ps
CPU time 15.59 seconds
Started May 23 01:30:38 PM PDT 24
Finished May 23 01:30:55 PM PDT 24
Peak memory 275748 kb
Host smart-4a37621c-f36d-4749-a156-7071fa303e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458438476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1458438476
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1373553921
Short name T155
Test name
Test status
Simulation time 48507400 ps
CPU time 21.78 seconds
Started May 23 01:30:35 PM PDT 24
Finished May 23 01:30:59 PM PDT 24
Peak memory 265292 kb
Host smart-d0d64705-2544-4bbf-9c86-c7ce58bf979f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373553921 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1373553921
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1466415936
Short name T890
Test name
Test status
Simulation time 10039420000 ps
CPU time 57.28 seconds
Started May 23 01:30:34 PM PDT 24
Finished May 23 01:31:33 PM PDT 24
Peak memory 269304 kb
Host smart-d8ff1f38-1562-4ad6-a887-bdb0034a4830
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466415936 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1466415936
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1809141838
Short name T171
Test name
Test status
Simulation time 26569900 ps
CPU time 13.43 seconds
Started May 23 01:30:32 PM PDT 24
Finished May 23 01:30:47 PM PDT 24
Peak memory 265016 kb
Host smart-14f05c53-a4e5-4d62-b058-03a555dd652c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809141838 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1809141838
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.4007882401
Short name T745
Test name
Test status
Simulation time 7767640100 ps
CPU time 125.03 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:32:28 PM PDT 24
Peak memory 262592 kb
Host smart-5a3e62b1-8846-404d-a464-c8ff67eebcc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007882401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.4007882401
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.4278401620
Short name T352
Test name
Test status
Simulation time 2074518700 ps
CPU time 132.13 seconds
Started May 23 01:30:24 PM PDT 24
Finished May 23 01:32:38 PM PDT 24
Peak memory 292892 kb
Host smart-90086ace-2a89-4eb0-b329-174ff9aaf148
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278401620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.4278401620
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.98904977
Short name T798
Test name
Test status
Simulation time 5775433800 ps
CPU time 141.92 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 291996 kb
Host smart-79e814ae-f0bb-4dd7-8d51-c158971154a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98904977 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.98904977
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.4257114964
Short name T697
Test name
Test status
Simulation time 11675967100 ps
CPU time 74.91 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:31:38 PM PDT 24
Peak memory 260660 kb
Host smart-94173225-6d86-4b6b-b1d3-6802b43fe8da
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257114964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4
257114964
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1401727456
Short name T693
Test name
Test status
Simulation time 47422700 ps
CPU time 13.55 seconds
Started May 23 01:30:35 PM PDT 24
Finished May 23 01:30:50 PM PDT 24
Peak memory 265204 kb
Host smart-eacf50e0-5e4b-4203-82d3-584eea44c305
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401727456 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1401727456
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.950280907
Short name T82
Test name
Test status
Simulation time 23089948700 ps
CPU time 1303.89 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:52:04 PM PDT 24
Peak memory 274352 kb
Host smart-01ce5131-5fd6-4cca-b39f-c57429a17f8b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950280907 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.950280907
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.284139829
Short name T771
Test name
Test status
Simulation time 158357700 ps
CPU time 130.66 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:32:33 PM PDT 24
Peak memory 259768 kb
Host smart-6ed6c92c-352a-4249-a92c-0ed5269e4837
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284139829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot
p_reset.284139829
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.3165249696
Short name T204
Test name
Test status
Simulation time 560494000 ps
CPU time 217.14 seconds
Started May 23 01:30:21 PM PDT 24
Finished May 23 01:34:00 PM PDT 24
Peak memory 262448 kb
Host smart-cd41fcae-4fc4-4ca9-a994-a1944c9ed2f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165249696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3165249696
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.525399481
Short name T727
Test name
Test status
Simulation time 47358700 ps
CPU time 15 seconds
Started May 23 01:30:34 PM PDT 24
Finished May 23 01:30:51 PM PDT 24
Peak memory 258748 kb
Host smart-a63bbb48-3a71-4269-9e22-331213903770
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525399481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_res
et.525399481
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3148565514
Short name T976
Test name
Test status
Simulation time 45780100 ps
CPU time 126.4 seconds
Started May 23 01:30:19 PM PDT 24
Finished May 23 01:32:26 PM PDT 24
Peak memory 271044 kb
Host smart-3127acf5-29a2-4f57-85f1-23f7e92e5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148565514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3148565514
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.1745222984
Short name T668
Test name
Test status
Simulation time 200718900 ps
CPU time 37.95 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:13 PM PDT 24
Peak memory 274532 kb
Host smart-7c3160a3-a226-4282-85e5-3c2e079e644f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745222984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.1745222984
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2919785933
Short name T472
Test name
Test status
Simulation time 592178300 ps
CPU time 126.55 seconds
Started May 23 01:30:24 PM PDT 24
Finished May 23 01:32:32 PM PDT 24
Peak memory 281648 kb
Host smart-5ac4b3c4-0cf9-4c06-817b-1f1582e0130f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919785933 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2919785933
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.644949302
Short name T96
Test name
Test status
Simulation time 2984652100 ps
CPU time 456.49 seconds
Started May 23 01:30:22 PM PDT 24
Finished May 23 01:38:01 PM PDT 24
Peak memory 309448 kb
Host smart-1be28090-7dfb-46e2-b87b-929dce233aa5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644949302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_rw.644949302
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3634398122
Short name T56
Test name
Test status
Simulation time 54075100 ps
CPU time 29.07 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:04 PM PDT 24
Peak memory 273572 kb
Host smart-1ee4914c-89ac-42e8-9ade-f7b4756299e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634398122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3634398122
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3076223377
Short name T675
Test name
Test status
Simulation time 61560600 ps
CPU time 31.75 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 275508 kb
Host smart-4ba207e8-b524-46c1-aef7-c6a14a9927b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076223377 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.3076223377
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1014750846
Short name T274
Test name
Test status
Simulation time 3765796500 ps
CPU time 74.79 seconds
Started May 23 01:30:32 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 261864 kb
Host smart-22378228-c58c-4b47-9d9d-115599d20947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014750846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1014750846
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2133271079
Short name T583
Test name
Test status
Simulation time 60810000 ps
CPU time 121.71 seconds
Started May 23 01:30:20 PM PDT 24
Finished May 23 01:32:24 PM PDT 24
Peak memory 277032 kb
Host smart-f5d92e50-4b34-4827-96a2-21d04127ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133271079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2133271079
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.3015200711
Short name T645
Test name
Test status
Simulation time 11325980300 ps
CPU time 220.34 seconds
Started May 23 01:30:22 PM PDT 24
Finished May 23 01:34:05 PM PDT 24
Peak memory 265120 kb
Host smart-a3d0883a-2683-4762-87a4-f7b19ab91966
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015200711 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.3015200711
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.4198075989
Short name T1009
Test name
Test status
Simulation time 28072800 ps
CPU time 13.54 seconds
Started May 23 01:30:51 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 264616 kb
Host smart-54f2c6e8-62cc-42cd-94a1-454a394ceaee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198075989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
4198075989
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.337221267
Short name T642
Test name
Test status
Simulation time 14292400 ps
CPU time 16.03 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:30:51 PM PDT 24
Peak memory 275940 kb
Host smart-8b0ef771-1027-4123-a81f-421e243abff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337221267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.337221267
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.165554299
Short name T723
Test name
Test status
Simulation time 12808900 ps
CPU time 21.05 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:30:56 PM PDT 24
Peak memory 265132 kb
Host smart-70902fec-2ea6-4244-9b55-a512d940afd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165554299 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.165554299
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2155812994
Short name T353
Test name
Test status
Simulation time 45008400 ps
CPU time 13.56 seconds
Started May 23 01:30:38 PM PDT 24
Finished May 23 01:30:54 PM PDT 24
Peak memory 265092 kb
Host smart-d40f54bb-4f54-4e1b-b21b-8eb4ab71de92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155812994 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2155812994
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2448819893
Short name T750
Test name
Test status
Simulation time 150193256500 ps
CPU time 863.69 seconds
Started May 23 01:30:37 PM PDT 24
Finished May 23 01:45:02 PM PDT 24
Peak memory 264212 kb
Host smart-cdb5d8da-3f01-434f-8ce2-6c918590f93e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448819893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2448819893
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1749413845
Short name T897
Test name
Test status
Simulation time 25808758200 ps
CPU time 76.82 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:52 PM PDT 24
Peak memory 262460 kb
Host smart-11ca4d4c-7c59-4b56-a5fa-9ab2252358bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749413845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1749413845
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3766542472
Short name T348
Test name
Test status
Simulation time 1563649600 ps
CPU time 248.52 seconds
Started May 23 01:30:34 PM PDT 24
Finished May 23 01:34:44 PM PDT 24
Peak memory 283976 kb
Host smart-2d0d52ad-4bdc-4c56-b31a-e1ede153c01f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766542472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3766542472
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3016813904
Short name T652
Test name
Test status
Simulation time 51208711100 ps
CPU time 313.03 seconds
Started May 23 01:30:36 PM PDT 24
Finished May 23 01:35:51 PM PDT 24
Peak memory 292024 kb
Host smart-68d02354-cddd-4893-8792-2c97ab224c9d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016813904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3016813904
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2894058392
Short name T805
Test name
Test status
Simulation time 1005028100 ps
CPU time 78.31 seconds
Started May 23 01:30:35 PM PDT 24
Finished May 23 01:31:55 PM PDT 24
Peak memory 260808 kb
Host smart-4a59ec95-070e-48bc-bfcf-f0eeef177ed3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894058392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
894058392
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.893617920
Short name T485
Test name
Test status
Simulation time 46105200 ps
CPU time 14.07 seconds
Started May 23 01:30:37 PM PDT 24
Finished May 23 01:30:53 PM PDT 24
Peak memory 265136 kb
Host smart-3a7eefd8-420b-40ec-a847-65979b6761c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893617920 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.893617920
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3245426691
Short name T931
Test name
Test status
Simulation time 10109032700 ps
CPU time 321.68 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:35:56 PM PDT 24
Peak memory 274452 kb
Host smart-a6195151-9a58-49ee-99f5-9ca8ff14fc31
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245426691 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.3245426691
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.964021040
Short name T311
Test name
Test status
Simulation time 140113100 ps
CPU time 110.09 seconds
Started May 23 01:30:37 PM PDT 24
Finished May 23 01:32:29 PM PDT 24
Peak memory 259920 kb
Host smart-6cb314dd-ea90-4dcf-bdc5-14fa85349a6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964021040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ot
p_reset.964021040
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.254207190
Short name T881
Test name
Test status
Simulation time 2980584400 ps
CPU time 383.76 seconds
Started May 23 01:30:35 PM PDT 24
Finished May 23 01:37:01 PM PDT 24
Peak memory 265136 kb
Host smart-41d8d658-84d3-4c7f-80de-ec065b7beae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254207190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.254207190
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.4181412410
Short name T414
Test name
Test status
Simulation time 55487000 ps
CPU time 14.84 seconds
Started May 23 01:30:32 PM PDT 24
Finished May 23 01:30:48 PM PDT 24
Peak memory 265196 kb
Host smart-bfae446f-2000-49f9-9bf3-59ae6edc6542
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181412410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.4181412410
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1803754210
Short name T926
Test name
Test status
Simulation time 59948500 ps
CPU time 33.87 seconds
Started May 23 01:30:35 PM PDT 24
Finished May 23 01:31:10 PM PDT 24
Peak memory 273540 kb
Host smart-bd1d861d-8413-4b62-b918-0fb6deeac96e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803754210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1803754210
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2036641666
Short name T754
Test name
Test status
Simulation time 20068443000 ps
CPU time 503.11 seconds
Started May 23 01:30:34 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 309376 kb
Host smart-4a040f94-f1f7-4e51-9d35-635f68a07ed0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036641666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.2036641666
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.442021016
Short name T889
Test name
Test status
Simulation time 52085600 ps
CPU time 31.56 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 274512 kb
Host smart-755632b5-bbf0-4fa6-b73b-6fcc97cd1da7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442021016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_rw_evict.442021016
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2270966561
Short name T526
Test name
Test status
Simulation time 28197000 ps
CPU time 31.39 seconds
Started May 23 01:30:33 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 275640 kb
Host smart-9736436d-d8cd-45ca-9b0a-5abb2db9c42b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270966561 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2270966561
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2189203555
Short name T691
Test name
Test status
Simulation time 441359400 ps
CPU time 171.21 seconds
Started May 23 01:30:32 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 276700 kb
Host smart-0f31b75c-903c-4957-be30-742165dab581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189203555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2189203555
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1350735262
Short name T1062
Test name
Test status
Simulation time 1981443200 ps
CPU time 176.41 seconds
Started May 23 01:30:27 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 265068 kb
Host smart-451637a2-3801-477b-b3f5-3a42f44beda0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350735262 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.1350735262
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1072470756
Short name T23
Test name
Test status
Simulation time 37366000 ps
CPU time 14.49 seconds
Started May 23 01:27:45 PM PDT 24
Finished May 23 01:28:00 PM PDT 24
Peak memory 264280 kb
Host smart-d62491b2-b48e-44d0-977c-281072f63e7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072470756 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1072470756
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2560262032
Short name T806
Test name
Test status
Simulation time 591603500 ps
CPU time 13.79 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:03 PM PDT 24
Peak memory 265068 kb
Host smart-66d28951-37b3-44e3-88c4-ec0f5432191e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560262032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
560262032
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3098770201
Short name T444
Test name
Test status
Simulation time 34098700 ps
CPU time 15.61 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:05 PM PDT 24
Peak memory 275632 kb
Host smart-671a1996-6b92-49cd-bb9d-be66aa3e97a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098770201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3098770201
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2512171250
Short name T618
Test name
Test status
Simulation time 198751800 ps
CPU time 105.15 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:33 PM PDT 24
Peak memory 281364 kb
Host smart-4b7571a5-ef95-4cc5-91a5-6ee5cef2ae83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512171250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2512171250
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1003853134
Short name T809
Test name
Test status
Simulation time 6047874300 ps
CPU time 340.47 seconds
Started May 23 01:27:43 PM PDT 24
Finished May 23 01:33:24 PM PDT 24
Peak memory 261408 kb
Host smart-0b0e762d-7c2f-4c4b-be82-322eaea49e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003853134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1003853134
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3795961494
Short name T1048
Test name
Test status
Simulation time 76328248000 ps
CPU time 2304.61 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 02:06:17 PM PDT 24
Peak memory 264724 kb
Host smart-72dcdd06-7754-4d1f-a5d0-2e03d402d324
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795961494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3795961494
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.2033107027
Short name T176
Test name
Test status
Simulation time 2813263800 ps
CPU time 2273.17 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 02:05:43 PM PDT 24
Peak memory 264800 kb
Host smart-f92acb14-21ec-4fd2-be09-d7634c80abdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033107027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2033107027
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1559236352
Short name T118
Test name
Test status
Simulation time 5003596900 ps
CPU time 989.96 seconds
Started May 23 01:27:44 PM PDT 24
Finished May 23 01:44:15 PM PDT 24
Peak memory 273200 kb
Host smart-ea33050d-e790-41d8-8ff6-f306854dbed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559236352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1559236352
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.4150750474
Short name T831
Test name
Test status
Simulation time 1839564500 ps
CPU time 24.72 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:13 PM PDT 24
Peak memory 265100 kb
Host smart-8859d208-352c-4010-9685-13bf52173fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150750474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.4150750474
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.901915879
Short name T77
Test name
Test status
Simulation time 179758733800 ps
CPU time 2423.71 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 02:08:13 PM PDT 24
Peak memory 265180 kb
Host smart-9105e542-f24d-4c5d-9021-6ab893ccd6fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901915879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.901915879
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.1686377905
Short name T460
Test name
Test status
Simulation time 65025000 ps
CPU time 90.77 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:29:21 PM PDT 24
Peak memory 265180 kb
Host smart-bbbce890-def9-4e1c-b27e-40f28bad8915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686377905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1686377905
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1864919067
Short name T173
Test name
Test status
Simulation time 10012419300 ps
CPU time 330.78 seconds
Started May 23 01:27:50 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 319400 kb
Host smart-3e37d04d-824d-4a85-a4ac-ec76cbe838ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864919067 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1864919067
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.150212977
Short name T287
Test name
Test status
Simulation time 26348600 ps
CPU time 13.58 seconds
Started May 23 01:27:56 PM PDT 24
Finished May 23 01:28:11 PM PDT 24
Peak memory 265232 kb
Host smart-9df5ca71-10f1-443a-9a5f-22d3238188d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150212977 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.150212977
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.4279522008
Short name T88
Test name
Test status
Simulation time 188128793800 ps
CPU time 1951.77 seconds
Started May 23 01:27:54 PM PDT 24
Finished May 23 02:00:27 PM PDT 24
Peak memory 263884 kb
Host smart-3335e3a7-0c90-4726-a6da-3c304f0ecb3e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279522008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.4279522008
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3399439708
Short name T87
Test name
Test status
Simulation time 140187883800 ps
CPU time 888.11 seconds
Started May 23 01:27:44 PM PDT 24
Finished May 23 01:42:33 PM PDT 24
Peak memory 262716 kb
Host smart-67c7f0cb-6a5d-4043-9ad8-9befbe592e49
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399439708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3399439708
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2062117690
Short name T574
Test name
Test status
Simulation time 3617490500 ps
CPU time 126.57 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:56 PM PDT 24
Peak memory 262312 kb
Host smart-79bb3a4e-76e3-4516-8153-f9572cc4e6cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062117690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2062117690
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3948003210
Short name T605
Test name
Test status
Simulation time 52257834400 ps
CPU time 144.52 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:30:17 PM PDT 24
Peak memory 292228 kb
Host smart-9e494d64-1e3b-4e3a-bf67-b9c61a5e2883
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948003210 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3948003210
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2455443519
Short name T800
Test name
Test status
Simulation time 46987805300 ps
CPU time 252.78 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:32:05 PM PDT 24
Peak memory 260168 kb
Host smart-a4bfafad-88ae-4d53-a74b-5ea3d25866d3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245
5443519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2455443519
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.2787204522
Short name T631
Test name
Test status
Simulation time 4272660400 ps
CPU time 64.08 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 01:28:54 PM PDT 24
Peak memory 260736 kb
Host smart-98ad055d-c0bb-4ae1-9f69-f909189cf028
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787204522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2787204522
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1667148907
Short name T623
Test name
Test status
Simulation time 25533700 ps
CPU time 13.54 seconds
Started May 23 01:27:55 PM PDT 24
Finished May 23 01:28:10 PM PDT 24
Peak memory 265144 kb
Host smart-e27a4a6b-d45f-4b82-98b2-d88e99cf6540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667148907 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1667148907
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.608508343
Short name T165
Test name
Test status
Simulation time 993077500 ps
CPU time 72.23 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:02 PM PDT 24
Peak memory 259888 kb
Host smart-36083a19-c3ca-49e7-87c7-b618e3ba1438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608508343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.608508343
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.3035742095
Short name T114
Test name
Test status
Simulation time 17632738400 ps
CPU time 248.34 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:31:56 PM PDT 24
Peak memory 274012 kb
Host smart-b98bc5c7-4ee8-4baa-8c3e-84823bd2cb23
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035742095 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.3035742095
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3023086746
Short name T324
Test name
Test status
Simulation time 39793500 ps
CPU time 130.71 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:30:03 PM PDT 24
Peak memory 264692 kb
Host smart-a1706eb4-09cc-4d7d-a5a2-832467859f55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023086746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3023086746
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.2303107729
Short name T1066
Test name
Test status
Simulation time 2423393200 ps
CPU time 185.66 seconds
Started May 23 01:27:54 PM PDT 24
Finished May 23 01:31:01 PM PDT 24
Peak memory 289936 kb
Host smart-22dcb5ea-d162-4e53-9f23-ee64f63bde2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303107729 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2303107729
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.130045588
Short name T1016
Test name
Test status
Simulation time 21617700 ps
CPU time 14.23 seconds
Started May 23 01:27:50 PM PDT 24
Finished May 23 01:28:06 PM PDT 24
Peak memory 276820 kb
Host smart-58acc9ff-c958-4f83-95c0-e89b53756369
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=130045588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.130045588
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4120439405
Short name T465
Test name
Test status
Simulation time 49028200 ps
CPU time 69.71 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:29:08 PM PDT 24
Peak memory 262560 kb
Host smart-4817a5af-36bd-472c-a0ac-2889719ba607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120439405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4120439405
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.171456937
Short name T54
Test name
Test status
Simulation time 903005000 ps
CPU time 23.02 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:28:11 PM PDT 24
Peak memory 262112 kb
Host smart-5eaa135a-387f-4c4c-9b80-6591954c3dac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171456937 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.171456937
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3072159450
Short name T709
Test name
Test status
Simulation time 10001329900 ps
CPU time 180.55 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 01:30:51 PM PDT 24
Peak memory 259988 kb
Host smart-8c40f5ea-434c-43af-aec5-6c308f8df119
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072159450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3072159450
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.679886631
Short name T629
Test name
Test status
Simulation time 497036000 ps
CPU time 1377.59 seconds
Started May 23 01:27:43 PM PDT 24
Finished May 23 01:50:41 PM PDT 24
Peak memory 288024 kb
Host smart-99241caf-41a8-4374-b130-3d32e24f0715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679886631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.679886631
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2144315524
Short name T989
Test name
Test status
Simulation time 88840200 ps
CPU time 99.14 seconds
Started May 23 01:27:50 PM PDT 24
Finished May 23 01:29:30 PM PDT 24
Peak memory 265220 kb
Host smart-b6799beb-477e-4530-a9f9-b37747b0db7a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2144315524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2144315524
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.1236943689
Short name T898
Test name
Test status
Simulation time 115772400 ps
CPU time 30.53 seconds
Started May 23 01:27:45 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 278424 kb
Host smart-f34e6653-ffb6-41b3-b3c2-4dcf487eaa9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236943689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.1236943689
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1135731200
Short name T923
Test name
Test status
Simulation time 765099000 ps
CPU time 38.9 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:27 PM PDT 24
Peak memory 273444 kb
Host smart-1956b292-c772-43a5-bb3e-5f17eeb11042
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135731200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1135731200
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.287298605
Short name T655
Test name
Test status
Simulation time 46330500 ps
CPU time 21.65 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:28:10 PM PDT 24
Peak memory 265336 kb
Host smart-7f96e06b-690f-4b95-a15a-2ab66a615ff0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287298605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_read_word_sweep_serr.287298605
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.151565948
Short name T1041
Test name
Test status
Simulation time 601694400 ps
CPU time 114.27 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:44 PM PDT 24
Peak memory 281644 kb
Host smart-c9fb0d83-f7ff-4301-b6b9-77b9d23d040b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151565948 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_ro.151565948
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1609742545
Short name T933
Test name
Test status
Simulation time 2045550900 ps
CPU time 115.99 seconds
Started May 23 01:27:46 PM PDT 24
Finished May 23 01:29:43 PM PDT 24
Peak memory 281596 kb
Host smart-3e46fc06-d69a-40c6-881e-5986a1da4f84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1609742545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1609742545
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3507796869
Short name T835
Test name
Test status
Simulation time 2320204500 ps
CPU time 123.83 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:29:55 PM PDT 24
Peak memory 294380 kb
Host smart-8bdeb666-bdf5-467f-b29c-8aa78a1663e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507796869 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3507796869
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.261662987
Short name T815
Test name
Test status
Simulation time 32545877300 ps
CPU time 627.62 seconds
Started May 23 01:27:55 PM PDT 24
Finished May 23 01:38:24 PM PDT 24
Peak memory 309592 kb
Host smart-bbc7f7b3-5567-48d7-9bf9-075276cdc5df
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261662987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_rw.261662987
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.1056593993
Short name T1058
Test name
Test status
Simulation time 29841874700 ps
CPU time 620.44 seconds
Started May 23 01:27:52 PM PDT 24
Finished May 23 01:38:14 PM PDT 24
Peak memory 341444 kb
Host smart-0171a0d5-721d-4a31-b364-c7c2e434fab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056593993 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.1056593993
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.197426751
Short name T695
Test name
Test status
Simulation time 71223100 ps
CPU time 31.22 seconds
Started May 23 01:27:56 PM PDT 24
Finished May 23 01:28:28 PM PDT 24
Peak memory 274584 kb
Host smart-1399815c-0234-4474-ada6-a11ba55d0156
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197426751 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.197426751
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3142860775
Short name T698
Test name
Test status
Simulation time 5136331600 ps
CPU time 589.13 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:37:40 PM PDT 24
Peak memory 320228 kb
Host smart-60fbe640-af0a-4065-8a3b-ac772721d8fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142860775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.3142860775
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.473506745
Short name T16
Test name
Test status
Simulation time 3059973300 ps
CPU time 4729.84 seconds
Started May 23 01:27:53 PM PDT 24
Finished May 23 02:46:44 PM PDT 24
Peak memory 289200 kb
Host smart-4f8ad457-91fd-4436-8699-bba9f7832382
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473506745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.473506745
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.2845342400
Short name T275
Test name
Test status
Simulation time 1037495100 ps
CPU time 64.27 seconds
Started May 23 01:27:50 PM PDT 24
Finished May 23 01:28:56 PM PDT 24
Peak memory 263036 kb
Host smart-1dd3f495-fda0-49cb-82a1-e9c70b4dadcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845342400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2845342400
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.4014950319
Short name T463
Test name
Test status
Simulation time 724903900 ps
CPU time 77.28 seconds
Started May 23 01:27:52 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 265300 kb
Host smart-dd25a085-95cd-42eb-a59a-503edf761648
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014950319 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.4014950319
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.1629375627
Short name T262
Test name
Test status
Simulation time 1567494400 ps
CPU time 75.55 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:04 PM PDT 24
Peak memory 273800 kb
Host smart-c5320e10-dc74-4530-8a61-29a038aa04a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629375627 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.1629375627
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2786851978
Short name T836
Test name
Test status
Simulation time 21011800 ps
CPU time 51.58 seconds
Started May 23 01:27:55 PM PDT 24
Finished May 23 01:28:47 PM PDT 24
Peak memory 270660 kb
Host smart-ec44d770-ebb1-4037-bd80-13cd1d3a05b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786851978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2786851978
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1370014781
Short name T509
Test name
Test status
Simulation time 29701900 ps
CPU time 26.22 seconds
Started May 23 01:27:52 PM PDT 24
Finished May 23 01:28:20 PM PDT 24
Peak memory 258964 kb
Host smart-416d8d25-13a5-4330-966f-6ba9798052e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370014781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1370014781
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.4155101152
Short name T819
Test name
Test status
Simulation time 1704635500 ps
CPU time 858.49 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:42:09 PM PDT 24
Peak memory 284184 kb
Host smart-af5a5bb1-757a-4004-993b-7eeaaaa1912c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155101152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.4155101152
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1143927208
Short name T752
Test name
Test status
Simulation time 69638300 ps
CPU time 24.06 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:28:17 PM PDT 24
Peak memory 261624 kb
Host smart-1cd1a494-f93b-4fff-8baf-0cb6dd7c0233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143927208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1143927208
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.162986489
Short name T235
Test name
Test status
Simulation time 2671035800 ps
CPU time 214.45 seconds
Started May 23 01:27:45 PM PDT 24
Finished May 23 01:31:20 PM PDT 24
Peak memory 264160 kb
Host smart-bfba11e3-2bba-4e2d-9625-cc62b8141767
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162986489 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_wo.162986489
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.621569720
Short name T234
Test name
Test status
Simulation time 82933700 ps
CPU time 15.13 seconds
Started May 23 01:27:58 PM PDT 24
Finished May 23 01:28:14 PM PDT 24
Peak memory 265224 kb
Host smart-32152546-ed71-4dc1-a9c9-87367de0c570
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621569720 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.621569720
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.4235145822
Short name T990
Test name
Test status
Simulation time 127746300 ps
CPU time 13.83 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:31:08 PM PDT 24
Peak memory 265080 kb
Host smart-412be111-e653-49c9-b32b-779805f1ee5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235145822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
4235145822
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.3768097957
Short name T547
Test name
Test status
Simulation time 14573800 ps
CPU time 15.7 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:31:10 PM PDT 24
Peak memory 275200 kb
Host smart-181f9c81-27c9-4fce-be9e-a3d85aa3d218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768097957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3768097957
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.1189566946
Short name T1040
Test name
Test status
Simulation time 29154100 ps
CPU time 20.76 seconds
Started May 23 01:30:53 PM PDT 24
Finished May 23 01:31:16 PM PDT 24
Peak memory 265176 kb
Host smart-5f1d69f7-b038-4416-a7d7-5b7bb6f66cab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189566946 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.1189566946
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2970713631
Short name T868
Test name
Test status
Simulation time 12663372900 ps
CPU time 117.24 seconds
Started May 23 01:30:53 PM PDT 24
Finished May 23 01:32:53 PM PDT 24
Peak memory 262516 kb
Host smart-8a666aee-4652-423d-b184-00d98cc3328e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970713631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2970713631
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.215556149
Short name T1018
Test name
Test status
Simulation time 4070566500 ps
CPU time 215.74 seconds
Started May 23 01:30:54 PM PDT 24
Finished May 23 01:34:32 PM PDT 24
Peak memory 284184 kb
Host smart-8b85aaa1-e528-4140-b8bc-4d3fcba47b1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215556149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flas
h_ctrl_intr_rd.215556149
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2008248208
Short name T661
Test name
Test status
Simulation time 10136762600 ps
CPU time 158.28 seconds
Started May 23 01:30:53 PM PDT 24
Finished May 23 01:33:34 PM PDT 24
Peak memory 291972 kb
Host smart-f0c306f9-8278-4bc8-b773-c8685c359cfa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008248208 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2008248208
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2973172848
Short name T944
Test name
Test status
Simulation time 43059100 ps
CPU time 130.76 seconds
Started May 23 01:30:53 PM PDT 24
Finished May 23 01:33:07 PM PDT 24
Peak memory 259700 kb
Host smart-bd0d7967-4f9b-4958-a56b-0dd4d4510946
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973172848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2973172848
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3377686261
Short name T373
Test name
Test status
Simulation time 70264500 ps
CPU time 13.66 seconds
Started May 23 01:30:55 PM PDT 24
Finished May 23 01:31:11 PM PDT 24
Peak memory 265136 kb
Host smart-7d863a84-576e-432c-b882-77d09d8abb71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377686261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.3377686261
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2379768989
Short name T334
Test name
Test status
Simulation time 29812400 ps
CPU time 31.2 seconds
Started May 23 01:30:51 PM PDT 24
Finished May 23 01:31:24 PM PDT 24
Peak memory 274756 kb
Host smart-3fc8d2ae-2ef6-4a5f-b7c9-a528712649f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379768989 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2379768989
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.3952168656
Short name T1031
Test name
Test status
Simulation time 42714200 ps
CPU time 98 seconds
Started May 23 01:30:50 PM PDT 24
Finished May 23 01:32:30 PM PDT 24
Peak memory 275444 kb
Host smart-feca1fd5-4cdd-4ea3-aad4-4a2d2fd67e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952168656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3952168656
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.1373886269
Short name T420
Test name
Test status
Simulation time 89094500 ps
CPU time 13.48 seconds
Started May 23 01:30:51 PM PDT 24
Finished May 23 01:31:07 PM PDT 24
Peak memory 265156 kb
Host smart-eacf50f8-a88a-41e5-aabc-ff756d5e019f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373886269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
1373886269
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.1625900078
Short name T613
Test name
Test status
Simulation time 18188800 ps
CPU time 15.8 seconds
Started May 23 01:30:55 PM PDT 24
Finished May 23 01:31:13 PM PDT 24
Peak memory 275120 kb
Host smart-cdf5f52c-5b30-4c04-a796-4cb6619e0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625900078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1625900078
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2032779865
Short name T940
Test name
Test status
Simulation time 2469343500 ps
CPU time 42.44 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:31:37 PM PDT 24
Peak memory 262428 kb
Host smart-94f04c17-3d00-4dfc-a289-1cc5d3196210
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032779865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2032779865
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.3705344149
Short name T955
Test name
Test status
Simulation time 723710200 ps
CPU time 130.66 seconds
Started May 23 01:30:44 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 294228 kb
Host smart-d3c4f0d4-d238-491e-9c08-52f06ab4b8ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705344149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.3705344149
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.467406782
Short name T916
Test name
Test status
Simulation time 24009380300 ps
CPU time 273.55 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:35:28 PM PDT 24
Peak memory 291124 kb
Host smart-ec100b5d-1d08-45a8-ae37-37d65ffe50dd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467406782 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.467406782
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2893359877
Short name T142
Test name
Test status
Simulation time 161724800 ps
CPU time 131.45 seconds
Started May 23 01:30:54 PM PDT 24
Finished May 23 01:33:08 PM PDT 24
Peak memory 261072 kb
Host smart-6ba62ea6-c5b2-4add-b078-60f25179bcd4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893359877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2893359877
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3063898001
Short name T830
Test name
Test status
Simulation time 8295839900 ps
CPU time 185.9 seconds
Started May 23 01:30:52 PM PDT 24
Finished May 23 01:34:01 PM PDT 24
Peak memory 265164 kb
Host smart-1b1381ab-c0e4-4e3d-9830-8d8aaf056a4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063898001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3063898001
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.4158025635
Short name T566
Test name
Test status
Simulation time 5649235600 ps
CPU time 71.15 seconds
Started May 23 01:30:54 PM PDT 24
Finished May 23 01:32:07 PM PDT 24
Peak memory 262992 kb
Host smart-92702ce7-c61d-4d06-8b4b-27d32fb321b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158025635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.4158025635
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2044191888
Short name T323
Test name
Test status
Simulation time 38107500 ps
CPU time 174.14 seconds
Started May 23 01:30:54 PM PDT 24
Finished May 23 01:33:51 PM PDT 24
Peak memory 277004 kb
Host smart-68fb0d5d-9b65-42df-9840-634612f8f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044191888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2044191888
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.300677062
Short name T1022
Test name
Test status
Simulation time 83084200 ps
CPU time 13.7 seconds
Started May 23 01:31:02 PM PDT 24
Finished May 23 01:31:16 PM PDT 24
Peak memory 265132 kb
Host smart-deaf6329-2b84-4abe-aa24-804712368bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300677062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.300677062
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3478265851
Short name T617
Test name
Test status
Simulation time 14545600 ps
CPU time 16.05 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:16 PM PDT 24
Peak memory 275160 kb
Host smart-fc73367d-427a-4fa1-8fd1-0802e7ff967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478265851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3478265851
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.845966456
Short name T696
Test name
Test status
Simulation time 10892000 ps
CPU time 21.9 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:31:24 PM PDT 24
Peak memory 273568 kb
Host smart-28d830aa-c91d-4145-afb7-149f8426f2e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845966456 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.845966456
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3017790537
Short name T824
Test name
Test status
Simulation time 2309611000 ps
CPU time 157.43 seconds
Started May 23 01:30:45 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 262548 kb
Host smart-7a52a6c5-e917-436b-816f-d002bd79f54f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017790537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.3017790537
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3046611434
Short name T259
Test name
Test status
Simulation time 3971081300 ps
CPU time 213.54 seconds
Started May 23 01:30:45 PM PDT 24
Finished May 23 01:34:19 PM PDT 24
Peak memory 290004 kb
Host smart-39cf33a9-8608-49db-83a3-439110b1ba92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046611434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3046611434
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2843943802
Short name T587
Test name
Test status
Simulation time 22764069800 ps
CPU time 259.5 seconds
Started May 23 01:30:59 PM PDT 24
Finished May 23 01:35:20 PM PDT 24
Peak memory 284480 kb
Host smart-0548f030-25be-46db-a137-a3127baeb896
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843943802 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2843943802
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.478637495
Short name T545
Test name
Test status
Simulation time 87897800 ps
CPU time 115.28 seconds
Started May 23 01:30:51 PM PDT 24
Finished May 23 01:32:49 PM PDT 24
Peak memory 261128 kb
Host smart-f9e992f9-abe1-4766-a3bb-482b247bc665
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478637495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot
p_reset.478637495
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3039886113
Short name T573
Test name
Test status
Simulation time 40787600 ps
CPU time 13.63 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:14 PM PDT 24
Peak memory 265064 kb
Host smart-6f473bad-3137-4ebb-8c89-adc7a0e3ea50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039886113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3039886113
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.3824885925
Short name T711
Test name
Test status
Simulation time 106979700 ps
CPU time 32.1 seconds
Started May 23 01:30:59 PM PDT 24
Finished May 23 01:31:33 PM PDT 24
Peak memory 267464 kb
Host smart-1cf199ef-cb93-43e3-8fde-304984508b64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824885925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.3824885925
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.565501579
Short name T987
Test name
Test status
Simulation time 439684500 ps
CPU time 55.61 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:55 PM PDT 24
Peak memory 263160 kb
Host smart-95bda638-c858-4b18-877f-4ea4a92a692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565501579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.565501579
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3771153118
Short name T535
Test name
Test status
Simulation time 177453100 ps
CPU time 123.1 seconds
Started May 23 01:30:50 PM PDT 24
Finished May 23 01:32:55 PM PDT 24
Peak memory 277080 kb
Host smart-4d4256e1-8b02-45b2-9f09-2be3219e119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771153118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3771153118
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.324778548
Short name T454
Test name
Test status
Simulation time 45994700 ps
CPU time 13.81 seconds
Started May 23 01:30:57 PM PDT 24
Finished May 23 01:31:13 PM PDT 24
Peak memory 265164 kb
Host smart-1a4ad5fa-5050-4177-8d3d-cad986819751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324778548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.324778548
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2146540145
Short name T744
Test name
Test status
Simulation time 49978900 ps
CPU time 13.32 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:31:15 PM PDT 24
Peak memory 275048 kb
Host smart-c3d537bd-b270-4227-b97e-fdabfba9925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146540145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2146540145
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2429521147
Short name T1010
Test name
Test status
Simulation time 15849200 ps
CPU time 22.38 seconds
Started May 23 01:31:01 PM PDT 24
Finished May 23 01:31:25 PM PDT 24
Peak memory 265296 kb
Host smart-d18c586d-ca4c-404b-9988-ec3e8f8a7af4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429521147 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2429521147
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1998616089
Short name T1049
Test name
Test status
Simulation time 729689100 ps
CPU time 34.59 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:34 PM PDT 24
Peak memory 262672 kb
Host smart-a0ef0e71-5e98-4abc-b9ee-42481aeb95f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998616089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1998616089
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3855538200
Short name T269
Test name
Test status
Simulation time 3235859000 ps
CPU time 240.32 seconds
Started May 23 01:31:03 PM PDT 24
Finished May 23 01:35:04 PM PDT 24
Peak memory 283940 kb
Host smart-ad87fac3-38ec-483c-a7b8-9b06f9b42ba3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855538200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3855538200
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2244394823
Short name T462
Test name
Test status
Simulation time 5570597000 ps
CPU time 136.16 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:33:18 PM PDT 24
Peak memory 292004 kb
Host smart-470f708d-3f27-4475-89a3-09b20c368695
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244394823 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2244394823
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.2345085993
Short name T638
Test name
Test status
Simulation time 42892300 ps
CPU time 13.63 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:13 PM PDT 24
Peak memory 258664 kb
Host smart-e0eea945-0118-4ce9-baf2-f5e8f714cde7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345085993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.2345085993
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.3087235545
Short name T1045
Test name
Test status
Simulation time 28409500 ps
CPU time 31.79 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:32 PM PDT 24
Peak memory 274500 kb
Host smart-79f82fa0-cd99-467d-9096-ad2ceaba9f27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087235545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.3087235545
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1902604379
Short name T982
Test name
Test status
Simulation time 1201207900 ps
CPU time 66.69 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:32:07 PM PDT 24
Peak memory 262944 kb
Host smart-d17607ac-55fd-4646-a6f6-871877192d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902604379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1902604379
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.4226989302
Short name T233
Test name
Test status
Simulation time 250167700 ps
CPU time 191.91 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:34:14 PM PDT 24
Peak memory 281408 kb
Host smart-339ff576-48f4-43ba-8812-d2cfba040f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226989302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.4226989302
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2736685886
Short name T582
Test name
Test status
Simulation time 23083100 ps
CPU time 13.4 seconds
Started May 23 01:31:26 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 265144 kb
Host smart-8bd1272c-f392-4ee0-8663-8cd5662e4a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736685886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2736685886
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3811900387
Short name T874
Test name
Test status
Simulation time 20112200 ps
CPU time 15.77 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:31:28 PM PDT 24
Peak memory 275136 kb
Host smart-4589e316-30e2-4be6-90db-1f0368e36757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811900387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3811900387
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1566591918
Short name T920
Test name
Test status
Simulation time 818755600 ps
CPU time 42.77 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:43 PM PDT 24
Peak memory 262612 kb
Host smart-249e3c7e-0e40-4dee-ab59-cdc18b1feae0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566591918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1566591918
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.802476815
Short name T1083
Test name
Test status
Simulation time 682987700 ps
CPU time 134.6 seconds
Started May 23 01:31:03 PM PDT 24
Finished May 23 01:33:18 PM PDT 24
Peak memory 284712 kb
Host smart-99b92ac0-9294-4b50-b187-fb300189b82e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802476815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.802476815
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.4124843543
Short name T947
Test name
Test status
Simulation time 52626375800 ps
CPU time 318.99 seconds
Started May 23 01:30:57 PM PDT 24
Finished May 23 01:36:18 PM PDT 24
Peak memory 293228 kb
Host smart-07eb4b29-93ac-463a-87ee-4e0c39f59fcf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124843543 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.4124843543
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.367997082
Short name T1014
Test name
Test status
Simulation time 122442200 ps
CPU time 134.4 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:33:16 PM PDT 24
Peak memory 260912 kb
Host smart-f14fe4a3-38b0-400f-a39f-dd9e1642f61d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367997082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.367997082
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2150763820
Short name T949
Test name
Test status
Simulation time 21671400 ps
CPU time 13.67 seconds
Started May 23 01:30:57 PM PDT 24
Finished May 23 01:31:13 PM PDT 24
Peak memory 265128 kb
Host smart-afee34b6-0135-4746-a021-6d310a8f9f7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150763820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.2150763820
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.154187439
Short name T1087
Test name
Test status
Simulation time 235071500 ps
CPU time 31.15 seconds
Started May 23 01:30:58 PM PDT 24
Finished May 23 01:31:31 PM PDT 24
Peak memory 273608 kb
Host smart-f8569711-b4b2-499a-9e69-acf541cc7d51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154187439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.154187439
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.745063061
Short name T1005
Test name
Test status
Simulation time 29735500 ps
CPU time 32.42 seconds
Started May 23 01:31:03 PM PDT 24
Finished May 23 01:31:36 PM PDT 24
Peak memory 274892 kb
Host smart-4a129bfd-fb41-4f59-9112-cf849be0b41e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745063061 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.745063061
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3704175096
Short name T1042
Test name
Test status
Simulation time 9504970700 ps
CPU time 76.41 seconds
Started May 23 01:31:09 PM PDT 24
Finished May 23 01:32:28 PM PDT 24
Peak memory 263220 kb
Host smart-7010adf1-76e1-4663-a803-8ac92550c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704175096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3704175096
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.340029211
Short name T1032
Test name
Test status
Simulation time 31256100 ps
CPU time 75.98 seconds
Started May 23 01:31:00 PM PDT 24
Finished May 23 01:32:18 PM PDT 24
Peak memory 276168 kb
Host smart-ea939a8b-2280-4c4e-8a3f-e70d1ce2c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340029211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.340029211
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.1137743738
Short name T536
Test name
Test status
Simulation time 85466800 ps
CPU time 14.27 seconds
Started May 23 01:31:12 PM PDT 24
Finished May 23 01:31:28 PM PDT 24
Peak memory 265048 kb
Host smart-1a538784-1552-4040-8598-8bf0de572af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137743738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
1137743738
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.3443625513
Short name T674
Test name
Test status
Simulation time 16828900 ps
CPU time 13.39 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:31:25 PM PDT 24
Peak memory 275580 kb
Host smart-8ea99eff-01c9-4c98-be2c-b3fa26d96976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443625513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.3443625513
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.864436054
Short name T174
Test name
Test status
Simulation time 39832700 ps
CPU time 20.58 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:31:34 PM PDT 24
Peak memory 265284 kb
Host smart-bcd3a4b2-59ae-4f64-a3e5-6bf84f03b7dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864436054 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.864436054
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3273217807
Short name T970
Test name
Test status
Simulation time 19604542600 ps
CPU time 157.99 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:33:51 PM PDT 24
Peak memory 262504 kb
Host smart-9b3bdd66-63f7-41d5-b339-ff78091e6995
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273217807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.3273217807
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.288874858
Short name T1047
Test name
Test status
Simulation time 23918078000 ps
CPU time 270.64 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:35:43 PM PDT 24
Peak memory 292260 kb
Host smart-addf3001-d5b1-4d29-98de-75305231f14e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288874858 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.288874858
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2996536877
Short name T699
Test name
Test status
Simulation time 76732500 ps
CPU time 109.99 seconds
Started May 23 01:31:26 PM PDT 24
Finished May 23 01:33:17 PM PDT 24
Peak memory 260104 kb
Host smart-b627911c-3ed7-4122-ab81-dbe5fee6ec1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996536877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2996536877
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3397033757
Short name T558
Test name
Test status
Simulation time 19526400 ps
CPU time 13.4 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:31:26 PM PDT 24
Peak memory 265196 kb
Host smart-330cef0f-bd20-46a1-b68e-04edf55dd085
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397033757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3397033757
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.285762829
Short name T441
Test name
Test status
Simulation time 70638000 ps
CPU time 31.71 seconds
Started May 23 01:31:12 PM PDT 24
Finished May 23 01:31:46 PM PDT 24
Peak memory 274592 kb
Host smart-2d80e4f0-d6bc-45ff-9453-e6712cbb4e00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285762829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_rw_evict.285762829
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2510761255
Short name T337
Test name
Test status
Simulation time 106055500 ps
CPU time 29.11 seconds
Started May 23 01:31:09 PM PDT 24
Finished May 23 01:31:40 PM PDT 24
Peak memory 274888 kb
Host smart-0c504af1-624e-4ad3-971b-6330dc8a8588
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510761255 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2510761255
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1570256613
Short name T466
Test name
Test status
Simulation time 3772997500 ps
CPU time 68.41 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:32:34 PM PDT 24
Peak memory 262816 kb
Host smart-041a2bf6-ebe6-47a7-8e8b-294ab0aa22fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570256613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1570256613
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.4033465849
Short name T539
Test name
Test status
Simulation time 30476800 ps
CPU time 119.64 seconds
Started May 23 01:31:13 PM PDT 24
Finished May 23 01:33:14 PM PDT 24
Peak memory 275676 kb
Host smart-66b6d993-584d-4100-92b8-231dd08538f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033465849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.4033465849
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.637356480
Short name T667
Test name
Test status
Simulation time 79657600 ps
CPU time 13.89 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:31:27 PM PDT 24
Peak memory 265148 kb
Host smart-9df7614b-0c7e-404a-b4fa-46fec6f1e15a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637356480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.637356480
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.3825564584
Short name T981
Test name
Test status
Simulation time 22570600 ps
CPU time 15.72 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 275948 kb
Host smart-279c408a-51d1-43ff-ba9c-dd47dc40fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825564584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3825564584
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3078169407
Short name T1029
Test name
Test status
Simulation time 84177200 ps
CPU time 21.79 seconds
Started May 23 01:31:12 PM PDT 24
Finished May 23 01:31:36 PM PDT 24
Peak memory 272956 kb
Host smart-f39d54aa-d921-4473-b3a3-cdc820dd5b35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078169407 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3078169407
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.1415366693
Short name T321
Test name
Test status
Simulation time 4849401600 ps
CPU time 140.81 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:33:34 PM PDT 24
Peak memory 262532 kb
Host smart-0c6e3120-8443-4566-9e34-8b1241e4d370
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415366693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.1415366693
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3272805542
Short name T266
Test name
Test status
Simulation time 10670280700 ps
CPU time 175.85 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:34:09 PM PDT 24
Peak memory 289960 kb
Host smart-773309bc-ac69-496e-92fe-41247cc964df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272805542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3272805542
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.4134367043
Short name T917
Test name
Test status
Simulation time 22297022100 ps
CPU time 266.87 seconds
Started May 23 01:31:08 PM PDT 24
Finished May 23 01:35:37 PM PDT 24
Peak memory 284396 kb
Host smart-253dcbcd-cb8d-4d17-ba7b-77e4a28634b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134367043 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.4134367043
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.196404999
Short name T449
Test name
Test status
Simulation time 41886500 ps
CPU time 131.16 seconds
Started May 23 01:31:26 PM PDT 24
Finished May 23 01:33:39 PM PDT 24
Peak memory 261100 kb
Host smart-e3a4e46a-7e7d-40fd-80f8-2545fe4a320b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196404999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.196404999
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2813980327
Short name T425
Test name
Test status
Simulation time 10704956100 ps
CPU time 186.61 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:34:20 PM PDT 24
Peak memory 259152 kb
Host smart-d7382256-0f69-442d-881f-6124699baa8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813980327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2813980327
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.350939555
Short name T942
Test name
Test status
Simulation time 32059400 ps
CPU time 29.27 seconds
Started May 23 01:31:12 PM PDT 24
Finished May 23 01:31:43 PM PDT 24
Peak memory 267392 kb
Host smart-68d0202d-a39d-465a-8fc8-57b63466c494
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350939555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_rw_evict.350939555
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3200243102
Short name T742
Test name
Test status
Simulation time 82608000 ps
CPU time 31.36 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:57 PM PDT 24
Peak memory 275644 kb
Host smart-bc2c9b32-5599-4e2f-bfd4-610b299ca8be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200243102 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3200243102
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2534833649
Short name T522
Test name
Test status
Simulation time 9341277200 ps
CPU time 84.77 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:32:39 PM PDT 24
Peak memory 262456 kb
Host smart-b3bc11f0-668c-4797-bc65-63471bc9fa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534833649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2534833649
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.409426162
Short name T438
Test name
Test status
Simulation time 111211800 ps
CPU time 122.4 seconds
Started May 23 01:31:11 PM PDT 24
Finished May 23 01:33:16 PM PDT 24
Peak memory 276760 kb
Host smart-1ccb32de-65f0-4b83-a34d-d598fa957422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409426162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.409426162
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1024356890
Short name T791
Test name
Test status
Simulation time 56101300 ps
CPU time 13.8 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:31:39 PM PDT 24
Peak memory 265184 kb
Host smart-1252f2c5-4abc-4fde-889f-b62a108d14f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024356890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1024356890
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2568360201
Short name T808
Test name
Test status
Simulation time 47130500 ps
CPU time 16.16 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:31:40 PM PDT 24
Peak memory 275688 kb
Host smart-dba72d0c-4823-41aa-a107-d60a5d3baf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568360201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2568360201
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.1497444431
Short name T153
Test name
Test status
Simulation time 27985500 ps
CPU time 20.87 seconds
Started May 23 01:31:22 PM PDT 24
Finished May 23 01:31:44 PM PDT 24
Peak memory 265300 kb
Host smart-1dc239d0-c2a0-4580-ac4f-1d0b3f66c401
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497444431 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.1497444431
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2301036671
Short name T1026
Test name
Test status
Simulation time 1625889800 ps
CPU time 41.7 seconds
Started May 23 01:31:10 PM PDT 24
Finished May 23 01:31:54 PM PDT 24
Peak memory 262544 kb
Host smart-26e24c7a-2f3a-4db0-8a0b-df94883bf3e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301036671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.2301036671
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3411613527
Short name T219
Test name
Test status
Simulation time 2196507800 ps
CPU time 156.65 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:34:00 PM PDT 24
Peak memory 293164 kb
Host smart-01e3845c-e8ba-414e-9c20-bc2b554da2b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411613527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3411613527
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3247171195
Short name T518
Test name
Test status
Simulation time 12030641500 ps
CPU time 147.32 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:33:52 PM PDT 24
Peak memory 291772 kb
Host smart-5ef28539-2e9c-4b07-a4e5-91a4a4f59037
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247171195 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3247171195
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.3251909829
Short name T622
Test name
Test status
Simulation time 37955600 ps
CPU time 129.67 seconds
Started May 23 01:31:13 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 259672 kb
Host smart-f17f2dc8-9074-4c19-9c56-055fc5f8da45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251909829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.3251909829
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.525927
Short name T374
Test name
Test status
Simulation time 12513637900 ps
CPU time 163.45 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:34:10 PM PDT 24
Peak memory 259880 kb
Host smart-08a241c1-e073-4e9a-af91-4978e31921ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.525927
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.980248233
Short name T461
Test name
Test status
Simulation time 74438400 ps
CPU time 31.77 seconds
Started May 23 01:31:27 PM PDT 24
Finished May 23 01:32:00 PM PDT 24
Peak memory 273584 kb
Host smart-7ce580af-3a9f-4679-9a56-4a146b3eb7ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980248233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.980248233
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2883198349
Short name T258
Test name
Test status
Simulation time 67851000 ps
CPU time 32.12 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:31:59 PM PDT 24
Peak memory 274904 kb
Host smart-761bac1e-8eba-4719-8489-73c7cdf691d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883198349 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2883198349
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.2415647438
Short name T726
Test name
Test status
Simulation time 642304000 ps
CPU time 55.26 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:32:22 PM PDT 24
Peak memory 263024 kb
Host smart-53330d02-55d8-47a4-88f7-48a0b739c8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415647438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2415647438
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.802205684
Short name T829
Test name
Test status
Simulation time 696243100 ps
CPU time 231.34 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:35:16 PM PDT 24
Peak memory 281276 kb
Host smart-3f41ea5a-cb5c-4704-baa2-b167f3059116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802205684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.802205684
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.601047683
Short name T483
Test name
Test status
Simulation time 73900400 ps
CPU time 13.55 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:40 PM PDT 24
Peak memory 265136 kb
Host smart-c32921a1-fcf9-4221-a65e-95023eabb08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601047683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.601047683
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.906450142
Short name T371
Test name
Test status
Simulation time 15681600 ps
CPU time 16.2 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 275612 kb
Host smart-78be0fbe-a5cd-46b8-9157-ec71240dae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906450142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.906450142
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.907607453
Short name T385
Test name
Test status
Simulation time 12359900 ps
CPU time 22.05 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:48 PM PDT 24
Peak memory 265340 kb
Host smart-036fa560-fb79-4b09-8e0b-0e4067bc66dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907607453 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.907607453
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1294444683
Short name T1000
Test name
Test status
Simulation time 1289315700 ps
CPU time 105.91 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:33:13 PM PDT 24
Peak memory 262624 kb
Host smart-cec0e228-0b1f-4699-9230-603e323845f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294444683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1294444683
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1061746478
Short name T473
Test name
Test status
Simulation time 7056884600 ps
CPU time 141.54 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:33:46 PM PDT 24
Peak memory 292340 kb
Host smart-f820ab72-8836-4ee3-b75c-21ffbdfba016
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061746478 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1061746478
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.1357870813
Short name T428
Test name
Test status
Simulation time 62319500 ps
CPU time 131.78 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:33:38 PM PDT 24
Peak memory 259920 kb
Host smart-2f9d6339-c074-49f4-9d73-a15c0ed05940
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357870813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.1357870813
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.681893120
Short name T608
Test name
Test status
Simulation time 9064190100 ps
CPU time 204.97 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:34:51 PM PDT 24
Peak memory 265120 kb
Host smart-c6e77f9d-deb3-4a01-96aa-541c0f02a080
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681893120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_res
et.681893120
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.3757314058
Short name T877
Test name
Test status
Simulation time 76183000 ps
CPU time 28.58 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:31:53 PM PDT 24
Peak memory 273480 kb
Host smart-5bb4f5f7-debb-4689-a3d3-ce0a28334a9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757314058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.3757314058
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.278901292
Short name T596
Test name
Test status
Simulation time 46068700 ps
CPU time 29.21 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:31:53 PM PDT 24
Peak memory 274656 kb
Host smart-f145e9e8-32c4-4a62-be60-dbfa6115c974
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278901292 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.278901292
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.1278146973
Short name T1030
Test name
Test status
Simulation time 2515374900 ps
CPU time 81.3 seconds
Started May 23 01:31:27 PM PDT 24
Finished May 23 01:32:49 PM PDT 24
Peak memory 262864 kb
Host smart-1b5a8f8e-5a29-4783-9a4b-94ab2d8693a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278146973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1278146973
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.3814258701
Short name T376
Test name
Test status
Simulation time 19942300 ps
CPU time 51.45 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:32:17 PM PDT 24
Peak memory 270680 kb
Host smart-2e2a00a8-1f07-4a29-9704-33b36e043b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814258701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3814258701
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3964995880
Short name T103
Test name
Test status
Simulation time 64046600 ps
CPU time 13.84 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:31:39 PM PDT 24
Peak memory 265084 kb
Host smart-29c5110c-49af-4ea6-99b7-73d29e33f423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964995880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3964995880
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1782298718
Short name T437
Test name
Test status
Simulation time 20106800 ps
CPU time 15.51 seconds
Started May 23 01:31:22 PM PDT 24
Finished May 23 01:31:39 PM PDT 24
Peak memory 276028 kb
Host smart-18cabd09-b937-4b19-8ae6-7816671b26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782298718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1782298718
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2661394830
Short name T1036
Test name
Test status
Simulation time 39157600 ps
CPU time 22.25 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 265352 kb
Host smart-6e394949-504a-4ffd-a11d-fad8bf149892
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661394830 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2661394830
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2657204012
Short name T19
Test name
Test status
Simulation time 5345254900 ps
CPU time 85.28 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:32:52 PM PDT 24
Peak memory 262612 kb
Host smart-481bd306-d7e7-46ad-ae86-ab7434604f17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657204012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.2657204012
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1428068189
Short name T33
Test name
Test status
Simulation time 748327000 ps
CPU time 144.16 seconds
Started May 23 01:31:23 PM PDT 24
Finished May 23 01:33:48 PM PDT 24
Peak memory 298000 kb
Host smart-975834e3-ede7-4ce1-be1e-4fbcf271439b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428068189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1428068189
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4009670878
Short name T776
Test name
Test status
Simulation time 40133923900 ps
CPU time 152.08 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:33:58 PM PDT 24
Peak memory 291964 kb
Host smart-4647eb4a-ca5c-40ef-b512-666bb793bc56
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009670878 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.4009670878
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.3320021400
Short name T934
Test name
Test status
Simulation time 42922500 ps
CPU time 132.23 seconds
Started May 23 01:31:22 PM PDT 24
Finished May 23 01:33:36 PM PDT 24
Peak memory 260868 kb
Host smart-e3e08f0c-f322-49e2-8295-b4146a290fab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320021400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.3320021400
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2055193403
Short name T1082
Test name
Test status
Simulation time 84200900 ps
CPU time 13.6 seconds
Started May 23 01:31:26 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 258768 kb
Host smart-c3251664-2e71-430d-b2d6-f500ac6084f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055193403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2055193403
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.823457656
Short name T208
Test name
Test status
Simulation time 29677000 ps
CPU time 29.3 seconds
Started May 23 01:31:25 PM PDT 24
Finished May 23 01:31:56 PM PDT 24
Peak memory 274888 kb
Host smart-1aa8203d-2562-46da-abd6-0b3e764db60f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823457656 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.823457656
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3272554675
Short name T440
Test name
Test status
Simulation time 7970991700 ps
CPU time 70.34 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:32:36 PM PDT 24
Peak memory 262524 kb
Host smart-254143a9-07fe-46b9-bc9e-76a0c3df187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272554675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3272554675
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3615474932
Short name T232
Test name
Test status
Simulation time 63579600 ps
CPU time 74.71 seconds
Started May 23 01:31:24 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 275364 kb
Host smart-4c433d7a-986b-4e1e-850e-8f62e67b6fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615474932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3615474932
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.1090417021
Short name T404
Test name
Test status
Simulation time 249264300 ps
CPU time 13.98 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 265196 kb
Host smart-a48f6d3f-6661-4c0e-b727-87742f8a3f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090417021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1
090417021
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3903852769
Short name T980
Test name
Test status
Simulation time 28090200 ps
CPU time 13.65 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:28:15 PM PDT 24
Peak memory 274884 kb
Host smart-f28826a4-3d8b-4f6e-a0a7-c76efa61a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903852769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3903852769
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.2098195240
Short name T762
Test name
Test status
Simulation time 196828600 ps
CPU time 105.46 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:29:49 PM PDT 24
Peak memory 280748 kb
Host smart-cf568d1d-1e23-4020-8832-e9c9110d1ee6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098195240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.2098195240
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.3396357487
Short name T1056
Test name
Test status
Simulation time 37802500 ps
CPU time 21.85 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:28:25 PM PDT 24
Peak memory 273572 kb
Host smart-73cb90c8-fe33-4bdb-ac6a-c530e4bdbefc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396357487 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.3396357487
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.870861448
Short name T1077
Test name
Test status
Simulation time 2855437900 ps
CPU time 338.2 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:33:42 PM PDT 24
Peak memory 261340 kb
Host smart-e6c974d0-2fbf-4f9a-af68-60c9035607f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870861448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.870861448
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2312187606
Short name T777
Test name
Test status
Simulation time 8736951200 ps
CPU time 2449.09 seconds
Started May 23 01:28:18 PM PDT 24
Finished May 23 02:09:09 PM PDT 24
Peak memory 265068 kb
Host smart-57103261-5fb7-4c70-9b37-2a0982d73ce3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312187606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2312187606
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2039077
Short name T702
Test name
Test status
Simulation time 2603780200 ps
CPU time 862.5 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 273360 kb
Host smart-10d44615-9136-4291-af25-0fb1cb5f4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2039077
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2264228770
Short name T178
Test name
Test status
Simulation time 6084390600 ps
CPU time 40.89 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:28:43 PM PDT 24
Peak memory 265244 kb
Host smart-bba063cb-41b2-4a71-ba15-ee230b0f322b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264228770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2264228770
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2753485800
Short name T1067
Test name
Test status
Simulation time 48916342800 ps
CPU time 3702.22 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 02:29:45 PM PDT 24
Peak memory 265108 kb
Host smart-34cb93a6-41b2-4074-a43f-5ae7476787d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753485800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2753485800
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3761929148
Short name T229
Test name
Test status
Simulation time 578400005500 ps
CPU time 2139.88 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 02:03:45 PM PDT 24
Peak memory 265208 kb
Host smart-222b7448-e52a-46f2-b11c-6ca1d03e2057
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761929148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3761929148
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2229639918
Short name T612
Test name
Test status
Simulation time 60773000 ps
CPU time 48.29 seconds
Started May 23 01:27:55 PM PDT 24
Finished May 23 01:28:45 PM PDT 24
Peak memory 262472 kb
Host smart-5f75fbad-bd38-487d-ba20-e0be49184198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229639918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2229639918
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2309474140
Short name T135
Test name
Test status
Simulation time 10011932000 ps
CPU time 312.08 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:33:19 PM PDT 24
Peak memory 309532 kb
Host smart-7143b180-a925-45d3-b32a-07ac787b2e7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309474140 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2309474140
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1497083922
Short name T192
Test name
Test status
Simulation time 48593800 ps
CPU time 13.45 seconds
Started May 23 01:27:58 PM PDT 24
Finished May 23 01:28:13 PM PDT 24
Peak memory 265148 kb
Host smart-434a31d9-9a27-46c6-ae26-78f1c60d3425
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497083922 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1497083922
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.932105560
Short name T90
Test name
Test status
Simulation time 40122434900 ps
CPU time 812.2 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:41:31 PM PDT 24
Peak memory 264544 kb
Host smart-1431f3e7-e2fc-4d26-9f8e-c8f9b5c8de3f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932105560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.932105560
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1867605831
Short name T710
Test name
Test status
Simulation time 33133820400 ps
CPU time 169.87 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:30:48 PM PDT 24
Peak memory 262664 kb
Host smart-9a88701b-c54d-44e7-abd5-5c2128044a8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867605831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1867605831
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.1850343528
Short name T689
Test name
Test status
Simulation time 1279302900 ps
CPU time 140.61 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:30:24 PM PDT 24
Peak memory 289872 kb
Host smart-43ee55e7-3946-4e4b-91db-d17a9b6d2685
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850343528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.1850343528
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1258270981
Short name T7
Test name
Test status
Simulation time 5636879600 ps
CPU time 125.48 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:30:07 PM PDT 24
Peak memory 292160 kb
Host smart-e67693a2-eae6-40d1-a075-bec0f58c98f0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258270981 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1258270981
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3608369547
Short name T772
Test name
Test status
Simulation time 5390074200 ps
CPU time 74.76 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:29:18 PM PDT 24
Peak memory 260176 kb
Host smart-40585ddc-4ff6-4bf7-b670-4467cc84ccda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608369547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3608369547
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.496639326
Short name T27
Test name
Test status
Simulation time 290739245600 ps
CPU time 475.86 seconds
Started May 23 01:27:58 PM PDT 24
Finished May 23 01:35:55 PM PDT 24
Peak memory 260376 kb
Host smart-5b750aca-b32f-4603-b3c6-d9b3087ba792
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496
639326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.496639326
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.1745439244
Short name T104
Test name
Test status
Simulation time 996307400 ps
CPU time 75.85 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:29:21 PM PDT 24
Peak memory 259728 kb
Host smart-1b261a63-0f89-4328-9128-1ac56decfb8a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745439244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1745439244
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4245839424
Short name T637
Test name
Test status
Simulation time 15722300 ps
CPU time 13.37 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 265076 kb
Host smart-9954468f-429a-4193-99b7-f9339909550a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245839424 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4245839424
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.2455254322
Short name T108
Test name
Test status
Simulation time 36918130400 ps
CPU time 593.36 seconds
Started May 23 01:28:08 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 274088 kb
Host smart-fe2f3504-487c-45c9-85c7-15e418703ba4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455254322 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.2455254322
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.3089035940
Short name T409
Test name
Test status
Simulation time 2863835600 ps
CPU time 134.14 seconds
Started May 23 01:27:57 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 281652 kb
Host smart-57c1fcbc-b6c6-40f7-ac87-4ce9e41cae5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089035940 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.3089035940
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.2556022080
Short name T701
Test name
Test status
Simulation time 145905600 ps
CPU time 152.95 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:30:33 PM PDT 24
Peak memory 261800 kb
Host smart-aaaf6692-4d6f-497a-8d90-4f0b21ab826b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556022080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2556022080
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3981126893
Short name T261
Test name
Test status
Simulation time 44894700 ps
CPU time 13.76 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:28:24 PM PDT 24
Peak memory 265328 kb
Host smart-c68b1ab8-3950-41a3-bb20-0441c3ceda29
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981126893 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3981126893
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3130625683
Short name T925
Test name
Test status
Simulation time 22028800 ps
CPU time 14 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:28:16 PM PDT 24
Peak memory 258548 kb
Host smart-880a8e32-4f89-4bae-a3f1-20a9e1fa2a44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130625683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.3130625683
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.813152434
Short name T724
Test name
Test status
Simulation time 649314600 ps
CPU time 914.07 seconds
Started May 23 01:27:49 PM PDT 24
Finished May 23 01:43:05 PM PDT 24
Peak memory 282560 kb
Host smart-cc536bad-c3c3-41e9-8da5-0779994e9488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813152434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.813152434
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.5452167
Short name T910
Test name
Test status
Simulation time 759947100 ps
CPU time 116.08 seconds
Started May 23 01:27:48 PM PDT 24
Finished May 23 01:29:46 PM PDT 24
Peak memory 265200 kb
Host smart-cc8161e3-4226-4308-9d87-23d1f0a2023c
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=5452167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.5452167
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.56511828
Short name T455
Test name
Test status
Simulation time 213865400 ps
CPU time 37.01 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:28:41 PM PDT 24
Peak memory 273364 kb
Host smart-1a96ccc5-24d7-42aa-8d21-05603d70b239
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56511828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_re_evict.56511828
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2587214511
Short name T1068
Test name
Test status
Simulation time 113425900 ps
CPU time 22.87 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:28:27 PM PDT 24
Peak memory 265108 kb
Host smart-fa87e6f8-76bc-4a57-8561-ff68f6d8c642
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587214511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2587214511
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.4288189839
Short name T408
Test name
Test status
Simulation time 554294100 ps
CPU time 120.45 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:30:04 PM PDT 24
Peak memory 281524 kb
Host smart-3898c289-39e4-4d3b-87e3-68d37149e0e2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288189839 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.4288189839
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.1465699010
Short name T1072
Test name
Test status
Simulation time 2144356900 ps
CPU time 136.88 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:30:23 PM PDT 24
Peak memory 281780 kb
Host smart-1bd50352-0c75-4873-b1cf-a3834bf437db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1465699010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1465699010
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.3916688011
Short name T183
Test name
Test status
Simulation time 1094128200 ps
CPU time 115.48 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:29:58 PM PDT 24
Peak memory 281708 kb
Host smart-68f2afab-2d98-4e81-978e-c3ca514740ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916688011 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3916688011
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.3003648620
Short name T1017
Test name
Test status
Simulation time 3256273900 ps
CPU time 500.55 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:36:24 PM PDT 24
Peak memory 314536 kb
Host smart-d793eccc-2a8a-4000-bf4a-297b25aef5b5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003648620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.3003648620
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1256057001
Short name T40
Test name
Test status
Simulation time 95914100 ps
CPU time 32.35 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:28:35 PM PDT 24
Peak memory 275592 kb
Host smart-ffeb6a66-6a9b-4df9-bae5-dd5e2c75c559
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256057001 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1256057001
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.1279532687
Short name T199
Test name
Test status
Simulation time 49686302900 ps
CPU time 634.42 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 312124 kb
Host smart-534234b6-50ee-47da-bc96-c727a008d0ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279532687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.1279532687
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.3823842792
Short name T190
Test name
Test status
Simulation time 1147217000 ps
CPU time 4785.09 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 02:47:49 PM PDT 24
Peak memory 282804 kb
Host smart-53c24bde-792b-4ddf-9124-465e58038643
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823842792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3823842792
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2857781239
Short name T470
Test name
Test status
Simulation time 3649007700 ps
CPU time 67.89 seconds
Started May 23 01:27:58 PM PDT 24
Finished May 23 01:29:07 PM PDT 24
Peak memory 263296 kb
Host smart-8639a59e-ff5f-478f-8eb8-99c263cef584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857781239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2857781239
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.762805427
Short name T847
Test name
Test status
Simulation time 2146422700 ps
CPU time 61.59 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:29:22 PM PDT 24
Peak memory 265184 kb
Host smart-18520279-ff99-48c4-a2d8-7b1d8ece0788
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762805427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.762805427
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.3712052656
Short name T457
Test name
Test status
Simulation time 3213141800 ps
CPU time 76.03 seconds
Started May 23 01:28:16 PM PDT 24
Finished May 23 01:29:33 PM PDT 24
Peak memory 273500 kb
Host smart-80d661b0-1be7-4b25-b577-1bbe10c769fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712052656 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.3712052656
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.1268386768
Short name T474
Test name
Test status
Simulation time 24728600 ps
CPU time 98.28 seconds
Started May 23 01:27:47 PM PDT 24
Finished May 23 01:29:27 PM PDT 24
Peak memory 275520 kb
Host smart-4671e714-89be-45a1-a4cd-53fb05a1c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268386768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1268386768
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3799286199
Short name T717
Test name
Test status
Simulation time 79628500 ps
CPU time 26.08 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:28:18 PM PDT 24
Peak memory 259052 kb
Host smart-210581d1-2f73-46e2-80f6-32a870e33a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799286199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3799286199
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2787725293
Short name T647
Test name
Test status
Simulation time 20097200 ps
CPU time 26.95 seconds
Started May 23 01:27:51 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 261852 kb
Host smart-8ea449f9-aa07-4025-9e88-5bbf6c2b8ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787725293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2787725293
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.644250557
Short name T533
Test name
Test status
Simulation time 1839350200 ps
CPU time 132.65 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:30:16 PM PDT 24
Peak memory 259096 kb
Host smart-66a8dd60-dab7-40f1-afd4-c05a8bd95e50
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644250557 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_wo.644250557
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.704385983
Short name T502
Test name
Test status
Simulation time 184069000 ps
CPU time 14.22 seconds
Started May 23 01:31:36 PM PDT 24
Finished May 23 01:31:51 PM PDT 24
Peak memory 265200 kb
Host smart-405ff648-fa79-40f9-b645-da0874106b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704385983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.704385983
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2614084472
Short name T952
Test name
Test status
Simulation time 41654100 ps
CPU time 16.02 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:31:56 PM PDT 24
Peak memory 275232 kb
Host smart-336a0b62-328b-4068-b4d3-1a0bfa694758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614084472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2614084472
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1617638231
Short name T1059
Test name
Test status
Simulation time 7561588900 ps
CPU time 141.05 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:34:00 PM PDT 24
Peak memory 262612 kb
Host smart-d98dbb94-9e5f-4e9e-88ed-f490b6d0c559
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617638231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1617638231
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2737295680
Short name T24
Test name
Test status
Simulation time 2676719100 ps
CPU time 134.26 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:33:54 PM PDT 24
Peak memory 290944 kb
Host smart-83504b49-2a79-4131-a23f-1fc61fe4ca78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737295680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2737295680
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2633675902
Short name T445
Test name
Test status
Simulation time 10033047900 ps
CPU time 120.37 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:33:39 PM PDT 24
Peak memory 292080 kb
Host smart-9a07f4f4-834a-4d1c-9bc6-0376e752dec1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633675902 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2633675902
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1398590881
Short name T626
Test name
Test status
Simulation time 38604300 ps
CPU time 130.2 seconds
Started May 23 01:31:39 PM PDT 24
Finished May 23 01:33:51 PM PDT 24
Peak memory 260012 kb
Host smart-cec630d3-3e10-4057-92b5-21785feabeff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398590881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1398590881
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1343001587
Short name T332
Test name
Test status
Simulation time 56110000 ps
CPU time 31.91 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:32:11 PM PDT 24
Peak memory 274872 kb
Host smart-f05dec62-6a85-440a-92cf-9d4b39a62fc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343001587 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1343001587
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2708182016
Short name T1039
Test name
Test status
Simulation time 2537885300 ps
CPU time 66.74 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:32:45 PM PDT 24
Peak memory 263352 kb
Host smart-c23c1238-ceeb-4d7f-b709-d6ed76e7bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708182016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2708182016
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3637949618
Short name T650
Test name
Test status
Simulation time 195219000 ps
CPU time 72.54 seconds
Started May 23 01:31:43 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 275328 kb
Host smart-5cde38e9-7ea1-482c-9ea3-4bd0ad0f624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637949618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3637949618
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.383866877
Short name T403
Test name
Test status
Simulation time 21035700 ps
CPU time 13.77 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:31:52 PM PDT 24
Peak memory 264468 kb
Host smart-a0e9142c-aeae-4326-93fe-5a185fc8023e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383866877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.383866877
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.2017265250
Short name T763
Test name
Test status
Simulation time 14783100 ps
CPU time 15.84 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:31:56 PM PDT 24
Peak memory 275716 kb
Host smart-d76c1f46-b2be-4b54-b6db-53e950359d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017265250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2017265250
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.2300379427
Short name T386
Test name
Test status
Simulation time 39531500 ps
CPU time 22.21 seconds
Started May 23 01:31:41 PM PDT 24
Finished May 23 01:32:04 PM PDT 24
Peak memory 280368 kb
Host smart-977ff407-f50c-4ebd-8e09-deaf17d9ab7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300379427 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.2300379427
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.4044798633
Short name T317
Test name
Test status
Simulation time 2756704300 ps
CPU time 227.19 seconds
Started May 23 01:31:36 PM PDT 24
Finished May 23 01:35:24 PM PDT 24
Peak memory 259476 kb
Host smart-97e3049a-c7a6-4fc2-8adb-cdbd6f3a1afa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044798633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.4044798633
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1659265287
Short name T640
Test name
Test status
Simulation time 1897716600 ps
CPU time 284.16 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:36:24 PM PDT 24
Peak memory 284196 kb
Host smart-1f60b050-446a-4ac6-b974-d36259f18138
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659265287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1659265287
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2054811778
Short name T496
Test name
Test status
Simulation time 13158837800 ps
CPU time 274.1 seconds
Started May 23 01:31:39 PM PDT 24
Finished May 23 01:36:15 PM PDT 24
Peak memory 284396 kb
Host smart-13fd3e44-c46d-42f3-85bf-6492dbc0c13c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054811778 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2054811778
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2811482369
Short name T12
Test name
Test status
Simulation time 39977200 ps
CPU time 130.67 seconds
Started May 23 01:31:41 PM PDT 24
Finished May 23 01:33:53 PM PDT 24
Peak memory 260136 kb
Host smart-99b7df23-27cb-4b1f-b01b-031698db9c5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811482369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2811482369
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3975160403
Short name T263
Test name
Test status
Simulation time 37401600 ps
CPU time 31.51 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:32:12 PM PDT 24
Peak memory 274592 kb
Host smart-e3345de9-4bf0-4109-9ce8-d96929b0d994
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975160403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3975160403
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3117932590
Short name T37
Test name
Test status
Simulation time 114302700 ps
CPU time 31.74 seconds
Started May 23 01:31:39 PM PDT 24
Finished May 23 01:32:12 PM PDT 24
Peak memory 274768 kb
Host smart-be1e7d95-02b4-4682-81bf-e9714255bf5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117932590 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3117932590
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.754563554
Short name T396
Test name
Test status
Simulation time 14503039200 ps
CPU time 83.82 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:33:02 PM PDT 24
Peak memory 262252 kb
Host smart-ce97f0a6-5310-4451-aece-aa0d718bd868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754563554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.754563554
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.2511374199
Short name T503
Test name
Test status
Simulation time 275794200 ps
CPU time 170.1 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:34:29 PM PDT 24
Peak memory 279572 kb
Host smart-f4c02042-abd0-4789-8946-8af7fcb1dc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511374199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2511374199
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2146176206
Short name T521
Test name
Test status
Simulation time 61056700 ps
CPU time 15.56 seconds
Started May 23 01:31:54 PM PDT 24
Finished May 23 01:32:12 PM PDT 24
Peak memory 275616 kb
Host smart-e5a8851b-9dc7-43c4-ae56-d0f9199ca825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146176206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2146176206
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.646375851
Short name T782
Test name
Test status
Simulation time 28369700 ps
CPU time 21.95 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:32:00 PM PDT 24
Peak memory 265236 kb
Host smart-b98b2a0b-0dc4-4fa5-a06b-3e71e4fe718b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646375851 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.646375851
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3568998496
Short name T453
Test name
Test status
Simulation time 10104235900 ps
CPU time 146.81 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:34:06 PM PDT 24
Peak memory 261948 kb
Host smart-025bce8c-4b41-4410-a348-6ca5ab0a0228
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568998496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3568998496
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.4093972689
Short name T909
Test name
Test status
Simulation time 1909684100 ps
CPU time 118.01 seconds
Started May 23 01:31:39 PM PDT 24
Finished May 23 01:33:39 PM PDT 24
Peak memory 284528 kb
Host smart-2b08aa42-a99a-400d-bb2c-c78ce365cfdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093972689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.4093972689
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2993597433
Short name T766
Test name
Test status
Simulation time 195669841100 ps
CPU time 441.61 seconds
Started May 23 01:31:40 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 284496 kb
Host smart-1c6d52e7-2052-4120-8ada-cfa745fedb50
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993597433 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2993597433
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.1583072752
Short name T680
Test name
Test status
Simulation time 184124400 ps
CPU time 32.66 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:32:12 PM PDT 24
Peak memory 273524 kb
Host smart-cacc64bc-48f5-4092-8aed-2b22b3337dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583072752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.1583072752
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3815108992
Short name T39
Test name
Test status
Simulation time 47090300 ps
CPU time 30.93 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:32:10 PM PDT 24
Peak memory 269116 kb
Host smart-9549a22a-3242-44a7-9297-fdf34411210b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815108992 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3815108992
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.312994601
Short name T399
Test name
Test status
Simulation time 2331083500 ps
CPU time 64.06 seconds
Started May 23 01:31:38 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 262512 kb
Host smart-4e63e980-8cb3-4e3c-8a9f-cabe03a9c989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312994601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.312994601
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.471564108
Short name T435
Test name
Test status
Simulation time 69856800 ps
CPU time 170.23 seconds
Started May 23 01:31:37 PM PDT 24
Finished May 23 01:34:29 PM PDT 24
Peak memory 276744 kb
Host smart-02aaaecb-c036-407e-adfa-a264405def02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471564108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.471564108
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.3259002014
Short name T450
Test name
Test status
Simulation time 186857700 ps
CPU time 13.92 seconds
Started May 23 01:31:50 PM PDT 24
Finished May 23 01:32:06 PM PDT 24
Peak memory 265040 kb
Host smart-953c1032-986d-42d3-a5b7-18ebbb1b1618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259002014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
3259002014
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1059088608
Short name T419
Test name
Test status
Simulation time 28611000 ps
CPU time 15.91 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:32:10 PM PDT 24
Peak memory 276032 kb
Host smart-60afa5fe-adc6-425a-a07d-7f684850555d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059088608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1059088608
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3938880332
Short name T156
Test name
Test status
Simulation time 19650500 ps
CPU time 22.19 seconds
Started May 23 01:31:54 PM PDT 24
Finished May 23 01:32:18 PM PDT 24
Peak memory 265232 kb
Host smart-3f622096-12d7-4204-b758-2260196dcb4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938880332 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3938880332
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1616418369
Short name T993
Test name
Test status
Simulation time 3668072800 ps
CPU time 138.19 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:34:12 PM PDT 24
Peak memory 262640 kb
Host smart-0d3624cf-c2e9-40a6-a87e-354adf2080a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616418369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1616418369
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.1808967747
Short name T225
Test name
Test status
Simulation time 1697070500 ps
CPU time 217.71 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:35:31 PM PDT 24
Peak memory 284080 kb
Host smart-8a353530-fa55-46dd-aa29-27e4ac4fa438
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808967747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.1808967747
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3491746263
Short name T490
Test name
Test status
Simulation time 11843924300 ps
CPU time 145.14 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:34:20 PM PDT 24
Peak memory 293072 kb
Host smart-3019e2e3-7fea-47ca-a8aa-092dbc4ce0da
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491746263 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3491746263
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.3891250275
Short name T649
Test name
Test status
Simulation time 157476400 ps
CPU time 131.24 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:34:05 PM PDT 24
Peak memory 260164 kb
Host smart-9707c608-6edb-4b38-97eb-06542abbe7a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891250275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.3891250275
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3316556721
Short name T1090
Test name
Test status
Simulation time 39228100 ps
CPU time 29.34 seconds
Started May 23 01:31:50 PM PDT 24
Finished May 23 01:32:21 PM PDT 24
Peak memory 273536 kb
Host smart-b43b5ad5-e2da-4e09-b811-289b65b2c497
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316556721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3316556721
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.779949535
Short name T817
Test name
Test status
Simulation time 82956800 ps
CPU time 29.37 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:32:23 PM PDT 24
Peak memory 274856 kb
Host smart-9ff5958a-2729-4913-8c63-f2cfef5f4625
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779949535 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.779949535
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1536740016
Short name T595
Test name
Test status
Simulation time 2872851600 ps
CPU time 72.95 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:33:08 PM PDT 24
Peak memory 263192 kb
Host smart-4c1009a6-bc43-4107-8d94-4106e0ef5f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536740016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1536740016
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.3648158614
Short name T589
Test name
Test status
Simulation time 101889200 ps
CPU time 96.06 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:33:30 PM PDT 24
Peak memory 276508 kb
Host smart-d7efbaad-e6d6-4363-a7de-9fbebdf2e100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648158614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3648158614
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.1657827765
Short name T576
Test name
Test status
Simulation time 26591400 ps
CPU time 13.83 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:32:09 PM PDT 24
Peak memory 265112 kb
Host smart-308c15ed-7a1c-47f5-a765-b72b980eb0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657827765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
1657827765
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.4154362424
Short name T669
Test name
Test status
Simulation time 110816700 ps
CPU time 15.65 seconds
Started May 23 01:31:50 PM PDT 24
Finished May 23 01:32:07 PM PDT 24
Peak memory 274972 kb
Host smart-e636a118-7f58-4ca4-9f6d-ef6f2e46ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154362424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.4154362424
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.3944427224
Short name T807
Test name
Test status
Simulation time 11898400 ps
CPU time 22.48 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:32:18 PM PDT 24
Peak memory 265228 kb
Host smart-ce9085ed-1f94-42ae-ac66-521c439c578f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944427224 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.3944427224
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2841932794
Short name T785
Test name
Test status
Simulation time 8099243700 ps
CPU time 142.61 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:34:16 PM PDT 24
Peak memory 262704 kb
Host smart-c7c6a8fa-bde7-4040-861b-419a4f232da1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841932794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2841932794
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.4093959710
Short name T270
Test name
Test status
Simulation time 1748492700 ps
CPU time 230.91 seconds
Started May 23 01:31:50 PM PDT 24
Finished May 23 01:35:42 PM PDT 24
Peak memory 284196 kb
Host smart-2bf888d6-982d-4f9c-832d-76b268173710
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093959710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.4093959710
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.935413147
Short name T873
Test name
Test status
Simulation time 31561662600 ps
CPU time 296.53 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:36:51 PM PDT 24
Peak memory 284236 kb
Host smart-d18a77bc-e199-4413-bcd1-933dd35f32b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935413147 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.935413147
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.939088769
Short name T911
Test name
Test status
Simulation time 75280000 ps
CPU time 31.5 seconds
Started May 23 01:31:54 PM PDT 24
Finished May 23 01:32:27 PM PDT 24
Peak memory 273552 kb
Host smart-43c8f436-704f-4a5d-9068-e1b96f964034
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939088769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_rw_evict.939088769
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3540568378
Short name T635
Test name
Test status
Simulation time 48941900 ps
CPU time 31.25 seconds
Started May 23 01:31:53 PM PDT 24
Finished May 23 01:32:26 PM PDT 24
Peak memory 275584 kb
Host smart-9f2d05c3-91eb-4800-9368-0882cf167c89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540568378 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.3540568378
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1736156892
Short name T561
Test name
Test status
Simulation time 1879277400 ps
CPU time 76.29 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:33:10 PM PDT 24
Peak memory 262336 kb
Host smart-e9c62475-8c5b-4189-8d1e-0082bbe7c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736156892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1736156892
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3161307941
Short name T927
Test name
Test status
Simulation time 37483600 ps
CPU time 51.99 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 270652 kb
Host smart-b2738c32-1efe-4c69-8051-d95ce43c7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161307941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3161307941
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.614960777
Short name T122
Test name
Test status
Simulation time 40896100 ps
CPU time 13.91 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:26 PM PDT 24
Peak memory 265076 kb
Host smart-30abfa15-a525-4d96-a5bc-b55d5c1ab45c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614960777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.614960777
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.3337000684
Short name T770
Test name
Test status
Simulation time 27771500 ps
CPU time 13.23 seconds
Started May 23 01:32:08 PM PDT 24
Finished May 23 01:32:22 PM PDT 24
Peak memory 275984 kb
Host smart-e8bf72b9-1296-4f23-821c-3677aadd7274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337000684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3337000684
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.1561381295
Short name T369
Test name
Test status
Simulation time 45261800 ps
CPU time 22.12 seconds
Started May 23 01:31:54 PM PDT 24
Finished May 23 01:32:18 PM PDT 24
Peak memory 265164 kb
Host smart-1f8c05f5-8f9e-4d75-b809-a8882a871155
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561381295 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.1561381295
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2943487639
Short name T591
Test name
Test status
Simulation time 3536941600 ps
CPU time 136.07 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:34:10 PM PDT 24
Peak memory 262632 kb
Host smart-b68946c2-e928-4aca-ab55-774287c2db7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943487639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2943487639
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.605122211
Short name T1091
Test name
Test status
Simulation time 1594295200 ps
CPU time 174.85 seconds
Started May 23 01:31:50 PM PDT 24
Finished May 23 01:34:47 PM PDT 24
Peak memory 284068 kb
Host smart-17112208-57d6-49f7-9db4-d9fb651de494
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605122211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.605122211
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.177246059
Short name T882
Test name
Test status
Simulation time 69564142700 ps
CPU time 151.04 seconds
Started May 23 01:31:54 PM PDT 24
Finished May 23 01:34:27 PM PDT 24
Peak memory 292348 kb
Host smart-b32a5b21-d72f-4a69-b8db-c4ed7dd5b0ed
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177246059 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.177246059
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.1679271516
Short name T150
Test name
Test status
Simulation time 77760300 ps
CPU time 132.71 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:34:06 PM PDT 24
Peak memory 264300 kb
Host smart-6acd0ceb-6647-4672-b331-76bd9dae161d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679271516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.1679271516
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2519448862
Short name T401
Test name
Test status
Simulation time 2242323600 ps
CPU time 70.7 seconds
Started May 23 01:31:52 PM PDT 24
Finished May 23 01:33:05 PM PDT 24
Peak memory 263212 kb
Host smart-cfbdac38-5938-470c-a9d8-0ce65f4758ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519448862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2519448862
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1795769444
Short name T1057
Test name
Test status
Simulation time 27395900 ps
CPU time 75.69 seconds
Started May 23 01:31:51 PM PDT 24
Finished May 23 01:33:08 PM PDT 24
Peak memory 275004 kb
Host smart-a12629c9-ce08-400e-ab26-39ca2cf70c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795769444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1795769444
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3866638453
Short name T448
Test name
Test status
Simulation time 305145600 ps
CPU time 14.42 seconds
Started May 23 01:32:07 PM PDT 24
Finished May 23 01:32:23 PM PDT 24
Peak memory 264224 kb
Host smart-0db7bb6d-52ea-443e-856e-40f7bdeebfae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866638453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3866638453
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.1542803473
Short name T469
Test name
Test status
Simulation time 15931900 ps
CPU time 13.39 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:25 PM PDT 24
Peak memory 274952 kb
Host smart-37224423-0491-410b-8af0-dd454fa5344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542803473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1542803473
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1825532113
Short name T937
Test name
Test status
Simulation time 106402200 ps
CPU time 22.15 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:34 PM PDT 24
Peak memory 265356 kb
Host smart-e834707b-cec7-43f5-9234-cb0ca4f8810c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825532113 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1825532113
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.375010464
Short name T422
Test name
Test status
Simulation time 20198975000 ps
CPU time 258.06 seconds
Started May 23 01:32:08 PM PDT 24
Finished May 23 01:36:26 PM PDT 24
Peak memory 262528 kb
Host smart-d4385e6b-2516-474e-8cae-1391484bbf07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375010464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h
w_sec_otp.375010464
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.777925584
Short name T1034
Test name
Test status
Simulation time 1744971900 ps
CPU time 234.93 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:36:06 PM PDT 24
Peak memory 284212 kb
Host smart-ea3228ec-9680-4979-8267-1cae308b570b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777925584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas
h_ctrl_intr_rd.777925584
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1751906836
Short name T310
Test name
Test status
Simulation time 24444732500 ps
CPU time 180.77 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:35:13 PM PDT 24
Peak memory 291848 kb
Host smart-268f7850-41dc-40e4-8446-7778df3eefbd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751906836 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1751906836
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.801001124
Short name T378
Test name
Test status
Simulation time 39119800 ps
CPU time 112 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:34:04 PM PDT 24
Peak memory 259680 kb
Host smart-d0fdf63d-0fff-4b31-a0c8-cd68acc9451b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801001124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ot
p_reset.801001124
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2699369632
Short name T761
Test name
Test status
Simulation time 47790300 ps
CPU time 31.35 seconds
Started May 23 01:32:08 PM PDT 24
Finished May 23 01:32:41 PM PDT 24
Peak memory 273460 kb
Host smart-33cb487b-a60e-40e1-b93c-c5277b8a1e11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699369632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2699369632
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2983766847
Short name T257
Test name
Test status
Simulation time 39565600 ps
CPU time 28.83 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 274764 kb
Host smart-d02cdbc0-7181-4b0a-9829-0bd980eefc3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983766847 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2983766847
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.317812033
Short name T397
Test name
Test status
Simulation time 2228023500 ps
CPU time 79.63 seconds
Started May 23 01:32:12 PM PDT 24
Finished May 23 01:33:33 PM PDT 24
Peak memory 263208 kb
Host smart-326945e7-0c42-4be2-92b0-3b8d60f766f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317812033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.317812033
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.439288250
Short name T670
Test name
Test status
Simulation time 81211800 ps
CPU time 53.15 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:33:05 PM PDT 24
Peak memory 270684 kb
Host smart-5f69dbae-0e28-4339-9170-cfa03d929f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439288250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.439288250
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1276206844
Short name T813
Test name
Test status
Simulation time 131752700 ps
CPU time 13.62 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:32:25 PM PDT 24
Peak memory 265184 kb
Host smart-2a0a7556-44ee-4cc2-a06a-eef0a3de307e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276206844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1276206844
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1404355826
Short name T969
Test name
Test status
Simulation time 29891100 ps
CPU time 15.7 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:32:29 PM PDT 24
Peak memory 275772 kb
Host smart-fa25c4ae-0584-475e-a063-e5818372609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404355826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1404355826
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.3995376456
Short name T781
Test name
Test status
Simulation time 16519400 ps
CPU time 22.17 seconds
Started May 23 01:32:08 PM PDT 24
Finished May 23 01:32:32 PM PDT 24
Peak memory 265136 kb
Host smart-6732e9ad-419c-4d6e-97b1-4705dd7c7095
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995376456 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.3995376456
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.692714615
Short name T1086
Test name
Test status
Simulation time 4227506900 ps
CPU time 150 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:34:43 PM PDT 24
Peak memory 259464 kb
Host smart-edfd74ad-845c-4de6-9ba3-b23bab506afb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692714615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h
w_sec_otp.692714615
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.3439652870
Short name T734
Test name
Test status
Simulation time 20534248600 ps
CPU time 214.82 seconds
Started May 23 01:32:12 PM PDT 24
Finished May 23 01:35:48 PM PDT 24
Peak memory 289808 kb
Host smart-57f082b5-a036-4d29-a201-757bee00100f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439652870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.3439652870
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2483592230
Short name T756
Test name
Test status
Simulation time 48991094100 ps
CPU time 269.78 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:36:40 PM PDT 24
Peak memory 291228 kb
Host smart-87af9f64-f3b3-498b-9fe2-4afaaa37e368
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483592230 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2483592230
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.4174711892
Short name T71
Test name
Test status
Simulation time 38727200 ps
CPU time 132.18 seconds
Started May 23 01:32:07 PM PDT 24
Finished May 23 01:34:20 PM PDT 24
Peak memory 264432 kb
Host smart-72f309ef-b330-44d8-b845-2e6b348cbc89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174711892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.4174711892
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.1269464461
Short name T215
Test name
Test status
Simulation time 27137600 ps
CPU time 30.94 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:32:42 PM PDT 24
Peak memory 274836 kb
Host smart-e40dd81b-a546-442f-bfcb-ccca59dc38c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269464461 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.1269464461
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3871828492
Short name T840
Test name
Test status
Simulation time 725170300 ps
CPU time 70.98 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:33:24 PM PDT 24
Peak memory 263216 kb
Host smart-967782b1-3068-42ed-a71b-94f1f097b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871828492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3871828492
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.2770223407
Short name T123
Test name
Test status
Simulation time 134678700 ps
CPU time 217.92 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:35:51 PM PDT 24
Peak memory 277360 kb
Host smart-b3ac8837-dfb8-410e-a909-259a7cea427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770223407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2770223407
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.1373346449
Short name T936
Test name
Test status
Simulation time 53142000 ps
CPU time 13.64 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:26 PM PDT 24
Peak memory 264596 kb
Host smart-e11de012-1307-4f66-9a8f-f766f590204a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373346449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
1373346449
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.1135716612
Short name T864
Test name
Test status
Simulation time 26855700 ps
CPU time 15.56 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:28 PM PDT 24
Peak memory 275556 kb
Host smart-d03474f0-078e-4731-9b60-c37a77532c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135716612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1135716612
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1415569068
Short name T154
Test name
Test status
Simulation time 10273900 ps
CPU time 20.36 seconds
Started May 23 01:32:11 PM PDT 24
Finished May 23 01:32:33 PM PDT 24
Peak memory 265304 kb
Host smart-de1f8616-f9f4-40f5-99f6-7d1324b3d29f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415569068 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1415569068
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2403011161
Short name T764
Test name
Test status
Simulation time 2984256200 ps
CPU time 198.77 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:35:31 PM PDT 24
Peak memory 262640 kb
Host smart-730a7997-d1c0-49a4-960f-8f2dfbec2aae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403011161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2403011161
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.3429069499
Short name T198
Test name
Test status
Simulation time 718837800 ps
CPU time 160.59 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:34:53 PM PDT 24
Peak memory 294472 kb
Host smart-c1f26916-6a18-4496-acd0-3acb54dd6e2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429069499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.3429069499
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.353078796
Short name T643
Test name
Test status
Simulation time 8968539400 ps
CPU time 209.26 seconds
Started May 23 01:32:12 PM PDT 24
Finished May 23 01:35:43 PM PDT 24
Peak memory 293176 kb
Host smart-8ec57f9b-75e9-402f-8e30-8a9a86529b58
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353078796 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.353078796
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.2205730236
Short name T585
Test name
Test status
Simulation time 260278600 ps
CPU time 131.38 seconds
Started May 23 01:32:12 PM PDT 24
Finished May 23 01:34:25 PM PDT 24
Peak memory 259768 kb
Host smart-5053e7c3-cf9a-4bfc-a902-c235ab81df25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205730236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.2205730236
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1886292361
Short name T557
Test name
Test status
Simulation time 29117700 ps
CPU time 31.7 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 273488 kb
Host smart-ec1f102d-2ab5-46f1-b44e-8ee43a940359
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886292361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1886292361
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3101041333
Short name T91
Test name
Test status
Simulation time 31109600 ps
CPU time 31.78 seconds
Started May 23 01:32:07 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 274876 kb
Host smart-55da1e2e-7905-49b6-a7f5-ee1ff7986b34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101041333 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3101041333
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1083786059
Short name T372
Test name
Test status
Simulation time 825465000 ps
CPU time 59.6 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:33:11 PM PDT 24
Peak memory 263400 kb
Host smart-0f54aa65-45e7-418b-89e5-3a5bc627229f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083786059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1083786059
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3018781030
Short name T965
Test name
Test status
Simulation time 58716600 ps
CPU time 74.99 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 275968 kb
Host smart-fe8cfcb2-40f3-478d-a402-7e1e230ca2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018781030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3018781030
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.1651150237
Short name T590
Test name
Test status
Simulation time 38074300 ps
CPU time 13.42 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:32:39 PM PDT 24
Peak memory 265208 kb
Host smart-6e440665-c446-46b8-a1ea-ae55ed1044bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651150237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
1651150237
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.1940625361
Short name T482
Test name
Test status
Simulation time 113254100 ps
CPU time 15.99 seconds
Started May 23 01:32:21 PM PDT 24
Finished May 23 01:32:38 PM PDT 24
Peak memory 275940 kb
Host smart-97931cde-0bbc-4562-8619-4e7445428a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940625361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1940625361
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2448023294
Short name T152
Test name
Test status
Simulation time 37577900 ps
CPU time 22.62 seconds
Started May 23 01:32:21 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 265188 kb
Host smart-5522f06a-36a4-4cf3-bd64-737f4d658045
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448023294 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2448023294
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1598244528
Short name T1076
Test name
Test status
Simulation time 8154835800 ps
CPU time 92.03 seconds
Started May 23 01:32:08 PM PDT 24
Finished May 23 01:33:41 PM PDT 24
Peak memory 262684 kb
Host smart-286bf46b-aa3e-4195-ab39-9b808819d1bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598244528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.1598244528
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2184203631
Short name T678
Test name
Test status
Simulation time 780707100 ps
CPU time 137.91 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:34:28 PM PDT 24
Peak memory 293300 kb
Host smart-c734d15e-2b8b-4dae-b855-451dfc76aa4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184203631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2184203631
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2012737114
Short name T406
Test name
Test status
Simulation time 5856191100 ps
CPU time 154.57 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:34:58 PM PDT 24
Peak memory 292292 kb
Host smart-74596d10-7cf6-49a3-8bcf-680b7b4a9b30
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012737114 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2012737114
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1428975266
Short name T611
Test name
Test status
Simulation time 39593900 ps
CPU time 109.99 seconds
Started May 23 01:32:09 PM PDT 24
Finished May 23 01:34:00 PM PDT 24
Peak memory 259988 kb
Host smart-82582659-5c76-40e2-b768-e79927013b67
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428975266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1428975266
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3212649154
Short name T962
Test name
Test status
Simulation time 34642000 ps
CPU time 31.25 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 273588 kb
Host smart-6a534439-639e-4757-997a-6b00277b49c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212649154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3212649154
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3746571640
Short name T899
Test name
Test status
Simulation time 31326200 ps
CPU time 31.56 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:32:59 PM PDT 24
Peak memory 274876 kb
Host smart-52ceba1a-9a79-410b-ba9d-ba1da9c1c06e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746571640 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.3746571640
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.3845530774
Short name T30
Test name
Test status
Simulation time 1632421100 ps
CPU time 67.57 seconds
Started May 23 01:32:24 PM PDT 24
Finished May 23 01:33:33 PM PDT 24
Peak memory 263004 kb
Host smart-c405932c-e461-4317-ace7-5d923a147e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845530774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3845530774
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.958479158
Short name T720
Test name
Test status
Simulation time 59529200 ps
CPU time 169.24 seconds
Started May 23 01:32:10 PM PDT 24
Finished May 23 01:35:01 PM PDT 24
Peak memory 276820 kb
Host smart-b0b22427-ae88-4d76-8c5b-169362318537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958479158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.958479158
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2542445374
Short name T796
Test name
Test status
Simulation time 32178800 ps
CPU time 13.42 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:28:18 PM PDT 24
Peak memory 264260 kb
Host smart-5680c823-4b3d-46ff-83de-1bea321171d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542445374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
542445374
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.992201743
Short name T362
Test name
Test status
Simulation time 63155400 ps
CPU time 13.74 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:28:20 PM PDT 24
Peak memory 265080 kb
Host smart-b4d7ce72-aef7-4ec0-8eae-7a9cc76f285f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992201743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.992201743
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.209301258
Short name T783
Test name
Test status
Simulation time 25915100 ps
CPU time 13.19 seconds
Started May 23 01:28:07 PM PDT 24
Finished May 23 01:28:22 PM PDT 24
Peak memory 275204 kb
Host smart-95b80f0e-c54a-4198-992c-e06c91e07d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209301258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.209301258
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2598750769
Short name T704
Test name
Test status
Simulation time 334606000 ps
CPU time 104.66 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:29:48 PM PDT 24
Peak memory 280872 kb
Host smart-ba42d2a0-ee36-41c8-be63-cfce22723063
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598750769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2598750769
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2897059750
Short name T370
Test name
Test status
Simulation time 28770700 ps
CPU time 22.01 seconds
Started May 23 01:28:07 PM PDT 24
Finished May 23 01:28:31 PM PDT 24
Peak memory 265232 kb
Host smart-339805bf-425f-43ef-b4b4-005cdf2e376e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897059750 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2897059750
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.985025657
Short name T722
Test name
Test status
Simulation time 6749844800 ps
CPU time 2206.66 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 02:04:53 PM PDT 24
Peak memory 264496 kb
Host smart-9433368d-c9b4-4bb9-a993-4cac575448b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985025657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.985025657
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.3021748904
Short name T597
Test name
Test status
Simulation time 1331482400 ps
CPU time 2348.96 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 02:07:16 PM PDT 24
Peak memory 265056 kb
Host smart-eb1d775d-0eff-432d-b1aa-b94e10366afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021748904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3021748904
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.2187040804
Short name T89
Test name
Test status
Simulation time 3625051500 ps
CPU time 934.31 seconds
Started May 23 01:28:08 PM PDT 24
Finished May 23 01:43:45 PM PDT 24
Peak memory 273220 kb
Host smart-6a59cf4e-3ed8-4c83-8807-2da56c363866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187040804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2187040804
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.836256663
Short name T511
Test name
Test status
Simulation time 1887231000 ps
CPU time 30.17 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:28:41 PM PDT 24
Peak memory 265124 kb
Host smart-37d0bd4a-a387-4ceb-9e37-64843e95e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836256663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.836256663
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1450396042
Short name T336
Test name
Test status
Simulation time 1360330900 ps
CPU time 43.07 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:28:49 PM PDT 24
Peak memory 264988 kb
Host smart-56733829-c8ae-4a2f-846d-13aa8dbc798f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450396042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1450396042
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1643604652
Short name T83
Test name
Test status
Simulation time 306172303500 ps
CPU time 4164.99 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 02:37:28 PM PDT 24
Peak memory 265260 kb
Host smart-9c5dedff-336e-4b68-9027-ad00dfd37c9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643604652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1643604652
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.784437528
Short name T85
Test name
Test status
Simulation time 331720316900 ps
CPU time 2084.63 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 02:02:45 PM PDT 24
Peak memory 265244 kb
Host smart-3dcf2704-bf79-44e2-b990-b6bea500e730
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784437528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_host_ctrl_arb.784437528
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.596838015
Short name T265
Test name
Test status
Simulation time 75317000 ps
CPU time 68.66 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:29:14 PM PDT 24
Peak memory 265124 kb
Host smart-47f51deb-a00a-45fe-acf3-09a88ae978c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596838015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.596838015
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.113072578
Short name T175
Test name
Test status
Simulation time 10019441100 ps
CPU time 83.3 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:29:34 PM PDT 24
Peak memory 321860 kb
Host smart-de575b0e-9158-4c77-a4a6-82d8488db357
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113072578 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.113072578
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3621656728
Short name T288
Test name
Test status
Simulation time 28583700 ps
CPU time 13.45 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:28:20 PM PDT 24
Peak memory 265216 kb
Host smart-01edd886-852f-4dfe-8eb2-eba01e065791
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621656728 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3621656728
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.44357342
Short name T124
Test name
Test status
Simulation time 160194871000 ps
CPU time 998.22 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:44:42 PM PDT 24
Peak memory 263912 kb
Host smart-af6c5d7e-57a0-4cf7-a8e1-d78e4dfb5637
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44357342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_hw_rma_reset.44357342
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1572300294
Short name T456
Test name
Test status
Simulation time 1695849900 ps
CPU time 58.91 seconds
Started May 23 01:28:11 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 262496 kb
Host smart-b64cf2ab-a82c-4e96-885d-0709649040e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572300294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1572300294
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3914289921
Short name T202
Test name
Test status
Simulation time 5400623200 ps
CPU time 681.37 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:39:27 PM PDT 24
Peak memory 337452 kb
Host smart-48c470c5-09b8-42c9-bf26-cb4c7524ad7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914289921 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3914289921
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2661559743
Short name T688
Test name
Test status
Simulation time 3492706100 ps
CPU time 227.33 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:31:52 PM PDT 24
Peak memory 283956 kb
Host smart-0ca703b7-f7ab-4bfd-9095-f76637492498
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661559743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2661559743
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2106838723
Short name T665
Test name
Test status
Simulation time 49257831700 ps
CPU time 290.64 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:32:59 PM PDT 24
Peak memory 284232 kb
Host smart-cc9d6cb0-47d1-453d-bb98-972d6bb3d814
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106838723 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2106838723
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.4058070829
Short name T29
Test name
Test status
Simulation time 4015749200 ps
CPU time 76.82 seconds
Started May 23 01:28:08 PM PDT 24
Finished May 23 01:29:27 PM PDT 24
Peak memory 265320 kb
Host smart-fd1b61f3-5d9e-4e2a-9c51-3d54c7dc1886
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058070829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.4058070829
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1765403994
Short name T823
Test name
Test status
Simulation time 59295517200 ps
CPU time 216.19 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:31:45 PM PDT 24
Peak memory 260412 kb
Host smart-82c8e94b-522f-4f05-a23d-a4f9e9a503bf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176
5403994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1765403994
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1175424126
Short name T735
Test name
Test status
Simulation time 15766500 ps
CPU time 13.36 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 264160 kb
Host smart-34abf31e-9586-4eb6-8d43-7e58f47aa268
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175424126 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1175424126
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1955431994
Short name T162
Test name
Test status
Simulation time 1692030700 ps
CPU time 70.93 seconds
Started May 23 01:28:07 PM PDT 24
Finished May 23 01:29:20 PM PDT 24
Peak memory 259632 kb
Host smart-a3c078c1-2d85-4340-9e09-9e82730a43da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955431994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1955431994
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.1580805009
Short name T76
Test name
Test status
Simulation time 17449998600 ps
CPU time 493.77 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:36:17 PM PDT 24
Peak memory 274056 kb
Host smart-b3e8d538-293e-45fa-91b1-5e10734b7ee4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580805009 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.1580805009
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1109514799
Short name T144
Test name
Test status
Simulation time 38705200 ps
CPU time 132.88 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:30:18 PM PDT 24
Peak memory 264440 kb
Host smart-cff57a37-1325-4d4b-8485-0c445ac07eea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109514799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1109514799
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.343612517
Short name T63
Test name
Test status
Simulation time 26912200 ps
CPU time 14.2 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 278304 kb
Host smart-5c0e165f-7909-42f8-90e5-ec17d36f470c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=343612517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.343612517
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.2415361802
Short name T671
Test name
Test status
Simulation time 3085369700 ps
CPU time 385.42 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:34:30 PM PDT 24
Peak memory 262496 kb
Host smart-48aa436f-c26d-450a-b019-74d47bb9e8a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415361802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2415361802
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.4069100525
Short name T14
Test name
Test status
Simulation time 25651400 ps
CPU time 14.07 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 265492 kb
Host smart-4dbce8ec-d780-4042-8986-962d30052038
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069100525 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.4069100525
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.755976844
Short name T546
Test name
Test status
Simulation time 113291000 ps
CPU time 13.46 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:28:22 PM PDT 24
Peak memory 258828 kb
Host smart-449f7672-8a20-4e6c-9ef5-8ff22c2fea8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755976844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.755976844
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3929580834
Short name T839
Test name
Test status
Simulation time 326100100 ps
CPU time 975.04 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:44:18 PM PDT 24
Peak memory 282364 kb
Host smart-583ccf70-5a4b-44e4-80d9-289e0f46bc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929580834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3929580834
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2525803299
Short name T1013
Test name
Test status
Simulation time 4607304300 ps
CPU time 127.35 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 265248 kb
Host smart-475a5764-32c5-475b-aef0-2e5162204e9d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525803299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2525803299
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2581824684
Short name T1003
Test name
Test status
Simulation time 158199400 ps
CPU time 40.55 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:28:49 PM PDT 24
Peak memory 267416 kb
Host smart-b1e16ed5-b20a-4587-bc08-48fe3c96fc3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581824684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2581824684
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1268670932
Short name T948
Test name
Test status
Simulation time 32976200 ps
CPU time 22.51 seconds
Started May 23 01:28:15 PM PDT 24
Finished May 23 01:28:38 PM PDT 24
Peak memory 265276 kb
Host smart-d265c20c-d15a-4d3d-a158-509d46123d0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268670932 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1268670932
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2915045006
Short name T1069
Test name
Test status
Simulation time 42925300 ps
CPU time 22.51 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:28:28 PM PDT 24
Peak memory 265304 kb
Host smart-81562c9f-668b-4d56-8d84-c2c879ae506c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915045006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2915045006
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1813568131
Short name T598
Test name
Test status
Simulation time 1494038700 ps
CPU time 157.31 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:30:42 PM PDT 24
Peak memory 281584 kb
Host smart-2a4a5a1f-ce3e-43dd-a5b0-f21e327bd7ac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813568131 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.1813568131
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.1449128430
Short name T214
Test name
Test status
Simulation time 6004297300 ps
CPU time 131.7 seconds
Started May 23 01:28:08 PM PDT 24
Finished May 23 01:30:22 PM PDT 24
Peak memory 281792 kb
Host smart-ab1d6c27-4246-4d1c-b92f-cd2763beba4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1449128430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1449128430
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1483078324
Short name T620
Test name
Test status
Simulation time 1980404300 ps
CPU time 147.78 seconds
Started May 23 01:28:10 PM PDT 24
Finished May 23 01:30:39 PM PDT 24
Peak memory 289928 kb
Host smart-bb823d02-75d5-4165-b61d-674f9fcc8841
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483078324 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1483078324
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3704163932
Short name T826
Test name
Test status
Simulation time 9564551400 ps
CPU time 599.54 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:38:06 PM PDT 24
Peak memory 309500 kb
Host smart-5bb13ecf-b820-4c50-86b6-ad9cdb81ca54
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704163932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.3704163932
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.4181434780
Short name T985
Test name
Test status
Simulation time 3969348400 ps
CPU time 517.2 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:36:42 PM PDT 24
Peak memory 332824 kb
Host smart-e8853715-acd4-424e-95d5-208ebeeb8b28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181434780 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.4181434780
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.220899230
Short name T578
Test name
Test status
Simulation time 30783200 ps
CPU time 31.38 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:28:40 PM PDT 24
Peak memory 273616 kb
Host smart-95662426-0ac6-47ab-a868-e20313a6eb14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220899230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.220899230
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.632454206
Short name T753
Test name
Test status
Simulation time 41274500 ps
CPU time 30.59 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:28:39 PM PDT 24
Peak memory 275672 kb
Host smart-224ff4f8-bf12-4847-8795-09f01c67dcfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632454206 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.632454206
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.4070755271
Short name T191
Test name
Test status
Simulation time 2694931000 ps
CPU time 4720.78 seconds
Started May 23 01:28:07 PM PDT 24
Finished May 23 02:46:51 PM PDT 24
Peak memory 286136 kb
Host smart-838b23d4-23be-4ec7-9545-c4bffd8aff6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070755271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.4070755271
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1528153238
Short name T326
Test name
Test status
Simulation time 2771796700 ps
CPU time 66.86 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:29:16 PM PDT 24
Peak memory 262988 kb
Host smart-b4f4d13d-b298-47bc-b2cc-0bbaaf72e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528153238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1528153238
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.3447980165
Short name T893
Test name
Test status
Simulation time 1223365600 ps
CPU time 66.03 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:29:12 PM PDT 24
Peak memory 273520 kb
Host smart-2a53fadb-c09a-4174-81f4-2f7e659bcd91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447980165 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.3447980165
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.620193416
Short name T895
Test name
Test status
Simulation time 1377544800 ps
CPU time 70.26 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:29:17 PM PDT 24
Peak memory 273444 kb
Host smart-8e5a2418-9413-4e1c-82e0-adcbd3dc798e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620193416 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.620193416
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.1483239169
Short name T477
Test name
Test status
Simulation time 146795800 ps
CPU time 193.8 seconds
Started May 23 01:28:02 PM PDT 24
Finished May 23 01:31:18 PM PDT 24
Peak memory 279404 kb
Host smart-574ad8e8-eac4-40f3-a022-f420eaf32273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483239169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1483239169
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.3302491435
Short name T434
Test name
Test status
Simulation time 17074800 ps
CPU time 23.76 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:28:29 PM PDT 24
Peak memory 258912 kb
Host smart-c3ae65ac-9148-4e5c-a45f-c80487f9e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302491435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3302491435
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.85013797
Short name T844
Test name
Test status
Simulation time 100445900 ps
CPU time 532.74 seconds
Started May 23 01:28:06 PM PDT 24
Finished May 23 01:37:02 PM PDT 24
Peak memory 280684 kb
Host smart-897bf8e4-7f01-45d0-9caa-7d6fc0847e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85013797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_
all.85013797
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2566717888
Short name T657
Test name
Test status
Simulation time 22957700 ps
CPU time 26.22 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:28:29 PM PDT 24
Peak memory 261396 kb
Host smart-e5153d80-7b63-4591-86d4-336de0e202d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566717888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2566717888
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.3594972190
Short name T646
Test name
Test status
Simulation time 48898805700 ps
CPU time 222.35 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 265080 kb
Host smart-23424e3f-5df2-4d38-bb64-d945ccf39d1d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594972190 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.3594972190
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.3071011238
Short name T662
Test name
Test status
Simulation time 284692000 ps
CPU time 14.53 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:32:39 PM PDT 24
Peak memory 265220 kb
Host smart-4e40e785-770e-4922-b1f6-f05743751e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071011238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
3071011238
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1018048766
Short name T185
Test name
Test status
Simulation time 16383300 ps
CPU time 15.86 seconds
Started May 23 01:32:21 PM PDT 24
Finished May 23 01:32:38 PM PDT 24
Peak memory 275940 kb
Host smart-fbe8e24e-f691-4894-a92d-1e01b0d424cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018048766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1018048766
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1013890244
Short name T1060
Test name
Test status
Simulation time 11030000 ps
CPU time 20.66 seconds
Started May 23 01:32:24 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 265304 kb
Host smart-341b0765-906e-49de-a44c-2ffac64f836c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013890244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1013890244
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.3235507931
Short name T382
Test name
Test status
Simulation time 74000600 ps
CPU time 112.37 seconds
Started May 23 01:32:29 PM PDT 24
Finished May 23 01:34:23 PM PDT 24
Peak memory 261096 kb
Host smart-a45638a8-731e-4e4c-a422-391abc123ad1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235507931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.3235507931
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.4245308672
Short name T391
Test name
Test status
Simulation time 1126279600 ps
CPU time 59.35 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:33:24 PM PDT 24
Peak memory 262516 kb
Host smart-a6c43ca2-630c-47a3-8fd1-dd3f85907446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245308672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.4245308672
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.598039703
Short name T1044
Test name
Test status
Simulation time 201442700 ps
CPU time 97.36 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:34:04 PM PDT 24
Peak memory 276668 kb
Host smart-c41f0243-e2c2-48bf-b316-a905f6ab877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598039703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.598039703
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.401693634
Short name T565
Test name
Test status
Simulation time 451268700 ps
CPU time 13.81 seconds
Started May 23 01:32:31 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 265048 kb
Host smart-4b20b87f-9140-4250-9ce4-279a4b5c5da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401693634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.401693634
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.491908316
Short name T1074
Test name
Test status
Simulation time 14236700 ps
CPU time 13.53 seconds
Started May 23 01:32:20 PM PDT 24
Finished May 23 01:32:34 PM PDT 24
Peak memory 275120 kb
Host smart-f2fb3799-0342-4338-b326-3cfcc8b82b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491908316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.491908316
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.2431511746
Short name T644
Test name
Test status
Simulation time 16388500 ps
CPU time 21.88 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 265236 kb
Host smart-06a0aabc-230a-46f3-95ab-b380eb97398e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431511746 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.2431511746
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.545001072
Short name T318
Test name
Test status
Simulation time 6861357500 ps
CPU time 138.64 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:34:45 PM PDT 24
Peak memory 262504 kb
Host smart-aa6b1bc2-716c-4b49-8fa6-cb92a4d98de0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545001072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.545001072
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.717259976
Short name T1075
Test name
Test status
Simulation time 70472100 ps
CPU time 112.21 seconds
Started May 23 01:32:20 PM PDT 24
Finished May 23 01:34:14 PM PDT 24
Peak memory 264968 kb
Host smart-cc48a6fc-a839-4b38-8c9d-9249285a0506
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717259976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.717259976
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.1702393606
Short name T792
Test name
Test status
Simulation time 25096179600 ps
CPU time 66.35 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:33:30 PM PDT 24
Peak memory 262512 kb
Host smart-4cc28fb0-cdb1-4082-a719-a95a5171d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702393606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1702393606
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1150864141
Short name T891
Test name
Test status
Simulation time 2796982500 ps
CPU time 100.07 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:34:03 PM PDT 24
Peak memory 281532 kb
Host smart-717b55df-bda2-4a6a-a208-41d720c8423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150864141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1150864141
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.4066903325
Short name T679
Test name
Test status
Simulation time 246833900 ps
CPU time 13.61 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:32:38 PM PDT 24
Peak memory 265144 kb
Host smart-05e4141e-1fce-46d3-a5f1-9b2d8478a987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066903325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
4066903325
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.526738307
Short name T768
Test name
Test status
Simulation time 123231000 ps
CPU time 15.93 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 275932 kb
Host smart-cc0e7360-ca5a-492b-8c2b-63d2f6a12317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526738307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.526738307
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.2622375456
Short name T523
Test name
Test status
Simulation time 18931600 ps
CPU time 21.92 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:32:47 PM PDT 24
Peak memory 265280 kb
Host smart-4e4730ed-8767-4ca3-822f-3840148a5458
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622375456 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.2622375456
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2953504155
Short name T908
Test name
Test status
Simulation time 17130133700 ps
CPU time 154.74 seconds
Started May 23 01:32:31 PM PDT 24
Finished May 23 01:35:07 PM PDT 24
Peak memory 262380 kb
Host smart-86cb8db4-a1e5-4fa0-97e8-d6faf8db5fbd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953504155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2953504155
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1400174260
Short name T887
Test name
Test status
Simulation time 38340800 ps
CPU time 130.47 seconds
Started May 23 01:32:29 PM PDT 24
Finished May 23 01:34:41 PM PDT 24
Peak memory 264580 kb
Host smart-1559af12-b697-470e-b60c-170d0d8975b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400174260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1400174260
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2782317183
Short name T929
Test name
Test status
Simulation time 87834100 ps
CPU time 192.86 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:35:40 PM PDT 24
Peak memory 277380 kb
Host smart-21f014ae-490f-4be8-bc06-d33b8082182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782317183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2782317183
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.701084339
Short name T712
Test name
Test status
Simulation time 97536800 ps
CPU time 13.86 seconds
Started May 23 01:32:24 PM PDT 24
Finished May 23 01:32:39 PM PDT 24
Peak memory 265176 kb
Host smart-5b67829c-32d8-4da9-9d1c-e059cdbd1c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701084339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.701084339
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3511697560
Short name T915
Test name
Test status
Simulation time 15261900 ps
CPU time 16.07 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:32:39 PM PDT 24
Peak memory 275664 kb
Host smart-aa8350ff-0969-4b0a-ade2-f9e17d80ba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511697560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3511697560
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3895786323
Short name T381
Test name
Test status
Simulation time 69306600 ps
CPU time 21.98 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:32:46 PM PDT 24
Peak memory 265268 kb
Host smart-37e60a4f-8a66-4bce-9111-e5428fd36cdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895786323 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3895786323
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2780548979
Short name T315
Test name
Test status
Simulation time 8056406100 ps
CPU time 70.29 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:33:35 PM PDT 24
Peak memory 262612 kb
Host smart-4e4e1e06-78cf-4488-a31a-6af6b8ee4a3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780548979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.2780548979
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2041834822
Short name T983
Test name
Test status
Simulation time 147085800 ps
CPU time 108.39 seconds
Started May 23 01:32:20 PM PDT 24
Finished May 23 01:34:09 PM PDT 24
Peak memory 259936 kb
Host smart-833c9fe7-3197-45b2-a983-822788de9b91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041834822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2041834822
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2453276513
Short name T392
Test name
Test status
Simulation time 3613982200 ps
CPU time 50.01 seconds
Started May 23 01:32:23 PM PDT 24
Finished May 23 01:33:15 PM PDT 24
Peak memory 264576 kb
Host smart-d61c1b94-8e57-44d0-a3ff-afc8f79b426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453276513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2453276513
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2210585227
Short name T601
Test name
Test status
Simulation time 35549600 ps
CPU time 99.94 seconds
Started May 23 01:32:21 PM PDT 24
Finished May 23 01:34:02 PM PDT 24
Peak memory 275296 kb
Host smart-36b7d2f9-c3e0-4f6c-bdbd-788fd04b0410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210585227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2210585227
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.199043970
Short name T447
Test name
Test status
Simulation time 20619800 ps
CPU time 13.6 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 265176 kb
Host smart-e0bf8ad7-527f-4f73-81d2-b87be0a91570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199043970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.199043970
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2721169048
Short name T491
Test name
Test status
Simulation time 52501000 ps
CPU time 13.16 seconds
Started May 23 01:32:29 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 275884 kb
Host smart-dc78fe45-317c-4a87-a519-3eda3af55bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721169048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2721169048
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1089438762
Short name T684
Test name
Test status
Simulation time 20716000 ps
CPU time 20.41 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:32:44 PM PDT 24
Peak memory 280776 kb
Host smart-0a6de238-9ee7-4fdd-a843-fcf4f95b490d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089438762 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1089438762
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3652981266
Short name T513
Test name
Test status
Simulation time 35883497200 ps
CPU time 254.71 seconds
Started May 23 01:32:21 PM PDT 24
Finished May 23 01:36:37 PM PDT 24
Peak memory 262644 kb
Host smart-133e6aad-2b19-47c0-818f-d566eb866143
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652981266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3652981266
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2471776881
Short name T921
Test name
Test status
Simulation time 113763500 ps
CPU time 110.96 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:34:14 PM PDT 24
Peak memory 260140 kb
Host smart-a4fe4279-e7e6-46c8-a279-e03da305a43a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471776881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2471776881
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1092795246
Short name T3
Test name
Test status
Simulation time 757559800 ps
CPU time 61.84 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 262564 kb
Host smart-39e6efe5-f118-4d7e-824d-e7135d11e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092795246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1092795246
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3158717486
Short name T494
Test name
Test status
Simulation time 159510400 ps
CPU time 52.3 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:33:19 PM PDT 24
Peak memory 270628 kb
Host smart-23912283-e919-4279-9af0-7e46434c1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158717486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3158717486
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.2376585338
Short name T476
Test name
Test status
Simulation time 119405300 ps
CPU time 13.87 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:32:53 PM PDT 24
Peak memory 264592 kb
Host smart-e69c7491-c553-4e14-b407-c9f403cbc44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376585338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
2376585338
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.383829657
Short name T424
Test name
Test status
Simulation time 31132000 ps
CPU time 15.99 seconds
Started May 23 01:32:38 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 274936 kb
Host smart-5c374286-9b97-4121-ba93-50b586474feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383829657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.383829657
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.1100558223
Short name T991
Test name
Test status
Simulation time 36845300 ps
CPU time 22.26 seconds
Started May 23 01:32:25 PM PDT 24
Finished May 23 01:32:49 PM PDT 24
Peak memory 265212 kb
Host smart-40e739f2-0731-46af-8a41-b2fd880aec6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100558223 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.1100558223
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1576436040
Short name T184
Test name
Test status
Simulation time 39996560000 ps
CPU time 210.53 seconds
Started May 23 01:32:22 PM PDT 24
Finished May 23 01:35:53 PM PDT 24
Peak memory 259444 kb
Host smart-60fccda7-0e6c-4997-b164-04666e37a5b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576436040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.1576436040
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.2612550605
Short name T537
Test name
Test status
Simulation time 34033900 ps
CPU time 216.22 seconds
Started May 23 01:32:29 PM PDT 24
Finished May 23 01:36:07 PM PDT 24
Peak memory 281144 kb
Host smart-d4a35803-1a69-420f-88d5-88e6672a45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612550605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2612550605
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.319461229
Short name T571
Test name
Test status
Simulation time 70786200 ps
CPU time 13.69 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:32:53 PM PDT 24
Peak memory 265076 kb
Host smart-c84ce76f-ee07-4c48-a0a5-82d1c3590060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319461229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.319461229
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.3400401344
Short name T550
Test name
Test status
Simulation time 45181900 ps
CPU time 15.82 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 274936 kb
Host smart-53b9535d-b2d3-4833-9fba-2c6bc191c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400401344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3400401344
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2634274873
Short name T471
Test name
Test status
Simulation time 17925300 ps
CPU time 20.45 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:32:58 PM PDT 24
Peak memory 273600 kb
Host smart-a42c646c-79e0-417f-bf65-14ec146c5ca0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634274873 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2634274873
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3622085298
Short name T322
Test name
Test status
Simulation time 5871160700 ps
CPU time 105.66 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:34:23 PM PDT 24
Peak memory 262596 kb
Host smart-be746295-dc59-4a44-9f8c-03d2f020794a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622085298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3622085298
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3604852481
Short name T13
Test name
Test status
Simulation time 47069400 ps
CPU time 132.15 seconds
Started May 23 01:32:38 PM PDT 24
Finished May 23 01:34:53 PM PDT 24
Peak memory 259796 kb
Host smart-505abbca-33e1-4631-877d-8d71808bd9d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604852481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3604852481
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.244087555
Short name T553
Test name
Test status
Simulation time 4292807100 ps
CPU time 72.08 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:33:50 PM PDT 24
Peak memory 263140 kb
Host smart-66947db2-8ef6-475f-988d-86a546689e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244087555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.244087555
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3206075130
Short name T1001
Test name
Test status
Simulation time 218502400 ps
CPU time 49.65 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:33:29 PM PDT 24
Peak memory 270684 kb
Host smart-03244b1f-8a1a-4480-8354-ac578455d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206075130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3206075130
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2996343075
Short name T865
Test name
Test status
Simulation time 31725900 ps
CPU time 13.51 seconds
Started May 23 01:32:38 PM PDT 24
Finished May 23 01:32:54 PM PDT 24
Peak memory 265140 kb
Host smart-f634fc85-4cff-4808-adf5-834ce9396707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996343075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2996343075
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.3203984194
Short name T564
Test name
Test status
Simulation time 44003500 ps
CPU time 15.88 seconds
Started May 23 01:32:38 PM PDT 24
Finished May 23 01:32:56 PM PDT 24
Peak memory 275704 kb
Host smart-f48559f0-99ef-436d-8760-8ad773c10933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203984194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3203984194
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.707971181
Short name T365
Test name
Test status
Simulation time 15961500 ps
CPU time 22.37 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:33:01 PM PDT 24
Peak memory 273380 kb
Host smart-00a92c9f-f275-4244-92e0-df02ecd50c3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707971181 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.707971181
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3244692491
Short name T818
Test name
Test status
Simulation time 1567868200 ps
CPU time 59.03 seconds
Started May 23 01:32:38 PM PDT 24
Finished May 23 01:33:40 PM PDT 24
Peak memory 262684 kb
Host smart-5b2933c5-daed-41cf-9dc8-a3d3dd288b52
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244692491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.3244692491
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2228725804
Short name T941
Test name
Test status
Simulation time 90318100 ps
CPU time 111.23 seconds
Started May 23 01:32:40 PM PDT 24
Finished May 23 01:34:33 PM PDT 24
Peak memory 260920 kb
Host smart-6cc553b1-3b9e-4ba4-96d2-ac9ca44ba330
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228725804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2228725804
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3701162388
Short name T672
Test name
Test status
Simulation time 37196800 ps
CPU time 170 seconds
Started May 23 01:32:35 PM PDT 24
Finished May 23 01:35:27 PM PDT 24
Peak memory 276712 kb
Host smart-6f997faf-1fd9-474c-8ad4-d639cee236c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701162388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3701162388
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.3030125147
Short name T555
Test name
Test status
Simulation time 44432100 ps
CPU time 13.85 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:32:52 PM PDT 24
Peak memory 258132 kb
Host smart-d66f3798-98e6-4a47-bff5-76980b4f11ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030125147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
3030125147
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3972396225
Short name T567
Test name
Test status
Simulation time 26711100 ps
CPU time 15.83 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:32:54 PM PDT 24
Peak memory 274956 kb
Host smart-4c1901ab-71f7-4bba-b125-88f4ccfea37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972396225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3972396225
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.3294474864
Short name T366
Test name
Test status
Simulation time 10959100 ps
CPU time 22.02 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:33:00 PM PDT 24
Peak memory 273636 kb
Host smart-2ca395f3-e581-46fc-a040-331f81c23e24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294474864 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.3294474864
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2755012184
Short name T314
Test name
Test status
Simulation time 39543736800 ps
CPU time 111.66 seconds
Started May 23 01:32:35 PM PDT 24
Finished May 23 01:34:28 PM PDT 24
Peak memory 262632 kb
Host smart-2e0435d0-1ae5-4084-808a-ba8d1c0c0352
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755012184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2755012184
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2843083416
Short name T871
Test name
Test status
Simulation time 132997700 ps
CPU time 135.35 seconds
Started May 23 01:32:35 PM PDT 24
Finished May 23 01:34:52 PM PDT 24
Peak memory 260968 kb
Host smart-05de32f1-87a1-420a-8f36-65614ecb2b9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843083416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2843083416
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2737363325
Short name T584
Test name
Test status
Simulation time 4890073500 ps
CPU time 77.96 seconds
Started May 23 01:32:35 PM PDT 24
Finished May 23 01:33:55 PM PDT 24
Peak memory 263000 kb
Host smart-2f6dc2d1-4c6b-4d0e-b235-bcbcd50b80a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737363325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2737363325
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2154211429
Short name T1081
Test name
Test status
Simulation time 1398484100 ps
CPU time 148.14 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:35:07 PM PDT 24
Peak memory 281240 kb
Host smart-dcb19645-02a1-4e7e-8e4f-26c13186c90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154211429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2154211429
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.831954190
Short name T181
Test name
Test status
Simulation time 168128100 ps
CPU time 13.92 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:33:05 PM PDT 24
Peak memory 265116 kb
Host smart-44512fd8-1a84-4b07-9267-b482416f6a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831954190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.831954190
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2487967580
Short name T690
Test name
Test status
Simulation time 16286700 ps
CPU time 15.88 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:33:06 PM PDT 24
Peak memory 275048 kb
Host smart-e1f43c23-5afa-47b1-97c8-436a86ec5956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487967580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2487967580
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.958133631
Short name T380
Test name
Test status
Simulation time 20139300 ps
CPU time 22.52 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:33:02 PM PDT 24
Peak memory 273496 kb
Host smart-d4bdea1f-3428-4fd0-9cc2-19e8571590b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958133631 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.958133631
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3510902324
Short name T966
Test name
Test status
Simulation time 2526058000 ps
CPU time 89.42 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:34:10 PM PDT 24
Peak memory 262544 kb
Host smart-1f1f4781-a6ec-4eb6-8b6c-8f2add290b0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510902324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3510902324
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.3766329489
Short name T716
Test name
Test status
Simulation time 44073800 ps
CPU time 130.79 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:34:51 PM PDT 24
Peak memory 261044 kb
Host smart-81803d2f-3c91-4f4e-99c5-6be67bf9df60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766329489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.3766329489
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.4281090280
Short name T718
Test name
Test status
Simulation time 13453939300 ps
CPU time 76.72 seconds
Started May 23 01:32:36 PM PDT 24
Finished May 23 01:33:55 PM PDT 24
Peak memory 262880 kb
Host smart-f4da1c64-0dd2-4ff1-9a53-e22b10868cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281090280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.4281090280
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2807229601
Short name T894
Test name
Test status
Simulation time 81574000 ps
CPU time 148.1 seconds
Started May 23 01:32:37 PM PDT 24
Finished May 23 01:35:07 PM PDT 24
Peak memory 278768 kb
Host smart-73276621-40b7-48d1-a513-056d49d9f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807229601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2807229601
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.321081613
Short name T431
Test name
Test status
Simulation time 35331500 ps
CPU time 13.75 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:28:35 PM PDT 24
Peak memory 265148 kb
Host smart-f32d89d8-fc25-41a7-9a82-c9dce42c54b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321081613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.321081613
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.322855170
Short name T514
Test name
Test status
Simulation time 15520000 ps
CPU time 20.74 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:28:43 PM PDT 24
Peak memory 265236 kb
Host smart-beb71f85-fff7-4bdb-96e6-13084cc3edde
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322855170 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.322855170
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3388037083
Short name T296
Test name
Test status
Simulation time 12939705900 ps
CPU time 2233.81 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 02:05:18 PM PDT 24
Peak memory 264536 kb
Host smart-d8ad8c0f-b32d-448a-aa3a-b4424de036eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388037083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3388037083
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1059243841
Short name T841
Test name
Test status
Simulation time 596043900 ps
CPU time 816.2 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:41:42 PM PDT 24
Peak memory 273276 kb
Host smart-dc6f8832-c4c0-42b2-8b44-b46bd89e5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059243841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1059243841
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1482453833
Short name T603
Test name
Test status
Simulation time 1531245300 ps
CPU time 23.27 seconds
Started May 23 01:28:07 PM PDT 24
Finished May 23 01:28:33 PM PDT 24
Peak memory 265120 kb
Host smart-f295a48b-6b0f-4058-9144-948f6570a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482453833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1482453833
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2745190796
Short name T788
Test name
Test status
Simulation time 10026223500 ps
CPU time 71.04 seconds
Started May 23 01:28:17 PM PDT 24
Finished May 23 01:29:28 PM PDT 24
Peak memory 305168 kb
Host smart-7845a623-1597-4391-aa8f-9c322de21825
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745190796 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2745190796
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1123107447
Short name T703
Test name
Test status
Simulation time 21413800 ps
CPU time 13.37 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:28:36 PM PDT 24
Peak memory 264236 kb
Host smart-8ebb983d-5868-4ec5-8792-489fedd5c334
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123107447 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1123107447
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.686417297
Short name T846
Test name
Test status
Simulation time 160184172900 ps
CPU time 862.17 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 264264 kb
Host smart-8042d0d0-7243-4391-b65d-72a35a6cd100
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686417297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.686417297
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.3184283253
Short name T739
Test name
Test status
Simulation time 7916440300 ps
CPU time 114.09 seconds
Started May 23 01:28:04 PM PDT 24
Finished May 23 01:30:01 PM PDT 24
Peak memory 262424 kb
Host smart-bff73e0e-7888-4b98-84ae-d7b89f65db35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184283253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.3184283253
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.715592290
Short name T349
Test name
Test status
Simulation time 1611313200 ps
CPU time 209.02 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:31:40 PM PDT 24
Peak memory 289832 kb
Host smart-e9f1c6b2-ca4a-4820-b1b5-59df33a3a5e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715592290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.715592290
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3209390658
Short name T876
Test name
Test status
Simulation time 8802039700 ps
CPU time 70.81 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:29:31 PM PDT 24
Peak memory 259772 kb
Host smart-a6374506-9203-4880-9a2c-1415881154cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209390658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3209390658
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4221392123
Short name T481
Test name
Test status
Simulation time 21626339300 ps
CPU time 176.19 seconds
Started May 23 01:28:13 PM PDT 24
Finished May 23 01:31:11 PM PDT 24
Peak memory 259620 kb
Host smart-66c94e21-9d2c-4526-a7c1-c8ad53709973
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422
1392123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.4221392123
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1406649353
Short name T636
Test name
Test status
Simulation time 2012635800 ps
CPU time 87.56 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:29:51 PM PDT 24
Peak memory 263264 kb
Host smart-dfdc6dd7-0b82-4086-ab86-f211478e6f1f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406649353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1406649353
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1726241035
Short name T663
Test name
Test status
Simulation time 48140400 ps
CPU time 13.41 seconds
Started May 23 01:28:12 PM PDT 24
Finished May 23 01:28:26 PM PDT 24
Peak memory 265200 kb
Host smart-4bfb73d9-f65f-40af-9c39-8f000301228c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726241035 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1726241035
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3131202932
Short name T1021
Test name
Test status
Simulation time 39702894600 ps
CPU time 741.03 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:40:26 PM PDT 24
Peak memory 273368 kb
Host smart-4ad7e699-01e0-4512-9f5c-177233646b3a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131202932 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3131202932
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.3972555918
Short name T423
Test name
Test status
Simulation time 81069800 ps
CPU time 108.91 seconds
Started May 23 01:28:03 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 259980 kb
Host smart-8a2b6781-1325-4098-a039-54d384f66f87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972555918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.3972555918
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.4004875015
Short name T1054
Test name
Test status
Simulation time 3787582300 ps
CPU time 441.98 seconds
Started May 23 01:27:59 PM PDT 24
Finished May 23 01:35:22 PM PDT 24
Peak memory 262308 kb
Host smart-a72e417c-101a-473a-a452-d60be2fe1332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004875015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.4004875015
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3152116716
Short name T543
Test name
Test status
Simulation time 2234346900 ps
CPU time 148.31 seconds
Started May 23 01:28:14 PM PDT 24
Finished May 23 01:30:43 PM PDT 24
Peak memory 259060 kb
Host smart-7a3ed1a5-66f3-42ab-87a4-35b043569833
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152116716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3152116716
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.376854043
Short name T705
Test name
Test status
Simulation time 121621400 ps
CPU time 492.25 seconds
Started May 23 01:28:00 PM PDT 24
Finished May 23 01:36:16 PM PDT 24
Peak memory 283152 kb
Host smart-363c753e-1617-4bf5-bc35-ea722065421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376854043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.376854043
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1804448172
Short name T226
Test name
Test status
Simulation time 338601400 ps
CPU time 36.93 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:28:48 PM PDT 24
Peak memory 273588 kb
Host smart-fd7bc5bb-dad6-4853-a7b2-82037cbad2c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804448172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1804448172
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.751915481
Short name T1012
Test name
Test status
Simulation time 1054085100 ps
CPU time 124.74 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 281732 kb
Host smart-d31e1700-6a7f-44fd-b4ba-ff426388c12d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751915481 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_ro.751915481
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.2004467656
Short name T848
Test name
Test status
Simulation time 656753600 ps
CPU time 138.35 seconds
Started May 23 01:28:13 PM PDT 24
Finished May 23 01:30:32 PM PDT 24
Peak memory 281712 kb
Host smart-c80d39e0-2e32-4111-a10c-554eac74e6a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2004467656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2004467656
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.1362122188
Short name T2
Test name
Test status
Simulation time 997280600 ps
CPU time 130.34 seconds
Started May 23 01:28:16 PM PDT 24
Finished May 23 01:30:27 PM PDT 24
Peak memory 281660 kb
Host smart-a67e48ce-4fd8-4ecb-b698-2eba07558482
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362122188 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.1362122188
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.1466282485
Short name T625
Test name
Test status
Simulation time 7666361300 ps
CPU time 455.45 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:36:03 PM PDT 24
Peak memory 313856 kb
Host smart-8364ea91-20e2-4483-9a71-30c935a0ec92
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466282485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.1466282485
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.4093133667
Short name T218
Test name
Test status
Simulation time 4509281800 ps
CPU time 650.23 seconds
Started May 23 01:28:18 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 321620 kb
Host smart-ac240508-0483-4d45-942e-2fbb8660f691
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093133667 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.4093133667
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1650018124
Short name T20
Test name
Test status
Simulation time 151091300 ps
CPU time 31.74 seconds
Started May 23 01:28:12 PM PDT 24
Finished May 23 01:28:45 PM PDT 24
Peak memory 273568 kb
Host smart-029a25b4-91b9-409b-b472-288617624010
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650018124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1650018124
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.992762823
Short name T107
Test name
Test status
Simulation time 53158900 ps
CPU time 30.64 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:28:58 PM PDT 24
Peak memory 272736 kb
Host smart-2671bf48-1d40-4cb3-b705-3be3b5ca29da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992762823 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.992762823
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.3600872255
Short name T769
Test name
Test status
Simulation time 2778893200 ps
CPU time 475.02 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:36:23 PM PDT 24
Peak memory 311784 kb
Host smart-80064481-ff5b-4663-853d-31a6cceb9d91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600872255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.3600872255
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2634858881
Short name T389
Test name
Test status
Simulation time 4504733400 ps
CPU time 65.33 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:29:26 PM PDT 24
Peak memory 263456 kb
Host smart-8e79f9de-ebd6-4b7c-ab98-4b62570746f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634858881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2634858881
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.1687774029
Short name T687
Test name
Test status
Simulation time 90081900 ps
CPU time 216.58 seconds
Started May 23 01:28:01 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 277308 kb
Host smart-27c030b8-f4d3-4743-9010-f714960c7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687774029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1687774029
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.451894719
Short name T627
Test name
Test status
Simulation time 8497539300 ps
CPU time 179.56 seconds
Started May 23 01:28:09 PM PDT 24
Finished May 23 01:31:10 PM PDT 24
Peak memory 265072 kb
Host smart-56385ad0-1df8-4d09-ad6b-b8d4aa7c59d2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451894719 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_wo.451894719
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1612160096
Short name T117
Test name
Test status
Simulation time 16081800 ps
CPU time 15.78 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:33:06 PM PDT 24
Peak memory 276032 kb
Host smart-c882639f-551e-459f-a605-34afba27d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612160096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1612160096
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3350651831
Short name T138
Test name
Test status
Simulation time 55631700 ps
CPU time 130.25 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:35:00 PM PDT 24
Peak memory 259936 kb
Host smart-b81baed9-c81e-4335-aa32-965f46ffeaa2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350651831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3350651831
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.1243738302
Short name T416
Test name
Test status
Simulation time 23835700 ps
CPU time 15.9 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:06 PM PDT 24
Peak memory 275132 kb
Host smart-01788f01-f9d4-4a27-aca7-72f89bed31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243738302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1243738302
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3446730599
Short name T1037
Test name
Test status
Simulation time 52901900 ps
CPU time 16.06 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:07 PM PDT 24
Peak memory 276052 kb
Host smart-c7bf6c27-0249-49a3-b402-fee80b795770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446730599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3446730599
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2504729246
Short name T919
Test name
Test status
Simulation time 35318200 ps
CPU time 132.22 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 264144 kb
Host smart-232bcc4a-101b-4b93-918e-1110e971fdcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504729246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2504729246
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2390789809
Short name T843
Test name
Test status
Simulation time 16442400 ps
CPU time 15.99 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:33:08 PM PDT 24
Peak memory 275060 kb
Host smart-d99fd5f2-f115-469e-88f6-9eb19e0508d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390789809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2390789809
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.3482089245
Short name T486
Test name
Test status
Simulation time 44720700 ps
CPU time 132.01 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:35:01 PM PDT 24
Peak memory 260956 kb
Host smart-be2592ed-f417-4c7a-915b-3847329cbee0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482089245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.3482089245
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.656721150
Short name T487
Test name
Test status
Simulation time 41720400 ps
CPU time 16.18 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:07 PM PDT 24
Peak memory 275004 kb
Host smart-f45b778e-c0e0-46be-bf65-4f9a1c8d9ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656721150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.656721150
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1311550345
Short name T958
Test name
Test status
Simulation time 449427800 ps
CPU time 110.16 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:34:44 PM PDT 24
Peak memory 261016 kb
Host smart-369d31c2-2514-4e82-ab8f-edd0562540ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311550345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1311550345
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.1895270867
Short name T442
Test name
Test status
Simulation time 46184800 ps
CPU time 16.19 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:33:10 PM PDT 24
Peak memory 275452 kb
Host smart-531928d6-92cf-4e63-8601-5f81d28e06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895270867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1895270867
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.360356877
Short name T992
Test name
Test status
Simulation time 144699900 ps
CPU time 133.34 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 259888 kb
Host smart-c1366633-40a1-4b78-8907-c3ff4215f385
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360356877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.360356877
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.457325664
Short name T99
Test name
Test status
Simulation time 21951400 ps
CPU time 13.83 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:33:05 PM PDT 24
Peak memory 275944 kb
Host smart-02ca9abb-045d-4dfd-8d66-e9a10d65241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457325664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.457325664
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2922854751
Short name T779
Test name
Test status
Simulation time 78698300 ps
CPU time 135.23 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:35:09 PM PDT 24
Peak memory 264224 kb
Host smart-3fddf87f-949d-4010-9a7b-aad8e78a6351
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922854751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2922854751
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2907417718
Short name T731
Test name
Test status
Simulation time 13719900 ps
CPU time 13.33 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:04 PM PDT 24
Peak memory 275072 kb
Host smart-4366bc0e-61a1-41a6-906e-fe09ae9086ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907417718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2907417718
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3408782462
Short name T384
Test name
Test status
Simulation time 561091800 ps
CPU time 131.62 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 261112 kb
Host smart-aa58598b-0a84-4046-98b0-faa15510577b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408782462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3408782462
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2169237951
Short name T520
Test name
Test status
Simulation time 28555400 ps
CPU time 15.95 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:33:09 PM PDT 24
Peak memory 275080 kb
Host smart-5928923e-2377-4640-9acc-e1e50419e529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169237951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2169237951
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1962058907
Short name T832
Test name
Test status
Simulation time 131992900 ps
CPU time 134.23 seconds
Started May 23 01:32:51 PM PDT 24
Finished May 23 01:35:06 PM PDT 24
Peak memory 259940 kb
Host smart-d6fa2c41-2df0-4eab-8e27-d87b07a8c9d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962058907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1962058907
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.745021509
Short name T880
Test name
Test status
Simulation time 15859200 ps
CPU time 13.46 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:04 PM PDT 24
Peak memory 275520 kb
Host smart-fc27007b-c60a-4c3f-b222-39d4f81ffe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745021509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.745021509
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2648957032
Short name T879
Test name
Test status
Simulation time 145764600 ps
CPU time 132.73 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 259996 kb
Host smart-666602f9-3ca3-4ba5-b645-51d283198749
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648957032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2648957032
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.1144575759
Short name T875
Test name
Test status
Simulation time 99347200 ps
CPU time 14.26 seconds
Started May 23 01:28:15 PM PDT 24
Finished May 23 01:28:30 PM PDT 24
Peak memory 265100 kb
Host smart-2af7b2a0-0570-4864-912d-c6028c5287b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144575759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1
144575759
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.951818844
Short name T748
Test name
Test status
Simulation time 14958100 ps
CPU time 15.6 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:28:39 PM PDT 24
Peak memory 275528 kb
Host smart-97bfac92-ae33-4e8e-a3e8-48ae8451fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951818844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.951818844
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.1790413146
Short name T811
Test name
Test status
Simulation time 14187300 ps
CPU time 22.82 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:28:47 PM PDT 24
Peak memory 264964 kb
Host smart-106225de-cc48-4dd7-869d-6e33f37fe5e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790413146 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.1790413146
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2933544866
Short name T1080
Test name
Test status
Simulation time 5477241300 ps
CPU time 2249.34 seconds
Started May 23 01:28:15 PM PDT 24
Finished May 23 02:05:46 PM PDT 24
Peak memory 265044 kb
Host smart-9c065a93-9608-4a0c-917b-82f222829a2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933544866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.2933544866
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.939438168
Short name T641
Test name
Test status
Simulation time 310798000 ps
CPU time 740.02 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:40:41 PM PDT 24
Peak memory 264692 kb
Host smart-6d70cd45-c9b3-412f-9d6d-cbf341d83106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939438168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.939438168
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1552812615
Short name T1070
Test name
Test status
Simulation time 10045323300 ps
CPU time 53.17 seconds
Started May 23 01:28:14 PM PDT 24
Finished May 23 01:29:09 PM PDT 24
Peak memory 281892 kb
Host smart-18bc0412-eb0f-4645-bcae-8194c855e4be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552812615 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1552812615
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3425941790
Short name T169
Test name
Test status
Simulation time 21883900 ps
CPU time 13.18 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:28:38 PM PDT 24
Peak memory 265152 kb
Host smart-3eeb2c2b-2b85-49f8-bcc2-79ce27667e7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425941790 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3425941790
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2122741250
Short name T1050
Test name
Test status
Simulation time 80148107000 ps
CPU time 852.24 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:42:33 PM PDT 24
Peak memory 263324 kb
Host smart-10f8f42c-346a-445e-940b-1ffeb266fb6b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122741250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.2122741250
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3688156274
Short name T780
Test name
Test status
Simulation time 748313800 ps
CPU time 72.93 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:29:34 PM PDT 24
Peak memory 262528 kb
Host smart-b9ca8719-d203-4daa-9bd2-60b9d4e63276
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688156274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3688156274
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.2098873714
Short name T34
Test name
Test status
Simulation time 6684293200 ps
CPU time 227.63 seconds
Started May 23 01:28:17 PM PDT 24
Finished May 23 01:32:06 PM PDT 24
Peak memory 284064 kb
Host smart-30b83d73-2322-4fe4-8562-4d36e85bc328
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098873714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.2098873714
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.776989617
Short name T812
Test name
Test status
Simulation time 104336583600 ps
CPU time 306.59 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:33:31 PM PDT 24
Peak memory 293304 kb
Host smart-45dfc792-c46e-43b7-bb1a-b6880d284ee8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776989617 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.776989617
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3839794328
Short name T604
Test name
Test status
Simulation time 1961733400 ps
CPU time 64.8 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:29:25 PM PDT 24
Peak memory 265132 kb
Host smart-886d30b2-3eef-4fcd-a272-e40e637c5475
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839794328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3839794328
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4290286174
Short name T575
Test name
Test status
Simulation time 133034757700 ps
CPU time 246.33 seconds
Started May 23 01:28:24 PM PDT 24
Finished May 23 01:32:31 PM PDT 24
Peak memory 265224 kb
Host smart-3d56eb89-ffc7-44c3-a206-9f11dd957b98
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429
0286174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.4290286174
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.195523244
Short name T5
Test name
Test status
Simulation time 4017419500 ps
CPU time 72.26 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:29:40 PM PDT 24
Peak memory 260192 kb
Host smart-879e9db7-8f45-4e00-969b-93e9613833ca
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195523244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.195523244
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2714745738
Short name T129
Test name
Test status
Simulation time 16118300 ps
CPU time 13.32 seconds
Started May 23 01:28:24 PM PDT 24
Finished May 23 01:28:38 PM PDT 24
Peak memory 265228 kb
Host smart-b0460749-51fd-4ed5-8088-cdd683aa8dac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714745738 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2714745738
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1269493467
Short name T628
Test name
Test status
Simulation time 2449187300 ps
CPU time 176.87 seconds
Started May 23 01:28:18 PM PDT 24
Finished May 23 01:31:15 PM PDT 24
Peak memory 265228 kb
Host smart-72f32d4f-b424-4fe7-890b-1929e80710d0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269493467 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.1269493467
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.1081904948
Short name T133
Test name
Test status
Simulation time 37475300 ps
CPU time 134.21 seconds
Started May 23 01:28:13 PM PDT 24
Finished May 23 01:30:28 PM PDT 24
Peak memory 261000 kb
Host smart-d43df83c-ed78-4498-8b52-fa667ca51267
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081904948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.1081904948
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3220123955
Short name T1051
Test name
Test status
Simulation time 149105300 ps
CPU time 366.75 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 01:34:30 PM PDT 24
Peak memory 262388 kb
Host smart-f405a442-9c76-470f-b3cd-6961b8f0bace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220123955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3220123955
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1947285405
Short name T593
Test name
Test status
Simulation time 8530309500 ps
CPU time 148.89 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:30:54 PM PDT 24
Peak memory 259596 kb
Host smart-4bdaf445-aea1-4b49-a75e-c7cfb63c23b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947285405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1947285405
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.2530682670
Short name T964
Test name
Test status
Simulation time 627881000 ps
CPU time 1285.77 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:49:50 PM PDT 24
Peak memory 286008 kb
Host smart-ece4fda5-efc7-4cf7-b579-b731ab2e58fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530682670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2530682670
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.509600533
Short name T633
Test name
Test status
Simulation time 203627700 ps
CPU time 37.41 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:29:02 PM PDT 24
Peak memory 273588 kb
Host smart-65507bde-581c-4f8c-9c5a-a1a1ec18808c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509600533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.509600533
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.994743128
Short name T707
Test name
Test status
Simulation time 2359540900 ps
CPU time 106.96 seconds
Started May 23 01:28:27 PM PDT 24
Finished May 23 01:30:15 PM PDT 24
Peak memory 296740 kb
Host smart-34339245-755b-4ce6-b119-1b71f626a79d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994743128 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.994743128
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.2485208804
Short name T1043
Test name
Test status
Simulation time 1250348300 ps
CPU time 144.81 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:30:46 PM PDT 24
Peak memory 281652 kb
Host smart-873712a6-9371-46f3-a3e8-5fcf3f4ce5c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2485208804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2485208804
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.127944339
Short name T517
Test name
Test status
Simulation time 1886583900 ps
CPU time 132.97 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 01:30:37 PM PDT 24
Peak memory 294528 kb
Host smart-9830811a-7413-4f9b-83a9-84596a04627a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127944339 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.127944339
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.4020082242
Short name T206
Test name
Test status
Simulation time 8170863400 ps
CPU time 598.06 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:38:19 PM PDT 24
Peak memory 312352 kb
Host smart-7a89cb33-2058-4637-929a-eb02d347d4ab
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020082242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.4020082242
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.952394813
Short name T765
Test name
Test status
Simulation time 11145605200 ps
CPU time 603.09 seconds
Started May 23 01:28:24 PM PDT 24
Finished May 23 01:38:28 PM PDT 24
Peak memory 340368 kb
Host smart-01fb9714-1ae8-4634-9e1a-3ebe4fc04c05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952394813 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.952394813
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.881171955
Short name T475
Test name
Test status
Simulation time 77067200 ps
CPU time 31.81 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:28:53 PM PDT 24
Peak memory 274468 kb
Host smart-ff2c07b6-0286-41a2-bfd8-7fbdfab72102
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881171955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_rw_evict.881171955
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1464661800
Short name T1085
Test name
Test status
Simulation time 39128500 ps
CPU time 31.34 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 01:28:55 PM PDT 24
Peak memory 276176 kb
Host smart-3bd9790f-88bc-48f4-97b6-ff7dd86564ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464661800 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1464661800
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1092694385
Short name T694
Test name
Test status
Simulation time 7174393000 ps
CPU time 75.81 seconds
Started May 23 01:28:27 PM PDT 24
Finished May 23 01:29:44 PM PDT 24
Peak memory 262388 kb
Host smart-e9de1ae2-0aa0-416c-8f80-15dd3e87aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092694385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1092694385
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1150143923
Short name T757
Test name
Test status
Simulation time 2873932900 ps
CPU time 200.85 seconds
Started May 23 01:28:08 PM PDT 24
Finished May 23 01:31:31 PM PDT 24
Peak memory 281440 kb
Host smart-63c12afc-15d9-4219-aca9-893c2dba2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150143923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1150143923
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.2719026410
Short name T730
Test name
Test status
Simulation time 1746948300 ps
CPU time 134.56 seconds
Started May 23 01:28:21 PM PDT 24
Finished May 23 01:30:38 PM PDT 24
Peak memory 264952 kb
Host smart-97087ef1-aff4-4ffa-9d87-8165546448c1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719026410 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.2719026410
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1817183509
Short name T1052
Test name
Test status
Simulation time 19721900 ps
CPU time 15.67 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:33:05 PM PDT 24
Peak memory 275644 kb
Host smart-7200494a-d784-4eac-9f50-ea1203cecc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817183509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1817183509
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3156286801
Short name T738
Test name
Test status
Simulation time 36559400 ps
CPU time 109.28 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:34:39 PM PDT 24
Peak memory 259828 kb
Host smart-f41f6e73-b1dc-4dd2-b00c-af6f75905b8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156286801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3156286801
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1771567025
Short name T189
Test name
Test status
Simulation time 14416900 ps
CPU time 15.64 seconds
Started May 23 01:32:53 PM PDT 24
Finished May 23 01:33:10 PM PDT 24
Peak memory 275568 kb
Host smart-8dc4d338-9996-416d-8844-855143f18001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771567025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1771567025
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2018819500
Short name T149
Test name
Test status
Simulation time 51042100 ps
CPU time 133.27 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:35:05 PM PDT 24
Peak memory 261044 kb
Host smart-f90b3b6e-6f16-40fe-9230-72d0fd551f51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018819500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2018819500
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3356246955
Short name T1092
Test name
Test status
Simulation time 21506000 ps
CPU time 16.12 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:33:10 PM PDT 24
Peak memory 276072 kb
Host smart-1a8e39d6-8e8b-4430-8df6-b94a2c4f5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356246955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3356246955
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1738002717
Short name T528
Test name
Test status
Simulation time 69691200 ps
CPU time 131.57 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:35:03 PM PDT 24
Peak memory 260088 kb
Host smart-da6011a2-8454-4096-8dc6-e0e5026cf20f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738002717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1738002717
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3632043766
Short name T737
Test name
Test status
Simulation time 35102000 ps
CPU time 13.39 seconds
Started May 23 01:32:48 PM PDT 24
Finished May 23 01:33:03 PM PDT 24
Peak memory 274788 kb
Host smart-d2292588-d374-434d-9144-95f1a90057f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632043766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3632043766
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.419074086
Short name T866
Test name
Test status
Simulation time 285826500 ps
CPU time 131.21 seconds
Started May 23 01:32:50 PM PDT 24
Finished May 23 01:35:02 PM PDT 24
Peak memory 259892 kb
Host smart-56c6bb8c-1257-4833-9d5c-37c0e76d651d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419074086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.419074086
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2782162035
Short name T904
Test name
Test status
Simulation time 26723200 ps
CPU time 15.98 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:33:09 PM PDT 24
Peak memory 275256 kb
Host smart-27ad950c-f02c-4886-ac17-a005cb35b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782162035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2782162035
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3264584499
Short name T426
Test name
Test status
Simulation time 16002400 ps
CPU time 16.22 seconds
Started May 23 01:32:51 PM PDT 24
Finished May 23 01:33:08 PM PDT 24
Peak memory 276052 kb
Host smart-8c91a1bd-f9ed-4491-933c-869ce962f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264584499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3264584499
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3780758639
Short name T708
Test name
Test status
Simulation time 41458000 ps
CPU time 131.96 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:35:06 PM PDT 24
Peak memory 259708 kb
Host smart-2678d69b-e483-4f64-bf38-57cb185e83c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780758639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3780758639
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.3052587896
Short name T498
Test name
Test status
Simulation time 22513100 ps
CPU time 13.31 seconds
Started May 23 01:32:49 PM PDT 24
Finished May 23 01:33:04 PM PDT 24
Peak memory 275616 kb
Host smart-d253a8f1-aa33-4a8e-bcdc-ab8317e0bf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052587896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3052587896
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.1007305851
Short name T706
Test name
Test status
Simulation time 41533100 ps
CPU time 110.67 seconds
Started May 23 01:32:52 PM PDT 24
Finished May 23 01:34:44 PM PDT 24
Peak memory 259968 kb
Host smart-76857524-b30b-4d78-aebf-e4a3d0d2d6f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007305851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.1007305851
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.2698669089
Short name T609
Test name
Test status
Simulation time 23245100 ps
CPU time 13.49 seconds
Started May 23 01:33:07 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 275096 kb
Host smart-81e2bc9a-2fb3-45e5-be39-97d482a63d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698669089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2698669089
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.1876875463
Short name T666
Test name
Test status
Simulation time 113250500 ps
CPU time 134.81 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:35:21 PM PDT 24
Peak memory 259780 kb
Host smart-939333f6-a8c4-486f-9f67-a66e36926130
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876875463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.1876875463
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.3830097776
Short name T978
Test name
Test status
Simulation time 26602600 ps
CPU time 16.15 seconds
Started May 23 01:33:07 PM PDT 24
Finished May 23 01:33:25 PM PDT 24
Peak memory 274992 kb
Host smart-36cd35dd-bfa0-4188-912b-ac386b678128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830097776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3830097776
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.4052238468
Short name T467
Test name
Test status
Simulation time 72721600 ps
CPU time 131.96 seconds
Started May 23 01:33:06 PM PDT 24
Finished May 23 01:35:20 PM PDT 24
Peak memory 259892 kb
Host smart-34e11fa5-819f-4aa9-b721-3c0aaf2432f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052238468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.4052238468
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.1894747804
Short name T1015
Test name
Test status
Simulation time 29876600 ps
CPU time 15.57 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:33:22 PM PDT 24
Peak memory 274964 kb
Host smart-48957303-2d61-4c37-9417-058124396d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894747804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1894747804
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.978841420
Short name T197
Test name
Test status
Simulation time 144971000 ps
CPU time 131.84 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:35:18 PM PDT 24
Peak memory 264532 kb
Host smart-fbe306da-7793-460f-9cc0-6dfad8c712d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978841420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot
p_reset.978841420
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.211362998
Short name T1065
Test name
Test status
Simulation time 32324200 ps
CPU time 13.41 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:28:53 PM PDT 24
Peak memory 258180 kb
Host smart-eaaac884-8226-46ad-b4a0-abfafb6afe97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211362998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.211362998
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.1506427817
Short name T677
Test name
Test status
Simulation time 110549500 ps
CPU time 15.83 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:28:57 PM PDT 24
Peak memory 275936 kb
Host smart-5c9eed1b-a10b-416c-9aaf-429ef6bae968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506427817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1506427817
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2572935700
Short name T47
Test name
Test status
Simulation time 13438300 ps
CPU time 22.72 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:03 PM PDT 24
Peak memory 265268 kb
Host smart-eaf72a06-accf-477f-a756-d7234205f7a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572935700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2572935700
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.834340502
Short name T1063
Test name
Test status
Simulation time 9443227200 ps
CPU time 2338.53 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 02:07:23 PM PDT 24
Peak memory 264276 kb
Host smart-604751e3-962b-4465-93a0-63b236941b66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834340502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_erro
r_mp.834340502
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.2971854511
Short name T177
Test name
Test status
Simulation time 1292897700 ps
CPU time 753.64 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:40:58 PM PDT 24
Peak memory 265048 kb
Host smart-a367a198-f8ae-452a-942d-def2f145e52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971854511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2971854511
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.276115252
Short name T51
Test name
Test status
Simulation time 295851000 ps
CPU time 20.91 seconds
Started May 23 01:28:25 PM PDT 24
Finished May 23 01:28:48 PM PDT 24
Peak memory 263140 kb
Host smart-dc595731-a20c-4d65-bfa1-4b7e50718e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276115252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.276115252
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3001593854
Short name T291
Test name
Test status
Simulation time 10023622400 ps
CPU time 71.4 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:52 PM PDT 24
Peak memory 276208 kb
Host smart-5f136743-c8b1-41ad-82dc-b871f55e3101
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001593854 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3001593854
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3572379909
Short name T721
Test name
Test status
Simulation time 17755700 ps
CPU time 13.55 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:28:54 PM PDT 24
Peak memory 265160 kb
Host smart-8401e796-e9bd-4683-ad4b-1b6f3e86ef13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572379909 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3572379909
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1912027599
Short name T820
Test name
Test status
Simulation time 170180828000 ps
CPU time 978.45 seconds
Started May 23 01:28:25 PM PDT 24
Finished May 23 01:44:46 PM PDT 24
Peak memory 261008 kb
Host smart-072a7460-301b-4abf-a6ef-511a0db5ab96
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912027599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1912027599
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.139915314
Short name T540
Test name
Test status
Simulation time 3954885100 ps
CPU time 81.59 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 01:29:45 PM PDT 24
Peak memory 262428 kb
Host smart-18b81ffb-10ad-4094-ba3a-a9d2ee6b2f02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139915314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw
_sec_otp.139915314
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.4023639252
Short name T884
Test name
Test status
Simulation time 2627848800 ps
CPU time 130.17 seconds
Started May 23 01:28:31 PM PDT 24
Finished May 23 01:30:43 PM PDT 24
Peak memory 289828 kb
Host smart-da61c1a6-2097-4659-9b2a-18007d4a609d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023639252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.4023639252
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.2896698445
Short name T28
Test name
Test status
Simulation time 4721449300 ps
CPU time 74.85 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:29:39 PM PDT 24
Peak memory 260172 kb
Host smart-afb023c3-0b86-4472-b767-b5d35bab0731
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896698445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.2896698445
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1114521
Short name T883
Test name
Test status
Simulation time 90082360800 ps
CPU time 277.81 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:33:02 PM PDT 24
Peak memory 265228 kb
Host smart-0570e657-0401-48c2-a96a-69b76e60c9ed
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111
4521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1114521
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2658999052
Short name T872
Test name
Test status
Simulation time 10132469600 ps
CPU time 67.07 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:29:35 PM PDT 24
Peak memory 259372 kb
Host smart-c9d8be8d-4096-45a3-8122-0d1f52298e02
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658999052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2658999052
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2350795212
Short name T901
Test name
Test status
Simulation time 15040000 ps
CPU time 14.19 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:28:54 PM PDT 24
Peak memory 265064 kb
Host smart-9f5db5c4-fd95-43fa-8b3f-12a661e4c50e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350795212 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2350795212
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3306268037
Short name T939
Test name
Test status
Simulation time 8841061800 ps
CPU time 119.02 seconds
Started May 23 01:28:26 PM PDT 24
Finished May 23 01:30:27 PM PDT 24
Peak memory 260696 kb
Host smart-f0bf268f-c40a-4b73-836e-a60abee5176b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306268037 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.3306268037
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.2472223249
Short name T497
Test name
Test status
Simulation time 35693500 ps
CPU time 111.32 seconds
Started May 23 01:28:20 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 259796 kb
Host smart-e50bea5c-3b2b-461d-824e-ed07d4444222
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472223249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.2472223249
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.3250018850
Short name T906
Test name
Test status
Simulation time 71876500 ps
CPU time 319.43 seconds
Started May 23 01:28:25 PM PDT 24
Finished May 23 01:33:47 PM PDT 24
Peak memory 263044 kb
Host smart-6c77c8f4-3268-4252-94d2-b52cf63389c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250018850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3250018850
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.1363811908
Short name T743
Test name
Test status
Simulation time 105853800 ps
CPU time 13.73 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:28:54 PM PDT 24
Peak memory 265116 kb
Host smart-8fd076c7-0a85-4910-a18e-730d4da93118
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363811908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.1363811908
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.531156334
Short name T556
Test name
Test status
Simulation time 6068654200 ps
CPU time 882.29 seconds
Started May 23 01:28:22 PM PDT 24
Finished May 23 01:43:06 PM PDT 24
Peak memory 283704 kb
Host smart-e39e0172-009d-4f90-a233-94a0ea9c87a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531156334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.531156334
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3445803703
Short name T1023
Test name
Test status
Simulation time 53014400 ps
CPU time 33.57 seconds
Started May 23 01:28:42 PM PDT 24
Finished May 23 01:29:17 PM PDT 24
Peak memory 273608 kb
Host smart-5b019b52-44e4-4ef8-bff1-3c20384ee221
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445803703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3445803703
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.2037618314
Short name T532
Test name
Test status
Simulation time 993092800 ps
CPU time 108.25 seconds
Started May 23 01:28:30 PM PDT 24
Finished May 23 01:30:19 PM PDT 24
Peak memory 296964 kb
Host smart-db4f5eb6-4912-4b58-987c-040a83011cfd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037618314 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.2037618314
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2839940481
Short name T429
Test name
Test status
Simulation time 4104779800 ps
CPU time 149.87 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:30:55 PM PDT 24
Peak memory 293460 kb
Host smart-0c799092-c389-4426-a12a-2988e69f5da3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839940481 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2839940481
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.2323385205
Short name T733
Test name
Test status
Simulation time 15165162500 ps
CPU time 531.05 seconds
Started May 23 01:28:24 PM PDT 24
Finished May 23 01:37:17 PM PDT 24
Peak memory 314504 kb
Host smart-b3fcdee8-f6ed-4a7c-a9ba-d376bb1dffd2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323385205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.2323385205
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.1476670229
Short name T892
Test name
Test status
Simulation time 31147300 ps
CPU time 31.37 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 274492 kb
Host smart-7e0e63be-0ab2-4b80-8daa-700a42210533
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476670229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.1476670229
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1584184807
Short name T508
Test name
Test status
Simulation time 140934100 ps
CPU time 31.52 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:12 PM PDT 24
Peak memory 274700 kb
Host smart-abbfb9c9-840d-4cbf-8e87-0ac81532026d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584184807 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1584184807
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1275660253
Short name T220
Test name
Test status
Simulation time 7176055500 ps
CPU time 502.09 seconds
Started May 23 01:28:24 PM PDT 24
Finished May 23 01:36:47 PM PDT 24
Peak memory 311904 kb
Host smart-2a6148b6-1989-434d-bff9-d9e0591358e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275660253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1275660253
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1017448979
Short name T858
Test name
Test status
Simulation time 2380952700 ps
CPU time 73.18 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 262692 kb
Host smart-9c26c176-135f-42d0-b441-d3d8fbbe015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017448979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1017448979
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.517821392
Short name T850
Test name
Test status
Simulation time 47117100 ps
CPU time 73.39 seconds
Started May 23 01:28:19 PM PDT 24
Finished May 23 01:29:34 PM PDT 24
Peak memory 276088 kb
Host smart-41d19368-efca-4eff-b5c4-4581c3179648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517821392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.517821392
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.2992891243
Short name T1025
Test name
Test status
Simulation time 13084084500 ps
CPU time 212.29 seconds
Started May 23 01:28:23 PM PDT 24
Finished May 23 01:31:57 PM PDT 24
Peak memory 265188 kb
Host smart-09944e43-09cc-4701-83a6-3038c137de11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992891243 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.2992891243
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.839421308
Short name T773
Test name
Test status
Simulation time 54016700 ps
CPU time 15.77 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:33:21 PM PDT 24
Peak memory 274832 kb
Host smart-4446cd6f-e5cc-40b1-a5bd-931e74e4a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839421308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.839421308
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3340738436
Short name T554
Test name
Test status
Simulation time 135250900 ps
CPU time 131.43 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:35:17 PM PDT 24
Peak memory 259992 kb
Host smart-fa809c39-d51c-4cba-8148-88de66cb3726
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340738436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3340738436
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.3457196008
Short name T500
Test name
Test status
Simulation time 23377100 ps
CPU time 15.81 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:33:22 PM PDT 24
Peak memory 275740 kb
Host smart-3252414c-389e-4d67-b06d-33babddb4246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457196008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3457196008
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.4236754492
Short name T784
Test name
Test status
Simulation time 111478900 ps
CPU time 130.64 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:35:15 PM PDT 24
Peak memory 261024 kb
Host smart-7c6af928-297e-4f2e-a6ad-b0ec3adc2be8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236754492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.4236754492
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.391630778
Short name T586
Test name
Test status
Simulation time 15718100 ps
CPU time 16.04 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 274812 kb
Host smart-e464303f-391d-4686-906b-1596ea0b9d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391630778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.391630778
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2934306138
Short name T1053
Test name
Test status
Simulation time 37514600 ps
CPU time 132.9 seconds
Started May 23 01:33:06 PM PDT 24
Finished May 23 01:35:21 PM PDT 24
Peak memory 260012 kb
Host smart-c943d058-9e5d-4b7f-a52a-4de01e5cc66b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934306138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2934306138
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3863075529
Short name T459
Test name
Test status
Simulation time 28932400 ps
CPU time 13.37 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:33:18 PM PDT 24
Peak memory 276016 kb
Host smart-01a9b1d0-a459-49d6-a11a-29afe62d4a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863075529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3863075529
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.626086638
Short name T886
Test name
Test status
Simulation time 110313000 ps
CPU time 130.13 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:35:16 PM PDT 24
Peak memory 261048 kb
Host smart-f9a2b803-b0bd-498b-9278-b90c6186d503
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626086638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_ot
p_reset.626086638
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.928534854
Short name T572
Test name
Test status
Simulation time 52044400 ps
CPU time 15.75 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:33:20 PM PDT 24
Peak memory 275640 kb
Host smart-34baa385-444c-4b5c-8f12-6bb4c29a6438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928534854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.928534854
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3674905961
Short name T69
Test name
Test status
Simulation time 87970600 ps
CPU time 132.13 seconds
Started May 23 01:33:06 PM PDT 24
Finished May 23 01:35:21 PM PDT 24
Peak memory 261116 kb
Host smart-7235bb62-efff-4958-8c82-c98ed3ac3a77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674905961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3674905961
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.3672822071
Short name T458
Test name
Test status
Simulation time 41059200 ps
CPU time 15.69 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:33:20 PM PDT 24
Peak memory 275040 kb
Host smart-adac1af5-fe2d-472c-a677-1d90c995b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672822071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3672822071
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2413445457
Short name T975
Test name
Test status
Simulation time 39077800 ps
CPU time 109.72 seconds
Started May 23 01:33:05 PM PDT 24
Finished May 23 01:34:57 PM PDT 24
Peak memory 259720 kb
Host smart-b7a8d506-f87b-4388-81b7-2187e6ce9cce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413445457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2413445457
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3106886430
Short name T804
Test name
Test status
Simulation time 50412000 ps
CPU time 15.9 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:33:22 PM PDT 24
Peak memory 275100 kb
Host smart-04237c3e-6fa4-47be-9328-1dddc6a14d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106886430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3106886430
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3112436807
Short name T797
Test name
Test status
Simulation time 57170400 ps
CPU time 134.29 seconds
Started May 23 01:33:05 PM PDT 24
Finished May 23 01:35:21 PM PDT 24
Peak memory 259864 kb
Host smart-d12a05cc-d65b-454d-9a9c-24a15000838b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112436807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3112436807
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.794707514
Short name T120
Test name
Test status
Simulation time 35143100 ps
CPU time 16.34 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:33:22 PM PDT 24
Peak memory 275588 kb
Host smart-dd62a03a-e7fc-4412-bac4-b84a5ee1cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794707514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.794707514
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3642136050
Short name T1019
Test name
Test status
Simulation time 124167000 ps
CPU time 109.37 seconds
Started May 23 01:33:05 PM PDT 24
Finished May 23 01:34:57 PM PDT 24
Peak memory 260124 kb
Host smart-c941ca3a-34cb-49b8-af77-70049a0453df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642136050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3642136050
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.498432742
Short name T495
Test name
Test status
Simulation time 55003100 ps
CPU time 15.7 seconds
Started May 23 01:33:05 PM PDT 24
Finished May 23 01:33:23 PM PDT 24
Peak memory 275688 kb
Host smart-340213dd-ba66-4157-b9df-59a0ed20a7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498432742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.498432742
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.3463179962
Short name T760
Test name
Test status
Simulation time 279686200 ps
CPU time 130.49 seconds
Started May 23 01:33:04 PM PDT 24
Finished May 23 01:35:17 PM PDT 24
Peak memory 259924 kb
Host smart-6548c74a-845d-4163-859b-e526ddf83491
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463179962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.3463179962
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2578731367
Short name T860
Test name
Test status
Simulation time 27143700 ps
CPU time 15.84 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:33:21 PM PDT 24
Peak memory 275112 kb
Host smart-79164ea7-9fb6-4aae-981e-4dea72c66dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578731367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2578731367
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.3183826316
Short name T634
Test name
Test status
Simulation time 192468300 ps
CPU time 131.17 seconds
Started May 23 01:33:03 PM PDT 24
Finished May 23 01:35:16 PM PDT 24
Peak memory 260000 kb
Host smart-94b26e0e-39c7-436a-bb1c-2805ff0cad49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183826316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.3183826316
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.679085715
Short name T594
Test name
Test status
Simulation time 65776700 ps
CPU time 13.64 seconds
Started May 23 01:28:53 PM PDT 24
Finished May 23 01:29:08 PM PDT 24
Peak memory 265072 kb
Host smart-d3ebaa94-04cb-4a64-a8df-1cfe6489bcc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679085715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.679085715
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.3996269450
Short name T417
Test name
Test status
Simulation time 27300900 ps
CPU time 13.35 seconds
Started May 23 01:28:56 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 275992 kb
Host smart-5fe1c31f-f2d4-420e-801e-900c234446cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996269450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3996269450
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.797591340
Short name T857
Test name
Test status
Simulation time 30570600 ps
CPU time 22.47 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:18 PM PDT 24
Peak memory 273528 kb
Host smart-46ad0a00-699f-4b71-8a1e-95c7ac50f102
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797591340 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.797591340
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.1368984735
Short name T58
Test name
Test status
Simulation time 11858672200 ps
CPU time 2416.34 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 02:08:57 PM PDT 24
Peak memory 264600 kb
Host smart-f7d31799-6d5d-406c-b15c-978060f67367
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368984735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.1368984735
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3544232576
Short name T795
Test name
Test status
Simulation time 294965200 ps
CPU time 727.84 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:40:48 PM PDT 24
Peak memory 273236 kb
Host smart-6e9d15b1-a2ae-4563-90ca-f0dbe943763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544232576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3544232576
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.4149759438
Short name T53
Test name
Test status
Simulation time 574276900 ps
CPU time 29.25 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:09 PM PDT 24
Peak memory 265204 kb
Host smart-fa93055f-f24c-44f5-b0d8-1013a91d24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149759438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.4149759438
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1853210338
Short name T568
Test name
Test status
Simulation time 10036460400 ps
CPU time 59.96 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:56 PM PDT 24
Peak memory 293028 kb
Host smart-5e9e3548-1ac0-4f1e-b3e0-89b7c6feee5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853210338 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1853210338
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3508692183
Short name T170
Test name
Test status
Simulation time 21304500 ps
CPU time 13.1 seconds
Started May 23 01:28:53 PM PDT 24
Finished May 23 01:29:06 PM PDT 24
Peak memory 265196 kb
Host smart-65750992-1985-45f6-be4a-783075bd546a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508692183 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3508692183
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.597010916
Short name T15
Test name
Test status
Simulation time 40129091600 ps
CPU time 859.03 seconds
Started May 23 01:28:40 PM PDT 24
Finished May 23 01:43:01 PM PDT 24
Peak memory 263732 kb
Host smart-10f3726d-2c43-4e12-95d2-e045ac12b9d4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597010916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.597010916
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.3124975390
Short name T421
Test name
Test status
Simulation time 4765418600 ps
CPU time 78.67 seconds
Started May 23 01:28:37 PM PDT 24
Finished May 23 01:29:57 PM PDT 24
Peak memory 262380 kb
Host smart-927d1639-750a-4b11-94da-9da793af7fd3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124975390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.3124975390
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.3272470549
Short name T347
Test name
Test status
Simulation time 7003310400 ps
CPU time 279.62 seconds
Started May 23 01:28:37 PM PDT 24
Finished May 23 01:33:18 PM PDT 24
Peak memory 284092 kb
Host smart-17bc0ae0-8086-4aa6-8922-b32170628563
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272470549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.3272470549
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.24631064
Short name T224
Test name
Test status
Simulation time 24187780300 ps
CPU time 278.83 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:33:19 PM PDT 24
Peak memory 284264 kb
Host smart-b22a7809-ea9c-4baf-ade9-c48f40d10d20
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24631064 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.24631064
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.3627120274
Short name T542
Test name
Test status
Simulation time 8909128200 ps
CPU time 72.92 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:29:52 PM PDT 24
Peak memory 259448 kb
Host smart-04263ba2-ea42-45fb-a899-f9158d196337
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627120274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.3627120274
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.399036841
Short name T95
Test name
Test status
Simulation time 44186231400 ps
CPU time 194.05 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:31:54 PM PDT 24
Peak memory 260308 kb
Host smart-7346aa3b-ca4d-49f9-af05-5196b549b1bd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399
036841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.399036841
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.954578228
Short name T950
Test name
Test status
Simulation time 6531329600 ps
CPU time 74.14 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:55 PM PDT 24
Peak memory 259752 kb
Host smart-98b73a37-5285-4524-b7fc-8d6fe8a2a596
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954578228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.954578228
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2045744995
Short name T292
Test name
Test status
Simulation time 48203400 ps
CPU time 13.37 seconds
Started May 23 01:28:56 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 265084 kb
Host smart-07f34d69-51d6-43dd-ace8-5ef579eb7239
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045744995 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2045744995
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.1031981527
Short name T660
Test name
Test status
Simulation time 37440300 ps
CPU time 108.07 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:30:27 PM PDT 24
Peak memory 264676 kb
Host smart-c89b1fea-2bea-4320-9d75-1b025de9d8cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031981527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.1031981527
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1693807292
Short name T228
Test name
Test status
Simulation time 2706697900 ps
CPU time 131.36 seconds
Started May 23 01:28:41 PM PDT 24
Finished May 23 01:30:54 PM PDT 24
Peak memory 262464 kb
Host smart-ec6f43c0-a35c-49e5-b501-911e81df160e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693807292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1693807292
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.1243581555
Short name T653
Test name
Test status
Simulation time 23126800 ps
CPU time 13.49 seconds
Started May 23 01:28:40 PM PDT 24
Finished May 23 01:28:56 PM PDT 24
Peak memory 258580 kb
Host smart-f6c9b121-4eb3-4376-932e-19c9727e2dc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243581555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.1243581555
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3685115886
Short name T867
Test name
Test status
Simulation time 56176500 ps
CPU time 53.2 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:34 PM PDT 24
Peak memory 265152 kb
Host smart-836574c1-466d-4a92-aed3-f1998f36c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685115886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3685115886
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1160811785
Short name T988
Test name
Test status
Simulation time 314938400 ps
CPU time 36.13 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:29:35 PM PDT 24
Peak memory 274528 kb
Host smart-d340cc64-5e90-4225-a9ea-3a82a1812ed6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160811785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1160811785
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.346809538
Short name T834
Test name
Test status
Simulation time 481732200 ps
CPU time 116.25 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:30:36 PM PDT 24
Peak memory 297116 kb
Host smart-e14b25ab-99e5-418b-894f-2e694d85b609
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346809538 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.346809538
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2454651506
Short name T767
Test name
Test status
Simulation time 598147000 ps
CPU time 138.99 seconds
Started May 23 01:28:38 PM PDT 24
Finished May 23 01:30:59 PM PDT 24
Peak memory 281700 kb
Host smart-5b47de04-048e-4d96-ae00-b1bf6d16d5bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2454651506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2454651506
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.235593296
Short name T1078
Test name
Test status
Simulation time 2977282600 ps
CPU time 147.07 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:31:07 PM PDT 24
Peak memory 281728 kb
Host smart-c6708363-c53b-4bad-9a7b-95d0e1abf7f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235593296 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.235593296
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1756087428
Short name T870
Test name
Test status
Simulation time 8610485400 ps
CPU time 651.79 seconds
Started May 23 01:28:37 PM PDT 24
Finished May 23 01:39:29 PM PDT 24
Peak memory 313588 kb
Host smart-91da7d1c-96b6-4b29-a811-b9d8ae1a2182
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756087428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.1756087428
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.2874729347
Short name T209
Test name
Test status
Simulation time 91324900 ps
CPU time 31.5 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:29:12 PM PDT 24
Peak memory 273516 kb
Host smart-1ddb432a-95dd-4087-b0ab-9cc1affec2f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874729347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.2874729347
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.711828583
Short name T212
Test name
Test status
Simulation time 69374700 ps
CPU time 30.96 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:27 PM PDT 24
Peak memory 276392 kb
Host smart-8239d49b-3def-4cf9-8cb1-5ff6b69a3350
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711828583 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.711828583
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.2852566849
Short name T544
Test name
Test status
Simulation time 3505358000 ps
CPU time 511.04 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:37:12 PM PDT 24
Peak memory 311984 kb
Host smart-1b6f0d56-fe07-45fe-ac2b-b4c12387e208
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852566849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.2852566849
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.968516418
Short name T41
Test name
Test status
Simulation time 167394200 ps
CPU time 215.9 seconds
Started May 23 01:28:41 PM PDT 24
Finished May 23 01:32:18 PM PDT 24
Peak memory 277356 kb
Host smart-b2fb17fa-c719-4d6f-975d-41a3496d8f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968516418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.968516418
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3315025489
Short name T681
Test name
Test status
Simulation time 1615370600 ps
CPU time 137.52 seconds
Started May 23 01:28:39 PM PDT 24
Finished May 23 01:30:58 PM PDT 24
Peak memory 264756 kb
Host smart-66a4854c-5897-4557-aa08-72611fb2de25
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315025489 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.3315025489
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.3308260736
Short name T842
Test name
Test status
Simulation time 113279300 ps
CPU time 14.21 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:29:23 PM PDT 24
Peak memory 265204 kb
Host smart-fbfe4bf6-f41b-40cf-9524-d4ea524feb8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308260736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3
308260736
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.3026265851
Short name T504
Test name
Test status
Simulation time 34898300 ps
CPU time 15.65 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:29:26 PM PDT 24
Peak memory 276020 kb
Host smart-13bf2e36-553f-4112-8d79-feefe4968bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026265851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3026265851
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.1894209316
Short name T368
Test name
Test status
Simulation time 25556800 ps
CPU time 21.85 seconds
Started May 23 01:29:12 PM PDT 24
Finished May 23 01:29:35 PM PDT 24
Peak memory 265332 kb
Host smart-afda301b-a483-417d-b470-c165fa5493a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894209316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.1894209316
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1089948145
Short name T227
Test name
Test status
Simulation time 8885535600 ps
CPU time 2198.85 seconds
Started May 23 01:28:53 PM PDT 24
Finished May 23 02:05:33 PM PDT 24
Peak memory 263916 kb
Host smart-929aa1c8-207d-49bf-bba6-202624a3af96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089948145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.1089948145
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.4182995858
Short name T484
Test name
Test status
Simulation time 560294600 ps
CPU time 775.22 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:41:50 PM PDT 24
Peak memory 273288 kb
Host smart-a99647ac-b93d-4b3f-b627-be910e5de8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182995858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.4182995858
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.798463415
Short name T52
Test name
Test status
Simulation time 421445800 ps
CPU time 23 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:19 PM PDT 24
Peak memory 265204 kb
Host smart-02f5c4cc-1e9f-4b50-b37f-a7208fac8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798463415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.798463415
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2603396671
Short name T140
Test name
Test status
Simulation time 10032733400 ps
CPU time 54.83 seconds
Started May 23 01:29:09 PM PDT 24
Finished May 23 01:30:05 PM PDT 24
Peak memory 282700 kb
Host smart-1a2d422f-ad4a-42d9-9274-568f971b6bba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603396671 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2603396671
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.580854264
Short name T922
Test name
Test status
Simulation time 25961100 ps
CPU time 13.78 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:29:21 PM PDT 24
Peak memory 265304 kb
Host smart-efccb8f1-af08-49f1-a404-a6f33f602f44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580854264 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.580854264
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2166162381
Short name T121
Test name
Test status
Simulation time 80152972600 ps
CPU time 772.01 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:41:49 PM PDT 24
Peak memory 264412 kb
Host smart-e07a8e18-1706-4802-9be8-a7b6a2335c15
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166162381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2166162381
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.411607565
Short name T320
Test name
Test status
Simulation time 25112425900 ps
CPU time 197.68 seconds
Started May 23 01:28:53 PM PDT 24
Finished May 23 01:32:12 PM PDT 24
Peak memory 262540 kb
Host smart-a6aa3cfb-76d7-4aee-8a18-8535aedc57f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411607565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.411607565
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.701608875
Short name T97
Test name
Test status
Simulation time 18439588900 ps
CPU time 161.34 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:31:37 PM PDT 24
Peak memory 260252 kb
Host smart-eb6a636d-fd92-46de-9671-2f4a94b52e0b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701
608875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.701608875
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1449622657
Short name T193
Test name
Test status
Simulation time 982916200 ps
CPU time 94.64 seconds
Started May 23 01:28:52 PM PDT 24
Finished May 23 01:30:28 PM PDT 24
Peak memory 259620 kb
Host smart-f3b4c745-42f9-4069-9b46-13fb0f42988c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449622657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1449622657
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1342697370
Short name T130
Test name
Test status
Simulation time 81882200 ps
CPU time 13.54 seconds
Started May 23 01:29:08 PM PDT 24
Finished May 23 01:29:22 PM PDT 24
Peak memory 259640 kb
Host smart-d0a83669-02b0-4873-88aa-3681064fc2f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342697370 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1342697370
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3246165405
Short name T749
Test name
Test status
Simulation time 116742400 ps
CPU time 129.5 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:31:06 PM PDT 24
Peak memory 264480 kb
Host smart-22a6d823-8b0c-46cc-b766-85ddee015e4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246165405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3246165405
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3814986446
Short name T913
Test name
Test status
Simulation time 2854590800 ps
CPU time 339.17 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:34:36 PM PDT 24
Peak memory 265240 kb
Host smart-8d83c770-dbd0-4ecc-af47-3cd659c726a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814986446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3814986446
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3864270767
Short name T853
Test name
Test status
Simulation time 13966266500 ps
CPU time 201.52 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:32:19 PM PDT 24
Peak memory 259732 kb
Host smart-052d7fdd-b797-4bdd-a294-b293bbd071c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864270767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3864270767
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3121989334
Short name T116
Test name
Test status
Simulation time 9382401700 ps
CPU time 913.79 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:44:12 PM PDT 24
Peak memory 284004 kb
Host smart-b51ae04a-3782-40e1-bed9-ebe029322c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121989334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3121989334
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.121529887
Short name T325
Test name
Test status
Simulation time 117762800 ps
CPU time 37.61 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:29:34 PM PDT 24
Peak memory 273364 kb
Host smart-210e8132-3196-4dfb-8f40-0860fc6c1a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121529887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.121529887
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3563437275
Short name T577
Test name
Test status
Simulation time 635961100 ps
CPU time 122.39 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:30:57 PM PDT 24
Peak memory 281636 kb
Host smart-8ec500f1-5b02-4a51-89f0-0ae82d8d30cc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563437275 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3563437275
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3179733490
Short name T907
Test name
Test status
Simulation time 502915800 ps
CPU time 116.55 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:30:55 PM PDT 24
Peak memory 281672 kb
Host smart-d06df33f-139e-446d-ab4c-d2f41110594c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3179733490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3179733490
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1818884705
Short name T998
Test name
Test status
Simulation time 2582049500 ps
CPU time 135.54 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:31:14 PM PDT 24
Peak memory 281656 kb
Host smart-51cf9d19-38e6-432c-b022-0d3cb8341fe7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818884705 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1818884705
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3788668999
Short name T1096
Test name
Test status
Simulation time 7808764400 ps
CPU time 636.6 seconds
Started May 23 01:28:54 PM PDT 24
Finished May 23 01:39:32 PM PDT 24
Peak memory 313688 kb
Host smart-03e2c3d9-276c-41ff-b376-de272b12d79e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788668999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.3788668999
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.4070954232
Short name T217
Test name
Test status
Simulation time 28114121000 ps
CPU time 710.17 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:40:49 PM PDT 24
Peak memory 347072 kb
Host smart-6165108a-5048-4b29-94c1-81285f8a7343
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070954232 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.4070954232
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.3760760843
Short name T632
Test name
Test status
Simulation time 145492100 ps
CPU time 32.32 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:29:31 PM PDT 24
Peak memory 272492 kb
Host smart-840dc57c-cabb-40a7-ac19-1652e416ca85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760760843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.3760760843
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2567441858
Short name T984
Test name
Test status
Simulation time 800504100 ps
CPU time 76.83 seconds
Started May 23 01:29:07 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 263212 kb
Host smart-0e3f04c9-8a2a-4db1-88bd-9a696cbe55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567441858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2567441858
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.709389756
Short name T930
Test name
Test status
Simulation time 66548400 ps
CPU time 75.63 seconds
Started May 23 01:28:55 PM PDT 24
Finished May 23 01:30:12 PM PDT 24
Peak memory 276072 kb
Host smart-8059879f-0c57-490c-9d82-d655384313de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709389756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.709389756
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.781525528
Short name T859
Test name
Test status
Simulation time 9852956000 ps
CPU time 221.52 seconds
Started May 23 01:28:57 PM PDT 24
Finished May 23 01:32:40 PM PDT 24
Peak memory 260244 kb
Host smart-542c6633-01ee-42d5-931e-c70fbc35c516
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781525528 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_wo.781525528
Directory /workspace/9.flash_ctrl_wo/latest
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