Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	456217	1		T1	1		T2	1		T3	1
all_values[1]	456217	1		T1	1		T2	1		T3	1
all_values[2]	456217	1		T1	1		T2	1		T3	1
all_values[3]	456217	1		T1	1		T2	1		T3	1
all_values[4]	456217	1		T1	1		T2	1		T3	1
all_values[5]	456217	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	918596	1		T1	6		T2	6		T3	6
auto[1]	1818706	1		T33	6136		T42	53824		T34	6560

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1338129	1		T1	4		T2	4		T3	4
auto[1]	1399173	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	456045	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	172	1		T274	1		T275	5		T276	6
all_values[1]	auto[0]	auto[1]	456053	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	164	1		T274	4		T275	6		T276	3
all_values[2]	auto[0]	auto[0]	1563	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	68	1		T275	2		T342	2		T343	4
all_values[2]	auto[1]	auto[0]	454539	1		T33	1534		T42	13456		T34	1640
all_values[2]	auto[1]	auto[1]	47	1		T274	1		T275	1		T276	2
all_values[3]	auto[0]	auto[0]	1569	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	56	1		T275	3		T342	1		T343	1
all_values[3]	auto[1]	auto[0]	73392	1		T33	1534		T42	392		T34	1640
all_values[3]	auto[1]	auto[1]	381200	1		T42	13064		T43	1734		T44	5310
all_values[4]	auto[0]	auto[0]	1101	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	508	1		T4	1		T7	1		T8	1
all_values[4]	auto[1]	auto[0]	349944	1		T33	1		T42	11823		T34	1
all_values[4]	auto[1]	auto[1]	104664	1		T33	1533		T42	1633		T34	1639
all_values[5]	auto[0]	auto[0]	1505	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	128	1		T7	1		T23	1		T9	4
all_values[5]	auto[1]	auto[0]	454516	1		T33	1534		T42	13456		T34	1640
all_values[5]	auto[1]	auto[1]	68	1		T274	1		T275	2		T276	4