Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246175	1		T1	1028		T3	5		T4	600
auto[FlashEraseBank]	273125	1		T3	6		T7	498		T8	600

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	260084	1		T1	512		T3	10		T4	200
auto[FlashOpProgram]	240134	1		T1	258		T3	1		T4	100
auto[FlashOpErase]	15082	1		T1	258		T4	100		T14	1
auto[FlashOpInvalid]	4000	1		T4	200		T107	200		T97	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	260084	1		T1	512		T3	10		T4	200
op[FlashOpProgram]	240134	1		T1	258		T3	1		T4	100
op[FlashOpErase]	15082	1		T1	258		T4	100		T14	1
read_erase_read	625	1		T20	18		T31	20		T36	1
read_prog_read	807	1		T8	2		T32	3		T48	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	384891	1		T3	4		T4	588		T7	905
auto[FlashPartInfo]	131201	1		T1	1028		T3	7		T4	12
auto[FlashPartInfo1]	742	1		T7	1		T8	1		T65	2
auto[FlashPartInfo2]	2466	1		T7	6		T8	6		T20	17

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	192398	1		T3	3		T4	196		T7	905
auto[FlashPartData]	auto[FlashOpProgram]	184775	1		T3	1		T4	98		T8	598
auto[FlashPartData]	auto[FlashOpErase]	3806	1		T4	98		T20	15		T31	15
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T4	196		T107	196		T97	194
auto[FlashPartInfo]	auto[FlashOpRead]	65659	1		T1	512		T3	7		T4	4
auto[FlashPartInfo]	auto[FlashOpProgram]	54273	1		T1	258		T4	2		T8	74
auto[FlashPartInfo]	auto[FlashOpErase]	11195	1		T1	258		T4	2		T14	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T4	4		T107	2		T97	4
auto[FlashPartInfo1]	auto[FlashOpRead]	569	1		T7	1		T8	1		T65	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T81	1		T93	1		T98	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T81	1		T93	1		T113	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T81	2		T93	2		T113	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1458	1		T7	6		T8	4		T20	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	923	1		T8	2		T23	7		T62	1
auto[FlashPartInfo2]	auto[FlashOpErase]	77	1		T20	8		T107	1		T97	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T107	2		T97	2		T423	2