Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	10	22	68.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	10	22	68.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29034	1		T1	516		T4	400		T37	4
auto[1]	11	1		T184	2		T301	1		T300	1
auto[2]	16	1		T29	4		T330	1		T331	4
auto[3]	107	1		T20	3		T31	7		T5	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7293	1		T1	129		T4	100		T20	1
evic_idx[1]	7290	1		T1	129		T4	100		T31	1
evic_idx[2]	7290	1		T1	129		T4	100		T31	2
evic_idx[3]	7295	1		T1	129		T4	100		T20	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28320	1		T1	516		T4	400		T20	3
evic_op[2]	280	1		T5	1		T62	1		T184	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	10	22	68.75	10

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4
[evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4
[evic_idx[2] , evic_idx[3]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7064	1		T1	129		T4	100		T37	1
evic_idx[0]	evic_op[1]	auto[3]	16	1		T20	1		T31	2		T143	1
evic_idx[0]	evic_op[2]	auto[0]	55	1		T121	1		T123	7		T293	4
evic_idx[0]	evic_op[2]	auto[1]	3	1		T332	1		T333	1		T334	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T335	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	12	1		T62	1		T45	1		T336	1
evic_idx[1]	evic_op[1]	auto[0]	7065	1		T1	129		T4	100		T37	1
evic_idx[1]	evic_op[1]	auto[3]	13	1		T31	1		T143	1		T302	1
evic_idx[1]	evic_op[2]	auto[0]	56	1		T123	7		T214	1		T293	4
evic_idx[1]	evic_op[2]	auto[1]	3	1		T332	1		T337	1		T334	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T330	1		T335	1		T338	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T45	1		T336	1		T339	1
evic_idx[2]	evic_op[1]	auto[0]	7064	1		T1	129		T4	100		T37	1
evic_idx[2]	evic_op[1]	auto[3]	16	1		T31	2		T143	1		T302	1
evic_idx[2]	evic_op[2]	auto[0]	54	1		T185	1		T123	7		T293	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T184	1		T301	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T45	1		T340	1		T336	1
evic_idx[3]	evic_op[1]	auto[0]	7065	1		T1	129		T4	100		T37	1
evic_idx[3]	evic_op[1]	auto[3]	17	1		T20	2		T31	2		T143	1
evic_idx[3]	evic_op[2]	auto[0]	55	1		T28	1		T123	7		T293	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T184	1		T300	1		T341	1
evic_idx[3]	evic_op[2]	auto[3]	13	1		T5	1		T45	1		T340	1