Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	78961	1		T350	14312		T351	1456		T352	15052
rd_lvl[2]	98081	1		T42	12280		T353	2638		T350	9864
rd_lvl[3]	9598	1		T42	392		T353	2136		T351	284
rd_lvl[4]	34831	1		T354	6097		T353	1146		T351	470
rd_lvl[5]	13041	1		T44	2491		T354	914		T353	1823
rd_lvl[6]	10658	1		T44	1321		T353	2928		T355	1303
rd_lvl[7]	7111	1		T356	1846		T299	287		T357	189
rd_lvl[8]	17266	1		T77	3072		T39	140		T356	1522
rd_lvl[9]	7616	1		T43	553		T77	358		T39	17
rd_lvl[10]	8665	1		T43	1181		T119	217		T358	1314
rd_lvl[11]	3905	1		T39	1		T358	496		T295	624
rd_lvl[12]	4990	1		T359	1022		T351	4		T360	100
rd_lvl[13]	1897	1		T40	194		T361	381		T351	1
rd_lvl[14]	6208	1		T328	1133		T40	1432		T361	181
rd_lvl[15]	1202	1		T328	452		T41	508		T362	242