Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	456217	1		T1	1		T2	1		T3	1
all_pins[1]	456217	1		T1	1		T2	1		T3	1
all_pins[2]	456217	1		T1	1		T2	1		T3	1
all_pins[3]	456217	1		T1	1		T2	1		T3	1
all_pins[4]	456217	1		T1	1		T2	1		T3	1
all_pins[5]	456217	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2317259	1		T1	6		T2	6		T3	6
values[0x1]	420043	1		T33	1533		T42	14305		T34	1639
transitions[0x0=>0x1]	379135	1		T33	1533		T42	13064		T34	1639
transitions[0x1=>0x0]	379112	1		T33	1533		T42	13064		T34	1639

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	456045	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	172	1		T274	1		T275	5		T276	6
all_pins[0]	transitions[0x0=>0x1]	75	1		T275	2		T276	4		T342	3
all_pins[0]	transitions[0x1=>0x0]	67	1		T274	3		T275	3		T276	1
all_pins[1]	values[0x0]	456053	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	164	1		T274	4		T275	6		T276	3
all_pins[1]	transitions[0x0=>0x1]	137	1		T274	3		T275	5		T276	2
all_pins[1]	transitions[0x1=>0x0]	1146	1		T41	1122		T362	4		T276	1
all_pins[2]	values[0x0]	455044	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	1173	1		T41	1122		T362	4		T274	1
all_pins[2]	transitions[0x0=>0x1]	36	1		T274	1		T275	1		T276	1
all_pins[2]	transitions[0x1=>0x0]	304081	1		T42	12672		T43	1734		T44	3812
all_pins[3]	values[0x0]	150999	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	305218	1		T42	12672		T43	1734		T44	3812
all_pins[3]	transitions[0x0=>0x1]	265624	1		T42	11431		T43	1734		T44	3718
all_pins[3]	transitions[0x1=>0x0]	73654	1		T33	1533		T42	392		T34	1639
all_pins[4]	values[0x0]	342969	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	113248	1		T33	1533		T42	1633		T34	1639
all_pins[4]	transitions[0x0=>0x1]	113226	1		T33	1533		T42	1633		T34	1639
all_pins[4]	transitions[0x1=>0x0]	46	1		T275	2		T276	4		T342	2
all_pins[5]	values[0x0]	456149	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	68	1		T274	1		T275	2		T276	4
all_pins[5]	transitions[0x0=>0x1]	37	1		T276	2		T342	1		T347	1
all_pins[5]	transitions[0x1=>0x0]	118	1		T275	3		T276	3		T342	2