Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T274 4 T275 7 T276 7
all_values[1] 281 1 T274 4 T275 7 T276 7
all_values[2] 281 1 T274 4 T275 7 T276 7
all_values[3] 281 1 T274 4 T275 7 T276 7
all_values[4] 281 1 T274 4 T275 7 T276 7
all_values[5] 281 1 T274 4 T275 7 T276 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 909 1 T274 13 T275 25 T276 22
auto[1] 777 1 T274 11 T275 17 T276 20



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 552 1 T274 12 T275 9 T276 10
auto[1] 1134 1 T274 12 T275 33 T276 32



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 988 1 T274 20 T275 22 T276 24
auto[1] 698 1 T274 4 T275 20 T276 18



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 75 1 T274 4 T275 1 T276 2
all_values[0] auto[0] auto[1] auto[1] 89 1 T275 3 T276 2 T342 2
all_values[0] auto[1] auto[0] auto[1] 70 1 T275 1 T276 2 T342 1
all_values[0] auto[1] auto[1] auto[1] 47 1 T275 2 T276 1 T342 3
all_values[1] auto[0] auto[0] auto[1] 77 1 T274 1 T275 1 T276 1
all_values[1] auto[0] auto[1] auto[1] 86 1 T274 3 T275 3 T276 2
all_values[1] auto[1] auto[0] auto[1] 70 1 T275 3 T276 2 T342 2
all_values[1] auto[1] auto[1] auto[1] 48 1 T276 2 T343 2 T344 1
all_values[2] auto[0] auto[0] auto[0] 90 1 T274 2 T275 2 T276 3
all_values[2] auto[0] auto[1] auto[0] 76 1 T274 1 T275 2 T276 2
all_values[2] auto[1] auto[0] auto[1] 76 1 T274 1 T275 3 T276 2
all_values[2] auto[1] auto[1] auto[1] 39 1 T342 1 T345 1 T346 2
all_values[3] auto[0] auto[0] auto[0] 89 1 T274 1 T275 2 T276 2
all_values[3] auto[0] auto[1] auto[0] 74 1 T274 2 T275 1 T276 2
all_values[3] auto[1] auto[0] auto[1] 64 1 T275 3 T276 1 T342 1
all_values[3] auto[1] auto[1] auto[1] 54 1 T274 1 T275 1 T276 2
all_values[4] auto[0] auto[0] auto[0] 61 1 T274 1 T276 1 T342 2
all_values[4] auto[0] auto[0] auto[1] 20 1 T276 2 T343 1 T345 1
all_values[4] auto[0] auto[1] auto[0] 43 1 T274 2 T275 1 T342 1
all_values[4] auto[0] auto[1] auto[1] 34 1 T275 3 T276 1 T342 2
all_values[4] auto[1] auto[0] auto[1] 63 1 T275 3 T342 1 T343 1
all_values[4] auto[1] auto[1] auto[1] 60 1 T274 1 T276 3 T342 1
all_values[5] auto[0] auto[0] auto[0] 71 1 T274 3 T275 1 T342 1
all_values[5] auto[0] auto[0] auto[1] 30 1 T275 2 T276 1 T345 1
all_values[5] auto[0] auto[1] auto[0] 48 1 T342 1 T343 1 T344 2
all_values[5] auto[0] auto[1] auto[1] 25 1 T276 3 T342 1 T347 1
all_values[5] auto[1] auto[0] auto[1] 53 1 T275 3 T276 3 T342 1
all_values[5] auto[1] auto[1] auto[1] 54 1 T274 1 T275 1 T342 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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