Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	463633	1		T1	1		T2	1		T3	1
all_values[1]	463633	1		T1	1		T2	1		T3	1
all_values[2]	463633	1		T1	1		T2	1		T3	1
all_values[3]	463633	1		T1	1		T2	1		T3	1
all_values[4]	463633	1		T1	1		T2	1		T3	1
all_values[5]	463633	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	933473	1		T1	6		T2	6		T3	6
auto[1]	1848325	1		T23	6040		T34	1260		T35	12664

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1364584	1		T1	4		T2	4		T3	4
auto[1]	1417214	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	463453	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	180	1		T255	1		T256	2		T257	5
all_values[1]	auto[0]	auto[1]	463475	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	158	1		T255	1		T256	3		T257	3
all_values[2]	auto[0]	auto[0]	1575	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	57	1		T255	1		T256	1		T257	1
all_values[2]	auto[1]	auto[0]	461942	1		T23	1510		T34	315		T35	3166
all_values[2]	auto[1]	auto[1]	59	1		T255	1		T257	2		T310	1
all_values[3]	auto[0]	auto[0]	1591	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	55	1		T255	1		T256	1		T257	1
all_values[3]	auto[1]	auto[0]	87586	1		T23	1510		T34	78		T35	1583
all_values[3]	auto[1]	auto[1]	374401	1		T34	237		T35	1583		T36	3512
all_values[4]	auto[0]	auto[0]	1106	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	518	1		T4	1		T6	1		T7	1
all_values[4]	auto[1]	auto[0]	347326	1		T23	1		T34	236		T35	1583
all_values[4]	auto[1]	auto[1]	114683	1		T23	1509		T34	79		T35	1583
all_values[5]	auto[0]	auto[0]	1519	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	124	1		T4	1		T37	1		T38	1
all_values[5]	auto[1]	auto[0]	461939	1		T23	1510		T34	315		T35	3166
all_values[5]	auto[1]	auto[1]	51	1		T257	3		T311	3		T314	1