Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	236076	1		T2	58		T4	1622		T5	1
auto[FlashEraseBank]	272352	1		T2	15		T4	1763		T9	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263762	1		T2	42		T4	1100		T6	1
auto[FlashOpProgram]	226024	1		T4	2285		T5	1		T6	3
auto[FlashOpErase]	14642	1		T2	31		T7	12		T20	119
auto[FlashOpInvalid]	4000	1		T78	200		T107	200		T286	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263762	1		T2	42		T4	1100		T6	1
op[FlashOpProgram]	226024	1		T4	2285		T5	1		T6	3
op[FlashOpErase]	14642	1		T2	31		T7	12		T20	119
read_erase_read	714	1		T2	31		T7	3		T29	1
read_prog_read	734	1		T4	6		T37	11		T38	9

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	376882	1		T2	1		T4	2938		T5	1
auto[FlashPartInfo]	128134	1		T2	71		T4	418		T7	278
auto[FlashPartInfo1]	839	1		T4	1		T8	2		T37	1
auto[FlashPartInfo2]	2573	1		T2	1		T4	28		T23	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	196797	1		T2	1		T4	796		T6	1
auto[FlashPartData]	auto[FlashOpProgram]	172394	1		T4	2142		T5	1		T6	3
auto[FlashPartData]	auto[FlashOpErase]	3755	1		T99	1		T56	9		T65	30
auto[FlashPartData]	auto[FlashOpInvalid]	3936	1		T78	200		T107	194		T286	198
auto[FlashPartInfo]	auto[FlashOpRead]	64665	1		T2	40		T4	282		T7	10
auto[FlashPartInfo]	auto[FlashOpProgram]	52580	1		T4	136		T7	256		T20	119
auto[FlashPartInfo]	auto[FlashOpErase]	10835	1		T2	31		T7	12		T20	119
auto[FlashPartInfo]	auto[FlashOpInvalid]	54	1		T107	4		T286	2		T82	2
auto[FlashPartInfo1]	auto[FlashOpRead]	671	1		T4	1		T8	2		T37	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T80	1		T57	32		T82	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T82	1		T393	1		T394	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T82	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1629	1		T2	1		T4	21		T8	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	887	1		T4	7		T23	4		T37	6
auto[FlashPartInfo2]	auto[FlashOpErase]	49	1		T103	1		T104	1		T107	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T107	2		T82	2		T395	2