Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28007	1		T20	228		T30	4		T75	484
auto[1]	16	1		T92	4		T269	4		T323	2
auto[2]	26	1		T65	4		T156	4		T204	1
auto[3]	71	1		T26	1		T301	2		T106	4

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7027	1		T20	57		T30	1		T75	121
evic_idx[1]	7033	1		T20	57		T30	1		T75	121
evic_idx[2]	7030	1		T20	57		T30	1		T75	121
evic_idx[3]	7030	1		T20	57		T30	1		T75	121

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27206	1		T20	228		T75	484		T44	380
evic_op[2]	326	1		T30	4		T151	4		T26	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1] , evic_idx[2]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6796	1		T20	57		T75	121		T44	95
evic_idx[0]	evic_op[1]	auto[1]	1	1		T269	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	1	1		T324	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	1	1		T106	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[0]	63	1		T30	1		T151	1		T325	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T92	1		T326	1		T327	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T328	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	14	1		T301	1		T207	1		T329	1
evic_idx[1]	evic_op[1]	auto[0]	6798	1		T20	57		T75	121		T44	95
evic_idx[1]	evic_op[1]	auto[1]	1	1		T269	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	1	1		T324	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	4	1		T106	1		T330	2		T331	1
evic_idx[1]	evic_op[2]	auto[0]	64	1		T30	1		T151	1		T192	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T92	1		T323	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	16	1		T209	1		T332	1		T333	1
evic_idx[2]	evic_op[1]	auto[0]	6796	1		T20	57		T75	121		T44	95
evic_idx[2]	evic_op[1]	auto[1]	1	1		T269	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T324	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	4	1		T106	1		T330	2		T331	1
evic_idx[2]	evic_op[2]	auto[0]	62	1		T30	1		T151	1		T152	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T92	1		T323	1		T326	1
evic_idx[2]	evic_op[2]	auto[3]	15	1		T26	1		T334	1		T105	1
evic_idx[3]	evic_op[1]	auto[0]	6796	1		T20	57		T75	121		T44	95
evic_idx[3]	evic_op[1]	auto[1]	1	1		T269	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T324	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	3	1		T106	1		T330	2		-	-
evic_idx[3]	evic_op[2]	auto[0]	64	1		T30	1		T151	1		T325	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T92	1		T335	1		T326	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T204	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T301	1		T334	1		T336	1