Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	57280	1		T198	1357		T316	15870		T317	2525
rd_lvl[2]	87204	1		T198	2145		T297	1467		T316	11409
rd_lvl[3]	14432	1		T198	408		T297	636		T316	1
rd_lvl[4]	33693	1		T198	1693		T297	197		T114	1104
rd_lvl[5]	26808	1		T34	177		T198	125		T297	293
rd_lvl[6]	31908	1		T34	60		T36	2590		T198	1498
rd_lvl[7]	15338	1		T36	922		T198	56		T297	60
rd_lvl[8]	10993	1		T198	409		T297	50		T114	45
rd_lvl[9]	7794	1		T198	1116		T297	47		T317	1780
rd_lvl[10]	6850	1		T35	1246		T317	1042		T318	1
rd_lvl[11]	6507	1		T35	337		T198	2856		T318	17
rd_lvl[12]	7816	1		T297	88		T114	162		T31	795
rd_lvl[13]	1974	1		T297	84		T31	92		T32	453
rd_lvl[14]	5560	1		T32	1119		T318	17		T307	250
rd_lvl[15]	2117	1		T31	109		T307	104		T319	458