Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	463633	1		T1	1		T2	1		T3	1
all_pins[1]	463633	1		T1	1		T2	1		T3	1
all_pins[2]	463633	1		T1	1		T2	1		T3	1
all_pins[3]	463633	1		T1	1		T2	1		T3	1
all_pins[4]	463633	1		T1	1		T2	1		T3	1
all_pins[5]	463633	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2330744	1		T1	6		T2	6		T3	6
values[0x1]	451054	1		T23	1509		T34	337		T35	3166
transitions[0x0=>0x1]	407618	1		T23	1509		T34	315		T35	3166
transitions[0x1=>0x0]	407594	1		T23	1509		T34	315		T35	3166

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	463453	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	180	1		T255	1		T256	2		T257	5
all_pins[0]	transitions[0x0=>0x1]	81	1		T255	1		T257	4		T310	5
all_pins[0]	transitions[0x1=>0x0]	59	1		T255	1		T256	1		T257	2
all_pins[1]	values[0x0]	463475	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	158	1		T255	1		T256	3		T257	3
all_pins[1]	transitions[0x0=>0x1]	125	1		T256	3		T257	2		T310	2
all_pins[1]	transitions[0x1=>0x0]	3292	1		T307	180		T337	4		T338	998
all_pins[2]	values[0x0]	460308	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	3325	1		T307	180		T337	4		T338	998
all_pins[2]	transitions[0x0=>0x1]	48	1		T257	2		T310	1		T312	2
all_pins[2]	transitions[0x1=>0x0]	316314	1		T34	237		T35	1583		T36	3512
all_pins[3]	values[0x0]	144042	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	319591	1		T34	237		T35	1583		T36	3512
all_pins[3]	transitions[0x0=>0x1]	279610	1		T34	215		T35	1583		T36	3512
all_pins[3]	transitions[0x1=>0x0]	87768	1		T23	1509		T34	78		T35	1583
all_pins[4]	values[0x0]	335884	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	127749	1		T23	1509		T34	100		T35	1583
all_pins[4]	transitions[0x0=>0x1]	127734	1		T23	1509		T34	100		T35	1583
all_pins[4]	transitions[0x1=>0x0]	36	1		T257	2		T311	3		T314	1
all_pins[5]	values[0x0]	463582	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	51	1		T257	3		T311	3		T314	1
all_pins[5]	transitions[0x0=>0x1]	20	1		T257	2		T311	1		T314	1
all_pins[5]	transitions[0x1=>0x0]	125	1		T255	1		T256	1		T257	3