Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 263 1 T255 4 T256 4 T257 7
all_values[1] 263 1 T255 4 T256 4 T257 7
all_values[2] 263 1 T255 4 T256 4 T257 7
all_values[3] 263 1 T255 4 T256 4 T257 7
all_values[4] 263 1 T255 4 T256 4 T257 7
all_values[5] 263 1 T255 4 T256 4 T257 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 828 1 T255 11 T256 17 T257 23
auto[1] 750 1 T255 13 T256 7 T257 19



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 516 1 T255 9 T256 10 T257 13
auto[1] 1062 1 T255 15 T256 14 T257 29



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 934 1 T255 14 T256 17 T257 25
auto[1] 644 1 T255 10 T256 7 T257 17



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 79 1 T255 1 T256 2 T257 2
all_values[0] auto[0] auto[1] auto[1] 87 1 T255 1 T256 1 T257 3
all_values[0] auto[1] auto[0] auto[1] 47 1 T255 2 T256 1 T257 1
all_values[0] auto[1] auto[1] auto[1] 50 1 T257 1 T310 4 T311 1
all_values[1] auto[0] auto[0] auto[1] 74 1 T255 1 T257 1 T310 3
all_values[1] auto[0] auto[1] auto[1] 79 1 T255 1 T256 3 T257 2
all_values[1] auto[1] auto[0] auto[1] 68 1 T255 2 T256 1 T257 4
all_values[1] auto[1] auto[1] auto[1] 42 1 T310 2 T312 2 T311 1
all_values[2] auto[0] auto[0] auto[0] 76 1 T255 2 T256 2 T257 2
all_values[2] auto[0] auto[1] auto[0] 71 1 T256 1 T257 2 T310 1
all_values[2] auto[1] auto[0] auto[1] 64 1 T255 1 T256 1 T257 1
all_values[2] auto[1] auto[1] auto[1] 52 1 T255 1 T257 2 T312 3
all_values[3] auto[0] auto[0] auto[0] 93 1 T256 3 T257 3 T310 2
all_values[3] auto[0] auto[1] auto[0] 65 1 T255 2 T257 2 T310 1
all_values[3] auto[1] auto[0] auto[1] 54 1 T255 1 T256 1 T257 2
all_values[3] auto[1] auto[1] auto[1] 51 1 T255 1 T310 2 T312 1
all_values[4] auto[0] auto[0] auto[0] 44 1 T256 2 T257 2 T310 1
all_values[4] auto[0] auto[0] auto[1] 23 1 T257 1 T312 1 T313 1
all_values[4] auto[0] auto[1] auto[0] 45 1 T255 2 T257 2 T310 1
all_values[4] auto[0] auto[1] auto[1] 33 1 T255 1 T256 1 T310 4
all_values[4] auto[1] auto[0] auto[1] 60 1 T312 2 T314 2 T313 4
all_values[4] auto[1] auto[1] auto[1] 58 1 T255 1 T256 1 T257 2
all_values[5] auto[0] auto[0] auto[0] 66 1 T256 2 T310 4 T312 3
all_values[5] auto[0] auto[0] auto[1] 24 1 T257 3 T312 1 T315 3
all_values[5] auto[0] auto[1] auto[0] 56 1 T255 3 T310 1 T312 1
all_values[5] auto[0] auto[1] auto[1] 19 1 T311 1 T313 1 T315 1
all_values[5] auto[1] auto[0] auto[1] 56 1 T255 1 T256 2 T257 1
all_values[5] auto[1] auto[1] auto[1] 42 1 T257 3 T311 2 T314 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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