Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	264334	1		T1	1		T2	1		T13	1
all_values[1]	264334	1		T1	1		T2	1		T13	1
all_values[2]	264334	1		T1	1		T2	1		T13	1
all_values[3]	264334	1		T1	1		T2	1		T13	1
all_values[4]	264334	1		T1	1		T2	1		T13	1
all_values[5]	264334	1		T1	1		T2	1		T13	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	534880	1		T1	6		T2	6		T13	6
auto[1]	1051124	1		T39	19788		T40	38904		T25	4416

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	776506	1		T1	4		T2	4		T13	4
auto[1]	809498	1		T1	2		T2	2		T13	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	264181	1		T1	1		T2	1		T13	1
all_values[0]	auto[1]	auto[1]	153	1		T251	5		T252	1		T253	2
all_values[1]	auto[0]	auto[1]	264177	1		T1	1		T2	1		T13	1
all_values[1]	auto[1]	auto[1]	157	1		T251	2		T252	4		T253	2
all_values[2]	auto[0]	auto[0]	1563	1		T1	1		T2	1		T13	1
all_values[2]	auto[0]	auto[1]	62	1		T251	1		T252	3		T253	1
all_values[2]	auto[1]	auto[0]	262655	1		T39	4947		T40	9726		T25	1104
all_values[2]	auto[1]	auto[1]	54	1		T251	3		T252	1		T253	1
all_values[3]	auto[0]	auto[0]	1548	1		T1	1		T2	1		T13	1
all_values[3]	auto[0]	auto[1]	65	1		T251	2		T252	4		T253	1
all_values[3]	auto[1]	auto[0]	89235	1		T39	1649		T40	1621		T25	552
all_values[3]	auto[1]	auto[1]	173486	1		T39	3298		T40	8105		T25	552
all_values[4]	auto[0]	auto[0]	1120	1		T1	1		T2	1		T13	1
all_values[4]	auto[0]	auto[1]	527	1		T4	1		T5	1		T9	1
all_values[4]	auto[1]	auto[0]	156242	1		T39	3298		T40	8105		T25	552
all_values[4]	auto[1]	auto[1]	106445	1		T39	1649		T40	1621		T25	552
all_values[5]	auto[0]	auto[0]	1501	1		T1	1		T2	1		T13	1
all_values[5]	auto[0]	auto[1]	136	1		T5	1		T41	1		T42	1
all_values[5]	auto[1]	auto[0]	262642	1		T39	4947		T40	9726		T25	1104
all_values[5]	auto[1]	auto[1]	55	1		T253	1		T337	2		T340	2