Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	244503	1		T1	643		T4	968		T5	461
auto[FlashEraseBank]	271913	1		T4	4		T5	291		T9	774

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	257410	1		T1	321		T4	642		T5	186
auto[FlashOpProgram]	239683	1		T1	161		T4	320		T5	566
auto[FlashOpErase]	15323	1		T1	161		T4	10		T28	100
auto[FlashOpInvalid]	4000	1		T28	200		T182	200		T79	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	257410	1		T1	321		T4	642		T5	186
op[FlashOpProgram]	239683	1		T1	161		T4	320		T5	566
op[FlashOpErase]	15323	1		T1	161		T4	10		T28	100
read_erase_read	654	1		T29	24		T6	7		T36	2
read_prog_read	830	1		T6	8		T47	9		T43	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	380723	1		T4	388		T5	632		T9	988
auto[FlashPartInfo]	131921	1		T1	643		T4	584		T5	118
auto[FlashPartInfo1]	874	1		T5	1		T9	2		T47	2
auto[FlashPartInfo2]	2898	1		T5	1		T9	9		T19	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189831	1		T4	256		T5	135		T9	988
auto[FlashPartData]	auto[FlashOpProgram]	183169	1		T4	128		T5	497		T19	2
auto[FlashPartData]	auto[FlashOpErase]	3805	1		T4	4		T28	96		T29	6
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T28	192		T182	200		T79	198
auto[FlashPartInfo]	auto[FlashOpRead]	65088	1		T1	321		T4	386		T5	50
auto[FlashPartInfo]	auto[FlashOpProgram]	55380	1		T1	161		T4	192		T5	68
auto[FlashPartInfo]	auto[FlashOpErase]	11381	1		T1	161		T4	6		T28	3
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T28	6		T110	6		T409	4
auto[FlashPartInfo1]	auto[FlashOpRead]	705	1		T5	1		T9	2		T47	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T79	1		T100	1		T111	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T79	1		T100	1		T102	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T79	2		T100	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1786	1		T9	9		T19	1		T31	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	972	1		T5	1		T28	1		T47	5
auto[FlashPartInfo2]	auto[FlashOpErase]	134	1		T28	1		T29	19		T87	35
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T28	2		T410	2		T411	2