Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	12	20	62.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	12	20	62.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29565	1		T1	324		T4	8		T28	400
auto[1]	16	1		T31	2		T175	1		T325	2
auto[2]	20	1		T61	4		T63	4		T81	8
auto[3]	62	1		T67	2		T177	1		T180	4

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7420	1		T1	81		T4	2		T31	1
evic_idx[1]	7414	1		T1	81		T4	2		T28	100
evic_idx[2]	7412	1		T1	81		T4	2		T28	100
evic_idx[3]	7417	1		T1	81		T4	2		T31	1

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28797	1		T1	324		T28	400		T45	1
evic_op[2]	305	1		T31	2		T67	2		T36	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	12	20	62.50	12

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8
*	[evic_op[2]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7193	1		T1	81		T28	100		T8	149
evic_idx[0]	evic_op[1]	auto[3]	8	1		T180	1		T326	2		T327	4
evic_idx[0]	evic_op[2]	auto[0]	63	1		T36	1		T154	1		T237	8
evic_idx[0]	evic_op[2]	auto[1]	6	1		T31	1		T325	1		T328	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T67	1		T329	1		T204	1
evic_idx[1]	evic_op[1]	auto[0]	7192	1		T1	81		T28	100		T8	149
evic_idx[1]	evic_op[1]	auto[3]	6	1		T180	1		T326	2		T327	3
evic_idx[1]	evic_op[2]	auto[0]	64	1		T36	1		T237	8		T330	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T331	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T67	1		T329	1		T205	1
evic_idx[2]	evic_op[1]	auto[0]	7193	1		T1	81		T28	100		T8	149
evic_idx[2]	evic_op[1]	auto[3]	6	1		T180	1		T326	2		T327	3
evic_idx[2]	evic_op[2]	auto[0]	64	1		T36	1		T185	1		T237	8
evic_idx[2]	evic_op[2]	auto[1]	4	1		T332	1		T331	1		T333	1
evic_idx[2]	evic_op[2]	auto[3]	5	1		T177	1		T181	1		T308	1
evic_idx[3]	evic_op[1]	auto[0]	7193	1		T1	81		T28	100		T45	1
evic_idx[3]	evic_op[1]	auto[3]	6	1		T180	1		T326	2		T327	3
evic_idx[3]	evic_op[2]	auto[0]	62	1		T36	1		T237	8		T86	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T31	1		T175	1		T325	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T204	1		T308	1		T334	1