Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6016	1		T344	2017		T345	1202		T346	2797
rd_lvl[2]	17827	1		T236	12698		T344	1012		T347	1943
rd_lvl[3]	18053	1		T40	4156		T236	423		T344	336
rd_lvl[4]	33358	1		T40	3949		T344	244		T348	3943
rd_lvl[5]	10828	1		T344	130		T349	2673		T348	1424
rd_lvl[6]	10674	1		T324	1291		T344	71		T350	323
rd_lvl[7]	6929	1		T39	1799		T324	309		T344	89
rd_lvl[8]	17485	1		T39	1499		T76	2982		T344	104
rd_lvl[9]	7140	1		T76	350		T164	611		T344	183
rd_lvl[10]	8317	1		T25	319		T164	1182		T273	271
rd_lvl[11]	3712	1		T25	230		T323	609		T273	175
rd_lvl[12]	7362	1		T203	209		T323	1128		T344	1
rd_lvl[13]	4054	1		T25	3		T37	149		T38	327
rd_lvl[14]	5504	1		T37	126		T38	126		T270	1184
rd_lvl[15]	4034	1		T203	55		T351	674		T352	309