Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	264334	1		T1	1		T2	1		T13	1
all_pins[1]	264334	1		T1	1		T2	1		T13	1
all_pins[2]	264334	1		T1	1		T2	1		T13	1
all_pins[3]	264334	1		T1	1		T2	1		T13	1
all_pins[4]	264334	1		T1	1		T2	1		T13	1
all_pins[5]	264334	1		T1	1		T2	1		T13	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1291536	1		T1	6		T2	6		T13	6
values[0x1]	294468	1		T39	4947		T40	10851		T25	1104
transitions[0x0=>0x1]	257178	1		T39	4947		T40	9726		T25	1104
transitions[0x1=>0x0]	257162	1		T39	4947		T40	9726		T25	1104

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	264181	1		T1	1		T2	1		T13	1
all_pins[0]	values[0x1]	153	1		T251	5		T252	1		T253	2
all_pins[0]	transitions[0x0=>0x1]	76	1		T251	3		T252	1		T253	2
all_pins[0]	transitions[0x1=>0x0]	80	1		T252	4		T253	2		T335	1
all_pins[1]	values[0x0]	264177	1		T1	1		T2	1		T13	1
all_pins[1]	values[0x1]	157	1		T251	2		T252	4		T253	2
all_pins[1]	transitions[0x0=>0x1]	133	1		T251	2		T252	3		T253	2
all_pins[1]	transitions[0x1=>0x0]	6082	1		T351	948		T352	198		T357	1037
all_pins[2]	values[0x0]	258228	1		T1	1		T2	1		T13	1
all_pins[2]	values[0x1]	6106	1		T351	948		T352	198		T357	1037
all_pins[2]	transitions[0x0=>0x1]	37	1		T251	3		T252	1		T335	1
all_pins[2]	transitions[0x1=>0x0]	161572	1		T39	3298		T40	8105		T25	552
all_pins[3]	values[0x0]	96693	1		T1	1		T2	1		T13	1
all_pins[3]	values[0x1]	167641	1		T39	3298		T40	8105		T25	552
all_pins[3]	transitions[0x0=>0x1]	136562	1		T39	3298		T40	6980		T25	552
all_pins[3]	transitions[0x1=>0x0]	89277	1		T39	1649		T40	1621		T25	552
all_pins[4]	values[0x0]	143978	1		T1	1		T2	1		T13	1
all_pins[4]	values[0x1]	120356	1		T39	1649		T40	2746		T25	552
all_pins[4]	transitions[0x0=>0x1]	120344	1		T39	1649		T40	2746		T25	552
all_pins[4]	transitions[0x1=>0x0]	43	1		T253	1		T337	1		T340	2
all_pins[5]	values[0x0]	264279	1		T1	1		T2	1		T13	1
all_pins[5]	values[0x1]	55	1		T253	1		T337	2		T340	2
all_pins[5]	transitions[0x0=>0x1]	26	1		T337	1		T340	2		T342	2
all_pins[5]	transitions[0x1=>0x0]	108	1		T251	5		T252	1		T253	2