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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.31 93.96 98.85 92.52 97.00 98.01 97.84


Total test records in report: 1237
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T1074 /workspace/coverage/default/3.flash_ctrl_full_mem_access.3264165144 May 30 01:10:03 PM PDT 24 May 30 01:51:50 PM PDT 24 313062085700 ps
T1075 /workspace/coverage/default/1.flash_ctrl_erase_suspend.3836603354 May 30 01:09:31 PM PDT 24 May 30 01:13:30 PM PDT 24 1210824600 ps
T1076 /workspace/coverage/default/49.flash_ctrl_disable.2088199803 May 30 01:14:10 PM PDT 24 May 30 01:14:34 PM PDT 24 60591600 ps
T1077 /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.4031100509 May 30 01:10:19 PM PDT 24 May 30 01:13:49 PM PDT 24 100961958100 ps
T1078 /workspace/coverage/default/11.flash_ctrl_connect.4065816549 May 30 01:10:58 PM PDT 24 May 30 01:11:15 PM PDT 24 15782900 ps
T1079 /workspace/coverage/default/25.flash_ctrl_disable.3968354224 May 30 01:13:01 PM PDT 24 May 30 01:13:24 PM PDT 24 19429100 ps
T1080 /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3467942927 May 30 01:10:05 PM PDT 24 May 30 01:10:37 PM PDT 24 38323200 ps
T1081 /workspace/coverage/default/47.flash_ctrl_alert_test.569733868 May 30 01:13:56 PM PDT 24 May 30 01:14:11 PM PDT 24 35780300 ps
T1082 /workspace/coverage/default/16.flash_ctrl_ro.2704375987 May 30 01:11:39 PM PDT 24 May 30 01:13:40 PM PDT 24 2321589600 ps
T1083 /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.4206415244 May 30 01:10:08 PM PDT 24 May 30 01:10:23 PM PDT 24 31260400 ps
T1084 /workspace/coverage/default/1.flash_ctrl_rw_derr.1498761041 May 30 01:09:33 PM PDT 24 May 30 01:19:43 PM PDT 24 14506290500 ps
T1085 /workspace/coverage/default/19.flash_ctrl_connect.1629470668 May 30 01:12:14 PM PDT 24 May 30 01:12:31 PM PDT 24 16121000 ps
T1086 /workspace/coverage/default/16.flash_ctrl_smoke.1199817497 May 30 01:11:42 PM PDT 24 May 30 01:12:58 PM PDT 24 183716800 ps
T1087 /workspace/coverage/default/5.flash_ctrl_fetch_code.1735091758 May 30 01:10:11 PM PDT 24 May 30 01:10:33 PM PDT 24 369221600 ps
T1088 /workspace/coverage/default/18.flash_ctrl_rand_ops.783125415 May 30 01:11:54 PM PDT 24 May 30 01:26:05 PM PDT 24 792142900 ps
T1089 /workspace/coverage/default/1.flash_ctrl_serr_counter.1257414154 May 30 01:09:33 PM PDT 24 May 30 01:10:45 PM PDT 24 2920354600 ps
T1090 /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.4100172167 May 30 01:13:30 PM PDT 24 May 30 01:16:24 PM PDT 24 2215778200 ps
T1091 /workspace/coverage/default/1.flash_ctrl_full_mem_access.1246390919 May 30 01:09:33 PM PDT 24 May 30 01:55:17 PM PDT 24 159625780700 ps
T1092 /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3087429407 May 30 01:09:31 PM PDT 24 May 30 01:10:28 PM PDT 24 10034144800 ps
T1093 /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1897170361 May 30 01:12:58 PM PDT 24 May 30 01:13:27 PM PDT 24 40031900 ps
T1094 /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1215507030 May 30 01:10:22 PM PDT 24 May 30 01:13:03 PM PDT 24 18713695700 ps
T1095 /workspace/coverage/default/49.flash_ctrl_otp_reset.248474684 May 30 01:14:15 PM PDT 24 May 30 01:16:31 PM PDT 24 40541000 ps
T169 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3952518147 May 30 01:04:57 PM PDT 24 May 30 01:05:17 PM PDT 24 55600600 ps
T251 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3467209229 May 30 01:04:58 PM PDT 24 May 30 01:05:12 PM PDT 24 31042100 ps
T1096 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1530996796 May 30 01:05:10 PM PDT 24 May 30 01:05:26 PM PDT 24 66313100 ps
T252 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3905395349 May 30 01:05:17 PM PDT 24 May 30 01:05:32 PM PDT 24 24216000 ps
T1097 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2931731937 May 30 01:05:20 PM PDT 24 May 30 01:05:37 PM PDT 24 33415700 ps
T72 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.781321278 May 30 01:05:15 PM PDT 24 May 30 01:20:03 PM PDT 24 5389221800 ps
T1098 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1702020427 May 30 01:05:15 PM PDT 24 May 30 01:05:31 PM PDT 24 25844500 ps
T1099 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3946006994 May 30 01:05:06 PM PDT 24 May 30 01:05:24 PM PDT 24 29132100 ps
T1100 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1922787063 May 30 01:04:55 PM PDT 24 May 30 01:05:11 PM PDT 24 14859800 ps
T73 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1619384283 May 30 01:05:38 PM PDT 24 May 30 01:05:55 PM PDT 24 123612300 ps
T1101 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1780339989 May 30 01:05:13 PM PDT 24 May 30 01:05:27 PM PDT 24 14062900 ps
T253 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.783594969 May 30 01:04:54 PM PDT 24 May 30 01:05:08 PM PDT 24 49473400 ps
T74 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2303305143 May 30 01:05:14 PM PDT 24 May 30 01:12:58 PM PDT 24 460825800 ps
T335 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1669620346 May 30 01:05:21 PM PDT 24 May 30 01:05:35 PM PDT 24 31900100 ps
T170 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1511529908 May 30 01:05:14 PM PDT 24 May 30 01:05:32 PM PDT 24 604522900 ps
T214 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.893882686 May 30 01:05:14 PM PDT 24 May 30 01:05:31 PM PDT 24 312877000 ps
T240 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.259122447 May 30 01:04:58 PM PDT 24 May 30 01:05:17 PM PDT 24 194660300 ps
T241 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2448286362 May 30 01:04:56 PM PDT 24 May 30 01:05:12 PM PDT 24 965416200 ps
T215 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2819774333 May 30 01:04:58 PM PDT 24 May 30 01:19:59 PM PDT 24 4221082900 ps
T221 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1313155726 May 30 01:05:19 PM PDT 24 May 30 01:05:34 PM PDT 24 25293200 ps
T336 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.342827586 May 30 01:05:17 PM PDT 24 May 30 01:05:32 PM PDT 24 16475000 ps
T1102 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1350099357 May 30 01:05:08 PM PDT 24 May 30 01:05:25 PM PDT 24 14920100 ps
T338 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.750928165 May 30 01:05:23 PM PDT 24 May 30 01:05:38 PM PDT 24 18113300 ps
T222 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.842437554 May 30 01:05:26 PM PDT 24 May 30 01:05:46 PM PDT 24 49836400 ps
T337 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3535028424 May 30 01:05:36 PM PDT 24 May 30 01:05:50 PM PDT 24 80023000 ps
T223 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2027189077 May 30 01:04:57 PM PDT 24 May 30 01:05:16 PM PDT 24 51358400 ps
T228 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3632160028 May 30 01:05:02 PM PDT 24 May 30 01:05:17 PM PDT 24 34988300 ps
T242 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2976635459 May 30 01:05:09 PM PDT 24 May 30 01:05:27 PM PDT 24 61594700 ps
T340 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3533834942 May 30 01:05:28 PM PDT 24 May 30 01:05:42 PM PDT 24 46852600 ps
T342 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2937368595 May 30 01:04:58 PM PDT 24 May 30 01:05:13 PM PDT 24 27565900 ps
T416 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1016654764 May 30 01:05:09 PM PDT 24 May 30 01:05:46 PM PDT 24 642758000 ps
T417 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3119819629 May 30 01:05:11 PM PDT 24 May 30 01:05:43 PM PDT 24 867406200 ps
T339 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2683147489 May 30 01:05:24 PM PDT 24 May 30 01:05:38 PM PDT 24 16513200 ps
T1103 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.623687760 May 30 01:04:59 PM PDT 24 May 30 01:05:16 PM PDT 24 34716800 ps
T243 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1712647273 May 30 01:05:02 PM PDT 24 May 30 01:05:21 PM PDT 24 121355600 ps
T224 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1806256614 May 30 01:05:14 PM PDT 24 May 30 01:05:31 PM PDT 24 91916000 ps
T1104 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3110868233 May 30 01:05:07 PM PDT 24 May 30 01:05:39 PM PDT 24 31070700 ps
T1105 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4005637406 May 30 01:04:55 PM PDT 24 May 30 01:05:43 PM PDT 24 125214600 ps
T225 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3751685008 May 30 01:04:52 PM PDT 24 May 30 01:05:09 PM PDT 24 79197100 ps
T1106 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.462468296 May 30 01:05:12 PM PDT 24 May 30 01:05:25 PM PDT 24 14026300 ps
T1107 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2880596399 May 30 01:05:33 PM PDT 24 May 30 01:05:51 PM PDT 24 137330200 ps
T1108 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.203545629 May 30 01:05:11 PM PDT 24 May 30 01:05:25 PM PDT 24 13338200 ps
T226 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2002988983 May 30 01:05:01 PM PDT 24 May 30 01:05:25 PM PDT 24 99250200 ps
T1109 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.426722435 May 30 01:04:56 PM PDT 24 May 30 01:05:17 PM PDT 24 1428460500 ps
T1110 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2846513669 May 30 01:05:20 PM PDT 24 May 30 01:05:39 PM PDT 24 61876500 ps
T1111 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.100932610 May 30 01:04:58 PM PDT 24 May 30 01:05:18 PM PDT 24 23892800 ps
T216 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1898201519 May 30 01:04:58 PM PDT 24 May 30 01:05:17 PM PDT 24 395653200 ps
T1112 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2814945462 May 30 01:05:17 PM PDT 24 May 30 01:05:31 PM PDT 24 55262400 ps
T260 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4140199864 May 30 01:04:55 PM PDT 24 May 30 01:12:37 PM PDT 24 3682574400 ps
T291 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.739332689 May 30 01:05:17 PM PDT 24 May 30 01:05:35 PM PDT 24 194407800 ps
T1113 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.580202019 May 30 01:05:23 PM PDT 24 May 30 01:06:33 PM PDT 24 2421503700 ps
T1114 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1267402941 May 30 01:04:54 PM PDT 24 May 30 01:05:39 PM PDT 24 1243919600 ps
T229 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.711780725 May 30 01:04:53 PM PDT 24 May 30 01:05:08 PM PDT 24 48366200 ps
T1115 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.116422628 May 30 01:04:53 PM PDT 24 May 30 01:05:07 PM PDT 24 169733000 ps
T1116 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1561533834 May 30 01:04:58 PM PDT 24 May 30 01:05:15 PM PDT 24 24774700 ps
T1117 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.296580944 May 30 01:05:08 PM PDT 24 May 30 01:05:24 PM PDT 24 13079300 ps
T1118 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1812732894 May 30 01:04:59 PM PDT 24 May 30 01:05:39 PM PDT 24 31215800 ps
T1119 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.486110429 May 30 01:04:51 PM PDT 24 May 30 01:05:05 PM PDT 24 46821900 ps
T1120 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.459272895 May 30 01:05:19 PM PDT 24 May 30 01:05:37 PM PDT 24 50845300 ps
T1121 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.826367281 May 30 01:05:13 PM PDT 24 May 30 01:05:28 PM PDT 24 337255300 ps
T1122 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.337647265 May 30 01:04:58 PM PDT 24 May 30 01:05:15 PM PDT 24 18456900 ps
T1123 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3591942511 May 30 01:04:48 PM PDT 24 May 30 01:05:04 PM PDT 24 29997200 ps
T248 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3186378670 May 30 01:05:26 PM PDT 24 May 30 01:05:43 PM PDT 24 37613300 ps
T1124 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1438914344 May 30 01:05:16 PM PDT 24 May 30 01:05:31 PM PDT 24 49742200 ps
T1125 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3630095720 May 30 01:05:09 PM PDT 24 May 30 01:05:24 PM PDT 24 24378600 ps
T1126 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3099127878 May 30 01:04:58 PM PDT 24 May 30 01:05:54 PM PDT 24 1804839100 ps
T1127 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1247595237 May 30 01:05:01 PM PDT 24 May 30 01:05:19 PM PDT 24 18642500 ps
T263 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4280891947 May 30 01:05:28 PM PDT 24 May 30 01:20:13 PM PDT 24 951488100 ps
T261 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3693157081 May 30 01:05:17 PM PDT 24 May 30 01:05:38 PM PDT 24 176818300 ps
T1128 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3937846303 May 30 01:05:06 PM PDT 24 May 30 01:05:40 PM PDT 24 58137100 ps
T1129 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2054558771 May 30 01:04:53 PM PDT 24 May 30 01:05:13 PM PDT 24 231958500 ps
T285 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1021265355 May 30 01:05:06 PM PDT 24 May 30 01:11:37 PM PDT 24 826711600 ps
T1130 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4938892 May 30 01:05:18 PM PDT 24 May 30 01:05:35 PM PDT 24 12346200 ps
T250 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3537667931 May 30 01:05:18 PM PDT 24 May 30 01:05:36 PM PDT 24 314016100 ps
T1131 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3784644508 May 30 01:05:08 PM PDT 24 May 30 01:05:24 PM PDT 24 21423800 ps
T286 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1991840317 May 30 01:05:24 PM PDT 24 May 30 01:05:40 PM PDT 24 130035200 ps
T1132 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3371180953 May 30 01:05:06 PM PDT 24 May 30 01:05:23 PM PDT 24 18060100 ps
T365 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1667152157 May 30 01:05:07 PM PDT 24 May 30 01:12:46 PM PDT 24 1103224000 ps
T341 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1841345554 May 30 01:05:17 PM PDT 24 May 30 01:05:36 PM PDT 24 24541000 ps
T1133 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1635879887 May 30 01:05:18 PM PDT 24 May 30 01:05:52 PM PDT 24 63395300 ps
T257 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3610688211 May 30 01:05:00 PM PDT 24 May 30 01:05:22 PM PDT 24 444712800 ps
T287 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2131415308 May 30 01:05:25 PM PDT 24 May 30 01:05:45 PM PDT 24 207070200 ps
T1134 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1961368867 May 30 01:04:52 PM PDT 24 May 30 01:05:11 PM PDT 24 39118300 ps
T1135 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4233147391 May 30 01:05:01 PM PDT 24 May 30 01:05:18 PM PDT 24 14959500 ps
T1136 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1875787181 May 30 01:05:21 PM PDT 24 May 30 01:05:36 PM PDT 24 17929300 ps
T1137 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.587520860 May 30 01:05:03 PM PDT 24 May 30 01:05:22 PM PDT 24 41141700 ps
T230 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2483265333 May 30 01:05:10 PM PDT 24 May 30 01:05:24 PM PDT 24 49374200 ps
T1138 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2689360674 May 30 01:05:16 PM PDT 24 May 30 01:05:32 PM PDT 24 44570300 ps
T1139 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1291235171 May 30 01:04:59 PM PDT 24 May 30 01:05:14 PM PDT 24 47810400 ps
T1140 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2651389969 May 30 01:05:00 PM PDT 24 May 30 01:05:17 PM PDT 24 29617900 ps
T1141 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3529384825 May 30 01:05:45 PM PDT 24 May 30 01:05:59 PM PDT 24 74979100 ps
T1142 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1616302767 May 30 01:05:13 PM PDT 24 May 30 01:05:27 PM PDT 24 20182900 ps
T288 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.513815574 May 30 01:05:23 PM PDT 24 May 30 01:05:39 PM PDT 24 43717900 ps
T1143 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1752313955 May 30 01:05:31 PM PDT 24 May 30 01:05:45 PM PDT 24 17375900 ps
T359 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2401124130 May 30 01:05:09 PM PDT 24 May 30 01:11:34 PM PDT 24 197986600 ps
T343 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4244180548 May 30 01:05:13 PM PDT 24 May 30 01:05:27 PM PDT 24 32006600 ps
T1144 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.810549666 May 30 01:05:09 PM PDT 24 May 30 01:05:26 PM PDT 24 15054500 ps
T289 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1427874013 May 30 01:04:58 PM PDT 24 May 30 01:05:39 PM PDT 24 314285600 ps
T1145 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.924316978 May 30 01:04:59 PM PDT 24 May 30 01:05:14 PM PDT 24 55028300 ps
T290 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2776028477 May 30 01:05:06 PM PDT 24 May 30 01:05:53 PM PDT 24 1463963700 ps
T1146 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1661239510 May 30 01:05:20 PM PDT 24 May 30 01:05:34 PM PDT 24 169667300 ps
T249 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1078692977 May 30 01:05:14 PM PDT 24 May 30 01:05:35 PM PDT 24 117556200 ps
T1147 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3484379011 May 30 01:05:16 PM PDT 24 May 30 01:05:32 PM PDT 24 55642400 ps
T258 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2071913425 May 30 01:04:56 PM PDT 24 May 30 01:17:36 PM PDT 24 1328253300 ps
T1148 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4091601639 May 30 01:05:19 PM PDT 24 May 30 01:05:33 PM PDT 24 53613700 ps
T363 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2809693074 May 30 01:05:37 PM PDT 24 May 30 01:20:36 PM PDT 24 2762818500 ps
T1149 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.834320353 May 30 01:04:56 PM PDT 24 May 30 01:05:11 PM PDT 24 15467300 ps
T1150 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2595681108 May 30 01:05:22 PM PDT 24 May 30 01:05:37 PM PDT 24 28686700 ps
T259 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.519696526 May 30 01:05:31 PM PDT 24 May 30 01:18:20 PM PDT 24 1735642100 ps
T1151 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2329373798 May 30 01:05:17 PM PDT 24 May 30 01:05:31 PM PDT 24 30903200 ps
T1152 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4126543920 May 30 01:05:07 PM PDT 24 May 30 01:05:39 PM PDT 24 446989000 ps
T1153 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.984143209 May 30 01:05:09 PM PDT 24 May 30 01:05:28 PM PDT 24 88631000 ps
T1154 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1947605763 May 30 01:05:38 PM PDT 24 May 30 01:05:53 PM PDT 24 31117300 ps
T1155 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2741211875 May 30 01:05:28 PM PDT 24 May 30 01:05:42 PM PDT 24 18108600 ps
T254 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.942379052 May 30 01:05:12 PM PDT 24 May 30 01:05:33 PM PDT 24 109468700 ps
T1156 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3848216537 May 30 01:05:11 PM PDT 24 May 30 01:05:27 PM PDT 24 122935200 ps
T255 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1008624687 May 30 01:05:11 PM PDT 24 May 30 01:05:31 PM PDT 24 51476000 ps
T292 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2568905930 May 30 01:05:08 PM PDT 24 May 30 01:05:26 PM PDT 24 39418800 ps
T1157 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2712471302 May 30 01:04:57 PM PDT 24 May 30 01:05:12 PM PDT 24 15059500 ps
T1158 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2313240465 May 30 01:05:21 PM PDT 24 May 30 01:05:36 PM PDT 24 133359100 ps
T293 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2247868712 May 30 01:05:00 PM PDT 24 May 30 01:06:13 PM PDT 24 2843544200 ps
T1159 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.321271082 May 30 01:05:02 PM PDT 24 May 30 01:05:17 PM PDT 24 42691300 ps
T1160 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2436769991 May 30 01:04:54 PM PDT 24 May 30 01:05:39 PM PDT 24 6391022200 ps
T1161 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4205908801 May 30 01:05:29 PM PDT 24 May 30 01:05:43 PM PDT 24 53743900 ps
T1162 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2866983599 May 30 01:05:09 PM PDT 24 May 30 01:05:24 PM PDT 24 15860000 ps
T1163 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1724042573 May 30 01:05:33 PM PDT 24 May 30 01:05:49 PM PDT 24 13076000 ps
T1164 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1906767021 May 30 01:05:20 PM PDT 24 May 30 01:05:56 PM PDT 24 324813900 ps
T1165 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1007355914 May 30 01:04:58 PM PDT 24 May 30 01:05:13 PM PDT 24 25615300 ps
T1166 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.869614489 May 30 01:05:35 PM PDT 24 May 30 01:05:52 PM PDT 24 99907500 ps
T358 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1686459304 May 30 01:04:53 PM PDT 24 May 30 01:12:33 PM PDT 24 347601400 ps
T1167 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1568935942 May 30 01:04:48 PM PDT 24 May 30 01:05:02 PM PDT 24 44501100 ps
T294 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.620565224 May 30 01:05:11 PM PDT 24 May 30 01:05:31 PM PDT 24 538116300 ps
T256 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3370797511 May 30 01:05:26 PM PDT 24 May 30 01:05:45 PM PDT 24 62423900 ps
T262 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2482677984 May 30 01:04:54 PM PDT 24 May 30 01:11:18 PM PDT 24 244446800 ps
T1168 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3258365228 May 30 01:05:23 PM PDT 24 May 30 01:05:38 PM PDT 24 15669500 ps
T1169 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2156749989 May 30 01:05:15 PM PDT 24 May 30 01:05:30 PM PDT 24 17000800 ps
T1170 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2265721938 May 30 01:05:17 PM PDT 24 May 30 01:05:32 PM PDT 24 14071200 ps
T1171 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1943550378 May 30 01:05:12 PM PDT 24 May 30 01:05:26 PM PDT 24 104865300 ps
T1172 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3632197568 May 30 01:05:31 PM PDT 24 May 30 01:05:46 PM PDT 24 15560100 ps
T1173 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1716087809 May 30 01:05:17 PM PDT 24 May 30 01:05:32 PM PDT 24 15624500 ps
T362 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3174168894 May 30 01:04:52 PM PDT 24 May 30 01:12:34 PM PDT 24 2104879300 ps
T1174 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2837447570 May 30 01:05:08 PM PDT 24 May 30 01:05:43 PM PDT 24 67254000 ps
T1175 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3886280476 May 30 01:05:21 PM PDT 24 May 30 01:05:35 PM PDT 24 56832100 ps
T1176 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.235412243 May 30 01:05:14 PM PDT 24 May 30 01:05:32 PM PDT 24 469726200 ps
T1177 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4290641724 May 30 01:05:12 PM PDT 24 May 30 01:05:30 PM PDT 24 35469500 ps
T1178 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4280192027 May 30 01:04:53 PM PDT 24 May 30 01:05:10 PM PDT 24 62359000 ps
T1179 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2858928714 May 30 01:05:11 PM PDT 24 May 30 01:05:27 PM PDT 24 24164400 ps
T1180 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1073615104 May 30 01:05:28 PM PDT 24 May 30 01:05:42 PM PDT 24 88039500 ps
T264 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3831216654 May 30 01:05:10 PM PDT 24 May 30 01:05:31 PM PDT 24 103341200 ps
T231 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4152652994 May 30 01:05:04 PM PDT 24 May 30 01:05:19 PM PDT 24 17626800 ps
T1181 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.290183389 May 30 01:04:59 PM PDT 24 May 30 01:05:17 PM PDT 24 30104800 ps
T1182 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.403521226 May 30 01:05:06 PM PDT 24 May 30 01:05:20 PM PDT 24 33523400 ps
T364 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3056144484 May 30 01:05:12 PM PDT 24 May 30 01:11:46 PM PDT 24 1591848300 ps
T1183 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.764689332 May 30 01:05:24 PM PDT 24 May 30 01:05:39 PM PDT 24 114672200 ps
T1184 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1616835739 May 30 01:05:06 PM PDT 24 May 30 01:05:27 PM PDT 24 64394800 ps
T1185 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.348860937 May 30 01:05:24 PM PDT 24 May 30 01:05:38 PM PDT 24 24756500 ps
T1186 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3221429524 May 30 01:05:26 PM PDT 24 May 30 01:05:40 PM PDT 24 27026300 ps
T295 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2525161179 May 30 01:05:23 PM PDT 24 May 30 01:05:41 PM PDT 24 239875800 ps
T1187 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.61278996 May 30 01:05:20 PM PDT 24 May 30 01:05:37 PM PDT 24 57715200 ps
T1188 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3593159273 May 30 01:04:57 PM PDT 24 May 30 01:05:15 PM PDT 24 42490100 ps
T1189 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1927417422 May 30 01:05:02 PM PDT 24 May 30 01:05:20 PM PDT 24 21749700 ps
T1190 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1572403760 May 30 01:05:13 PM PDT 24 May 30 01:05:30 PM PDT 24 36846400 ps
T1191 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.375680853 May 30 01:05:21 PM PDT 24 May 30 01:17:55 PM PDT 24 1303200700 ps
T1192 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1422558894 May 30 01:05:17 PM PDT 24 May 30 01:05:36 PM PDT 24 56319000 ps
T1193 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3314673572 May 30 01:04:56 PM PDT 24 May 30 01:05:28 PM PDT 24 103689100 ps
T1194 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3101884367 May 30 01:05:16 PM PDT 24 May 30 01:05:33 PM PDT 24 146565200 ps
T1195 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2060931840 May 30 01:05:32 PM PDT 24 May 30 01:05:46 PM PDT 24 137282400 ps
T1196 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2083865703 May 30 01:05:29 PM PDT 24 May 30 01:05:43 PM PDT 24 15404600 ps
T1197 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2697634954 May 30 01:05:26 PM PDT 24 May 30 01:05:41 PM PDT 24 20456400 ps
T1198 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1045575938 May 30 01:05:23 PM PDT 24 May 30 01:13:03 PM PDT 24 1185625000 ps
T296 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.887710131 May 30 01:04:59 PM PDT 24 May 30 01:05:19 PM PDT 24 108213800 ps
T1199 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2887464534 May 30 01:05:07 PM PDT 24 May 30 01:05:24 PM PDT 24 21710700 ps
T1200 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.589137835 May 30 01:05:23 PM PDT 24 May 30 01:05:38 PM PDT 24 34903600 ps
T1201 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2770109970 May 30 01:05:20 PM PDT 24 May 30 01:05:35 PM PDT 24 27528800 ps
T1202 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.188821037 May 30 01:05:24 PM PDT 24 May 30 01:05:40 PM PDT 24 22355700 ps
T1203 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3396037110 May 30 01:05:24 PM PDT 24 May 30 01:05:43 PM PDT 24 209797500 ps
T1204 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2586902373 May 30 01:04:56 PM PDT 24 May 30 01:05:13 PM PDT 24 34769000 ps
T1205 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1798339008 May 30 01:05:18 PM PDT 24 May 30 01:05:37 PM PDT 24 35932600 ps
T1206 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2494907775 May 30 01:05:23 PM PDT 24 May 30 01:05:37 PM PDT 24 14730200 ps
T1207 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.638968015 May 30 01:05:10 PM PDT 24 May 30 01:05:24 PM PDT 24 14565400 ps
T1208 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2541834569 May 30 01:05:12 PM PDT 24 May 30 01:05:28 PM PDT 24 50335300 ps
T1209 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4088683465 May 30 01:04:59 PM PDT 24 May 30 01:05:17 PM PDT 24 25475900 ps
T1210 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.226245021 May 30 01:05:00 PM PDT 24 May 30 01:05:19 PM PDT 24 73293400 ps
T1211 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3635419440 May 30 01:04:53 PM PDT 24 May 30 01:05:11 PM PDT 24 65299000 ps
T297 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2093828726 May 30 01:04:55 PM PDT 24 May 30 01:05:35 PM PDT 24 1672677700 ps
T361 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.927693170 May 30 01:05:15 PM PDT 24 May 30 01:12:54 PM PDT 24 368276100 ps
T1212 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1839799372 May 30 01:04:59 PM PDT 24 May 30 01:05:20 PM PDT 24 522798700 ps
T360 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.421460776 May 30 01:05:23 PM PDT 24 May 30 01:20:18 PM PDT 24 687142000 ps
T1213 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.613052873 May 30 01:05:22 PM PDT 24 May 30 01:05:39 PM PDT 24 19867400 ps
T1214 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.453631399 May 30 01:05:09 PM PDT 24 May 30 01:12:47 PM PDT 24 1364797500 ps
T232 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1404441955 May 30 01:05:02 PM PDT 24 May 30 01:05:17 PM PDT 24 17746300 ps
T1215 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1408509938 May 30 01:05:11 PM PDT 24 May 30 01:05:28 PM PDT 24 14118300 ps
T1216 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4069866093 May 30 01:05:10 PM PDT 24 May 30 01:05:29 PM PDT 24 1027779600 ps
T1217 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3525202453 May 30 01:05:03 PM PDT 24 May 30 01:05:21 PM PDT 24 41787100 ps
T1218 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2557764548 May 30 01:05:05 PM PDT 24 May 30 01:05:22 PM PDT 24 79995700 ps
T298 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3853400184 May 30 01:05:06 PM PDT 24 May 30 01:05:25 PM PDT 24 232435000 ps
T1219 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.141966599 May 30 01:05:18 PM PDT 24 May 30 01:05:32 PM PDT 24 42782400 ps
T1220 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1490861973 May 30 01:05:15 PM PDT 24 May 30 01:05:33 PM PDT 24 181956400 ps
T1221 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3484718668 May 30 01:05:02 PM PDT 24 May 30 01:05:18 PM PDT 24 12466900 ps
T1222 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1232094386 May 30 01:05:16 PM PDT 24 May 30 01:05:30 PM PDT 24 48143800 ps
T1223 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1751122701 May 30 01:05:07 PM PDT 24 May 30 01:05:25 PM PDT 24 85688700 ps
T1224 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.497412654 May 30 01:05:26 PM PDT 24 May 30 01:05:42 PM PDT 24 12383200 ps
T1225 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3117068404 May 30 01:05:26 PM PDT 24 May 30 01:05:43 PM PDT 24 36956300 ps
T1226 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4074245579 May 30 01:05:30 PM PDT 24 May 30 01:05:50 PM PDT 24 119634600 ps
T1227 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3294873773 May 30 01:05:03 PM PDT 24 May 30 01:05:18 PM PDT 24 15039700 ps
T1228 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3295511657 May 30 01:05:08 PM PDT 24 May 30 01:05:26 PM PDT 24 88620800 ps
T1229 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1664409393 May 30 01:04:57 PM PDT 24 May 30 01:05:26 PM PDT 24 89804700 ps
T1230 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3211981765 May 30 01:05:22 PM PDT 24 May 30 01:05:37 PM PDT 24 209327400 ps
T1231 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3477156600 May 30 01:05:36 PM PDT 24 May 30 01:05:51 PM PDT 24 14774900 ps
T1232 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2800339421 May 30 01:05:25 PM PDT 24 May 30 01:05:39 PM PDT 24 27673100 ps
T1233 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2453955246 May 30 01:05:30 PM PDT 24 May 30 01:05:45 PM PDT 24 35046900 ps
T1234 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.915797268 May 30 01:05:15 PM PDT 24 May 30 01:05:34 PM PDT 24 102292700 ps
T1235 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1802797253 May 30 01:05:30 PM PDT 24 May 30 01:05:45 PM PDT 24 26385000 ps
T1236 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.137679765 May 30 01:05:20 PM PDT 24 May 30 01:05:34 PM PDT 24 16334600 ps
T1237 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.327051119 May 30 01:05:33 PM PDT 24 May 30 01:05:47 PM PDT 24 16879200 ps

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3020153756
Short name T4
Test name
Test status
Simulation time 334664356400 ps
CPU time 1794.3 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:39:28 PM PDT 24
Peak memory 263804 kb
Host smart-0cda8394-9192-48bf-934b-2866dba7c867
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020153756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3020153756
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2017142507
Short name T6
Test name
Test status
Simulation time 34561061100 ps
CPU time 434.18 seconds
Started May 30 01:10:14 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 274248 kb
Host smart-d7adb847-defd-4270-91d0-145bd4943048
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017142507 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2017142507
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.781321278
Short name T72
Test name
Test status
Simulation time 5389221800 ps
CPU time 886.99 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:20:03 PM PDT 24
Peak memory 264204 kb
Host smart-d344189b-76ee-4849-9095-34f45c086444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781321278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.781321278
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.78455032
Short name T19
Test name
Test status
Simulation time 30165900 ps
CPU time 30.69 seconds
Started May 30 01:10:10 PM PDT 24
Finished May 30 01:10:42 PM PDT 24
Peak memory 273220 kb
Host smart-127e277b-4598-4984-9ae8-375eafc9663d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78455032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_rw_evict.78455032
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3273275478
Short name T47
Test name
Test status
Simulation time 6668353100 ps
CPU time 525.15 seconds
Started May 30 01:11:26 PM PDT 24
Finished May 30 01:20:12 PM PDT 24
Peak memory 313320 kb
Host smart-ab291bde-bd88-4807-8331-2faeb1cdaef6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273275478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.3273275478
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.154015023
Short name T15
Test name
Test status
Simulation time 1988931900 ps
CPU time 4734.89 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 02:28:45 PM PDT 24
Peak memory 286304 kb
Host smart-8cc8aec0-74bf-479e-a49b-d2c0557da847
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154015023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.154015023
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.111571695
Short name T52
Test name
Test status
Simulation time 40646100 ps
CPU time 130.23 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 259656 kb
Host smart-b927947a-3012-4730-875a-2ec315fdd75e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111571695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ot
p_reset.111571695
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4140199864
Short name T260
Test name
Test status
Simulation time 3682574400 ps
CPU time 460.59 seconds
Started May 30 01:04:55 PM PDT 24
Finished May 30 01:12:37 PM PDT 24
Peak memory 264160 kb
Host smart-a95a1ff1-a371-4344-9fbb-47bfbdde5664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140199864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.4140199864
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3990353206
Short name T61
Test name
Test status
Simulation time 6755315100 ps
CPU time 296.09 seconds
Started May 30 01:09:12 PM PDT 24
Finished May 30 01:14:09 PM PDT 24
Peak memory 261016 kb
Host smart-f90d3de1-b66d-4819-a950-97c190f795f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990353206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3990353206
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2644673680
Short name T95
Test name
Test status
Simulation time 153866600 ps
CPU time 130.52 seconds
Started May 30 01:13:54 PM PDT 24
Finished May 30 01:16:06 PM PDT 24
Peak memory 259688 kb
Host smart-18d4b7f1-ce66-4055-91a9-8ab0d6292847
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644673680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2644673680
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.3868694386
Short name T45
Test name
Test status
Simulation time 2583393000 ps
CPU time 71.46 seconds
Started May 30 01:09:57 PM PDT 24
Finished May 30 01:11:10 PM PDT 24
Peak memory 259640 kb
Host smart-1b4b26d5-17e8-4c4c-a6a7-1db867cc2b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868694386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3868694386
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2027189077
Short name T223
Test name
Test status
Simulation time 51358400 ps
CPU time 18.25 seconds
Started May 30 01:04:57 PM PDT 24
Finished May 30 01:05:16 PM PDT 24
Peak memory 264104 kb
Host smart-45cfe153-19c5-43c7-b009-8b1b5b768b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027189077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2027189077
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.558492454
Short name T156
Test name
Test status
Simulation time 7831592500 ps
CPU time 607.57 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:20:17 PM PDT 24
Peak memory 337996 kb
Host smart-0800d8b9-43c3-43f5-ac04-1300081aa954
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558492454 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_rw_derr.558492454
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.60674201
Short name T120
Test name
Test status
Simulation time 70202700 ps
CPU time 129.42 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 263124 kb
Host smart-07d1f46a-9695-433d-bd31-3f6f6b7012a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60674201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp
_reset.60674201
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.813099837
Short name T18
Test name
Test status
Simulation time 25154300 ps
CPU time 13.53 seconds
Started May 30 01:12:11 PM PDT 24
Finished May 30 01:12:25 PM PDT 24
Peak memory 264748 kb
Host smart-00f8014d-9d8e-4cff-ad49-17b1a828ad94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813099837 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.813099837
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2937368595
Short name T342
Test name
Test status
Simulation time 27565900 ps
CPU time 13.8 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:13 PM PDT 24
Peak memory 262688 kb
Host smart-248dfbca-f910-4dbe-bce8-6fbc0a65e2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937368595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2937368595
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.571128651
Short name T302
Test name
Test status
Simulation time 3451925100 ps
CPU time 124.67 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:15:23 PM PDT 24
Peak memory 262364 kb
Host smart-137e012c-77ea-4b29-8e12-54788cec9534
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571128651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h
w_sec_otp.571128651
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2608397345
Short name T203
Test name
Test status
Simulation time 451998300 ps
CPU time 99.51 seconds
Started May 30 01:09:37 PM PDT 24
Finished May 30 01:11:18 PM PDT 24
Peak memory 289436 kb
Host smart-f1a9b21e-27fd-4632-9400-30d671d063bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608397345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2608397345
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2203631314
Short name T159
Test name
Test status
Simulation time 10033206000 ps
CPU time 96.97 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:12:37 PM PDT 24
Peak memory 264848 kb
Host smart-0fe247e8-b21e-40bd-9cb7-f0737e0eb05a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203631314 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2203631314
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.292709304
Short name T28
Test name
Test status
Simulation time 976892700 ps
CPU time 85.16 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:13:34 PM PDT 24
Peak memory 260232 kb
Host smart-44676e37-5164-4663-a06a-eb1e649f8d56
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292709304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.292709304
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3908405389
Short name T10
Test name
Test status
Simulation time 14366900 ps
CPU time 13.55 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:11 PM PDT 24
Peak memory 260916 kb
Host smart-f821843a-2f06-400b-85ed-7ee7e3f19b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908405389 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3908405389
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1574723979
Short name T36
Test name
Test status
Simulation time 734737900 ps
CPU time 79.16 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:11:08 PM PDT 24
Peak memory 263116 kb
Host smart-7f7b1f92-298b-4a2c-8a50-3e1e472e2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574723979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1574723979
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1079427479
Short name T83
Test name
Test status
Simulation time 131573000 ps
CPU time 13.73 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:11 PM PDT 24
Peak memory 262048 kb
Host smart-1f3713b5-8ef9-4744-91dc-dfc10e47fd2f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079427479 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1079427479
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.704497475
Short name T13
Test name
Test status
Simulation time 74342100 ps
CPU time 131.63 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 263844 kb
Host smart-f9e6a62f-a082-49c7-b01f-3be23001754c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704497475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.704497475
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3693212590
Short name T58
Test name
Test status
Simulation time 74184800 ps
CPU time 14.07 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:11:13 PM PDT 24
Peak memory 264200 kb
Host smart-226e192d-06a5-4fd8-b361-82da988fe10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693212590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3693212590
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3403621668
Short name T777
Test name
Test status
Simulation time 43323300 ps
CPU time 110.23 seconds
Started May 30 01:11:53 PM PDT 24
Finished May 30 01:13:44 PM PDT 24
Peak memory 259740 kb
Host smart-235096c7-7d1c-4f08-9199-b865d908bbad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403621668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3403621668
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3032951636
Short name T30
Test name
Test status
Simulation time 187329100 ps
CPU time 13.81 seconds
Started May 30 01:12:27 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 258424 kb
Host smart-0de78a65-18f5-47a4-993b-e83de6cf7b67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032951636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3032951636
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3846933545
Short name T131
Test name
Test status
Simulation time 502746200800 ps
CPU time 1600.02 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:36:15 PM PDT 24
Peak memory 262152 kb
Host smart-f037626e-ced5-4fff-8a1f-f431969adf68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846933545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.3846933545
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3773846752
Short name T84
Test name
Test status
Simulation time 858361300 ps
CPU time 65.57 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:55 PM PDT 24
Peak memory 259768 kb
Host smart-d6204120-a2ea-4839-a364-eacb9baddb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773846752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3773846752
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2549036809
Short name T134
Test name
Test status
Simulation time 159380360600 ps
CPU time 1093.54 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:27:48 PM PDT 24
Peak memory 259132 kb
Host smart-80df8e89-b10e-4736-a9c8-2f7018de6a95
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549036809 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2549036809
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.1968338369
Short name T54
Test name
Test status
Simulation time 400586500 ps
CPU time 25.35 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:10:52 PM PDT 24
Peak memory 264900 kb
Host smart-7b3bfbf8-f6c4-4290-8610-c2997197d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968338369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.1968338369
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1920354541
Short name T571
Test name
Test status
Simulation time 10012425300 ps
CPU time 127.43 seconds
Started May 30 01:12:17 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 350484 kb
Host smart-63b59d5e-d78a-4f86-8fdc-690643197b7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920354541 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1920354541
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.4156342917
Short name T344
Test name
Test status
Simulation time 556247400 ps
CPU time 169.27 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 292020 kb
Host smart-77b43054-74e0-47a0-ac74-c8a571c96b0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156342917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.4156342917
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1668826566
Short name T76
Test name
Test status
Simulation time 43915809700 ps
CPU time 280.95 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:18:13 PM PDT 24
Peak memory 292428 kb
Host smart-da2c6917-8e27-4d07-81fb-639b3ed7f181
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668826566 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1668826566
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1404441955
Short name T232
Test name
Test status
Simulation time 17746300 ps
CPU time 13.68 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 263872 kb
Host smart-7be52ad0-219d-44a1-8595-899c0b4b34ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404441955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1404441955
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3831216654
Short name T264
Test name
Test status
Simulation time 103341200 ps
CPU time 20.14 seconds
Started May 30 01:05:10 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 264144 kb
Host smart-b43e643a-e253-4f25-b348-bc7f50fe395e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831216654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3831216654
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3467209229
Short name T251
Test name
Test status
Simulation time 31042100 ps
CPU time 13.37 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:12 PM PDT 24
Peak memory 262528 kb
Host smart-76f9eca0-658c-4a42-8aba-14ced59e06dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467209229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
467209229
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3714613520
Short name T180
Test name
Test status
Simulation time 220070900 ps
CPU time 37.51 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:11:02 PM PDT 24
Peak memory 272996 kb
Host smart-e3b75696-1a20-45d4-b068-89c526455d1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714613520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3714613520
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.2463220642
Short name T22
Test name
Test status
Simulation time 178158900 ps
CPU time 15.85 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:09:50 PM PDT 24
Peak memory 264736 kb
Host smart-5f67b3dd-4cfd-443f-88c3-1e77e347f21a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463220642 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2463220642
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.421460776
Short name T360
Test name
Test status
Simulation time 687142000 ps
CPU time 894.11 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:20:18 PM PDT 24
Peak memory 264248 kb
Host smart-ac044d05-7c9c-44ec-9503-d9d7b16dbc46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421460776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.421460776
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.4057528186
Short name T77
Test name
Test status
Simulation time 11472057900 ps
CPU time 260.55 seconds
Started May 30 01:12:10 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 273756 kb
Host smart-ed041093-718c-4599-bf96-365db705092e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057528186 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.4057528186
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.713978891
Short name T155
Test name
Test status
Simulation time 6502965100 ps
CPU time 483.27 seconds
Started May 30 01:09:40 PM PDT 24
Finished May 30 01:17:43 PM PDT 24
Peak memory 306500 kb
Host smart-5668a369-87ee-48f2-8bd9-f3583d8213ee
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713978891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_rw.713978891
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.1671350185
Short name T135
Test name
Test status
Simulation time 12509400 ps
CPU time 21.91 seconds
Started May 30 01:11:16 PM PDT 24
Finished May 30 01:11:40 PM PDT 24
Peak memory 264964 kb
Host smart-c7b4759c-fec3-4280-b89a-307456e85106
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671350185 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.1671350185
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3438899145
Short name T90
Test name
Test status
Simulation time 910753100 ps
CPU time 16.05 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:09:50 PM PDT 24
Peak memory 261896 kb
Host smart-b1382b6b-a074-46bd-8ab3-59f54dd19a7f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438899145 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3438899145
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.4013896022
Short name T412
Test name
Test status
Simulation time 4724454500 ps
CPU time 149.38 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:13:17 PM PDT 24
Peak memory 259768 kb
Host smart-8284467f-b0a2-4e9c-bb01-2f5ebc02fb4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013896022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.4013896022
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4280891947
Short name T263
Test name
Test status
Simulation time 951488100 ps
CPU time 884.67 seconds
Started May 30 01:05:28 PM PDT 24
Finished May 30 01:20:13 PM PDT 24
Peak memory 261772 kb
Host smart-c23d4c25-0150-41b4-84a3-c4eb25fb213c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280891947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.4280891947
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.3596619450
Short name T331
Test name
Test status
Simulation time 1332346800 ps
CPU time 39.92 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:29 PM PDT 24
Peak memory 264796 kb
Host smart-f27a7514-4132-4f72-8fee-5f93a02f567f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596619450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.3596619450
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3755279063
Short name T65
Test name
Test status
Simulation time 45884600 ps
CPU time 14.07 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:09:49 PM PDT 24
Peak memory 276464 kb
Host smart-ed833298-f634-48a0-80b9-73bb19741410
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3755279063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3755279063
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.3049368661
Short name T190
Test name
Test status
Simulation time 9459135000 ps
CPU time 670.01 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:21:02 PM PDT 24
Peak memory 338896 kb
Host smart-86789ad6-8e2d-494f-8688-5b4138856634
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049368661 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.3049368661
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.4248543538
Short name T16
Test name
Test status
Simulation time 3318082100 ps
CPU time 4662.93 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 02:27:30 PM PDT 24
Peak memory 286896 kb
Host smart-2066aea0-2238-4ad4-b4c6-0535c8381857
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248543538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.4248543538
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2583154492
Short name T79
Test name
Test status
Simulation time 1863591000 ps
CPU time 60.96 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:12:04 PM PDT 24
Peak memory 259580 kb
Host smart-515248dd-a903-4f2b-8521-4269540abf42
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583154492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
583154492
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.739332689
Short name T291
Test name
Test status
Simulation time 194407800 ps
CPU time 17.22 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 264076 kb
Host smart-8d73b404-0ff3-41b4-adcc-0eaffd4f8c0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739332689 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.739332689
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2071913425
Short name T258
Test name
Test status
Simulation time 1328253300 ps
CPU time 759.17 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 261868 kb
Host smart-57316e75-5a7d-494b-bbb6-f81cf6e12816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071913425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2071913425
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3968901361
Short name T68
Test name
Test status
Simulation time 10014991100 ps
CPU time 80.32 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:13:16 PM PDT 24
Peak memory 265128 kb
Host smart-bee0e597-b075-4052-b26a-3c4f053ed8e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968901361 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3968901361
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.4207241150
Short name T712
Test name
Test status
Simulation time 15127400 ps
CPU time 13.71 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:29 PM PDT 24
Peak memory 264776 kb
Host smart-b850a070-a4e2-4713-972a-c72529b4f6c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207241150 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.4207241150
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1429153908
Short name T356
Test name
Test status
Simulation time 32532900 ps
CPU time 13.24 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:09:50 PM PDT 24
Peak memory 258928 kb
Host smart-d8fcb00e-1245-4e77-9dd1-db626fd371e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429153908 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1429153908
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.1147962850
Short name T171
Test name
Test status
Simulation time 24660400 ps
CPU time 13.15 seconds
Started May 30 01:14:28 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 274736 kb
Host smart-f4429917-a025-472f-a916-c46f85b5a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147962850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1147962850
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1684704488
Short name T265
Test name
Test status
Simulation time 47399200 ps
CPU time 13.24 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:10:05 PM PDT 24
Peak memory 257976 kb
Host smart-69513756-b3ed-4b47-bde6-a408cdc505e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684704488 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1684704488
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.6502654
Short name T48
Test name
Test status
Simulation time 2404596300 ps
CPU time 172.14 seconds
Started May 30 01:09:57 PM PDT 24
Finished May 30 01:12:50 PM PDT 24
Peak memory 281220 kb
Host smart-5dfee188-002d-4507-af7c-4b14c365f31f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6502654 -assert nopos
tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.6502654
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2141733769
Short name T266
Test name
Test status
Simulation time 82960000 ps
CPU time 78.02 seconds
Started May 30 01:09:34 PM PDT 24
Finished May 30 01:10:54 PM PDT 24
Peak memory 264776 kb
Host smart-a6f87a84-9366-4329-922f-6822c22fa8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141733769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2141733769
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.458473779
Short name T1032
Test name
Test status
Simulation time 735234900 ps
CPU time 1934.14 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:41:48 PM PDT 24
Peak memory 264620 kb
Host smart-afd145d3-f824-4f82-9659-f274a6ec4b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458473779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.458473779
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1539630847
Short name T205
Test name
Test status
Simulation time 114359400 ps
CPU time 30.94 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 274132 kb
Host smart-2a4dc79f-360d-4c70-a280-4e556a817158
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539630847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1539630847
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2254543557
Short name T144
Test name
Test status
Simulation time 160189086300 ps
CPU time 986.4 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:27:38 PM PDT 24
Peak memory 263020 kb
Host smart-dbc4cdd8-eebd-4911-af4a-768b2c33eda2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254543557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2254543557
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1930799160
Short name T140
Test name
Test status
Simulation time 30466200 ps
CPU time 22.08 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:40 PM PDT 24
Peak memory 273144 kb
Host smart-3c83e82c-15f4-444e-a9bd-ca84cde742c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930799160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1930799160
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2741211875
Short name T1155
Test name
Test status
Simulation time 18108600 ps
CPU time 13.31 seconds
Started May 30 01:05:28 PM PDT 24
Finished May 30 01:05:42 PM PDT 24
Peak memory 262692 kb
Host smart-eae9597a-9cf2-46cc-a2af-d2e235ca8f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741211875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
2741211875
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3757393427
Short name T396
Test name
Test status
Simulation time 21696936600 ps
CPU time 89.57 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:11:03 PM PDT 24
Peak memory 264712 kb
Host smart-708a5251-1bc1-409c-8c4a-93c41ff39b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757393427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3757393427
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.184097964
Short name T393
Test name
Test status
Simulation time 4438562300 ps
CPU time 65.6 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:12:05 PM PDT 24
Peak memory 262920 kb
Host smart-f08e0cd8-71ff-414f-b8ca-c31d3023c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184097964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.184097964
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2480433400
Short name T401
Test name
Test status
Simulation time 3969656800 ps
CPU time 63.75 seconds
Started May 30 01:12:17 PM PDT 24
Finished May 30 01:13:21 PM PDT 24
Peak memory 262340 kb
Host smart-05a29de3-a779-4abc-ae7b-b2b60f94212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480433400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2480433400
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3734075602
Short name T403
Test name
Test status
Simulation time 2422576900 ps
CPU time 65.58 seconds
Started May 30 01:12:17 PM PDT 24
Finished May 30 01:13:24 PM PDT 24
Peak memory 261776 kb
Host smart-5334078d-93c6-4903-a46a-925229b4fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734075602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3734075602
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.190875771
Short name T394
Test name
Test status
Simulation time 697426600 ps
CPU time 48.12 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 262320 kb
Host smart-4662a5e3-22b6-488a-a7b0-6b975db7d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190875771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.190875771
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2805218605
Short name T308
Test name
Test status
Simulation time 29008600 ps
CPU time 30.49 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:10:55 PM PDT 24
Peak memory 274332 kb
Host smart-d092360d-cb5e-4e71-84a3-ba3d86e70c63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805218605 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.2805218605
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3537667931
Short name T250
Test name
Test status
Simulation time 314016100 ps
CPU time 16.62 seconds
Started May 30 01:05:18 PM PDT 24
Finished May 30 01:05:36 PM PDT 24
Peak memory 264180 kb
Host smart-039371f8-8dde-4232-acb3-05c58f0511f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537667931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3
537667931
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.3986315051
Short name T41
Test name
Test status
Simulation time 337022000 ps
CPU time 39.95 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:37 PM PDT 24
Peak memory 264844 kb
Host smart-50487fae-2e00-4da6-bfd0-7cde2f82c26d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986315051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.3986315051
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3230066824
Short name T196
Test name
Test status
Simulation time 4566025700 ps
CPU time 555.14 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:20:01 PM PDT 24
Peak memory 311784 kb
Host smart-96c42ef4-7741-46c3-9bb5-21b3ae012a24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230066824 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.3230066824
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2819774333
Short name T215
Test name
Test status
Simulation time 4221082900 ps
CPU time 898.65 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 264196 kb
Host smart-4a6ef7f8-c3ee-461d-a58e-b5e11793eaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819774333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2819774333
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.453631399
Short name T1214
Test name
Test status
Simulation time 1364797500 ps
CPU time 456.87 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:12:47 PM PDT 24
Peak memory 264168 kb
Host smart-ae18dc03-ef79-401f-aa45-8de0ee013d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453631399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_tl_intg_err.453631399
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.2819686215
Short name T247
Test name
Test status
Simulation time 75037600 ps
CPU time 13.81 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:09:43 PM PDT 24
Peak memory 264848 kb
Host smart-093aa651-418e-41f9-ada4-221718acd463
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819686215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.2819686215
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.3252046430
Short name T415
Test name
Test status
Simulation time 121542400 ps
CPU time 105.18 seconds
Started May 30 01:09:39 PM PDT 24
Finished May 30 01:11:25 PM PDT 24
Peak memory 280368 kb
Host smart-a30cb957-8ea8-493a-8ed6-aeeafc1f9717
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252046430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.3252046430
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.905608727
Short name T1002
Test name
Test status
Simulation time 10011800 ps
CPU time 21.48 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:12:03 PM PDT 24
Peak memory 273040 kb
Host smart-f57b3c92-3436-47f9-9711-ef9bad75108b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905608727 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.905608727
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.2413862819
Short name T516
Test name
Test status
Simulation time 12797400 ps
CPU time 21.5 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 273232 kb
Host smart-ed0ccf9d-8a02-4b8f-ba0d-bdd050cce4e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413862819 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.2413862819
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2996819277
Short name T373
Test name
Test status
Simulation time 10360400 ps
CPU time 22.01 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:12:59 PM PDT 24
Peak memory 280340 kb
Host smart-33e8f150-e28a-46c0-8325-034975dd9bf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996819277 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2996819277
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1865825953
Short name T369
Test name
Test status
Simulation time 41781700 ps
CPU time 22.26 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:13:21 PM PDT 24
Peak memory 264904 kb
Host smart-6b8b1e88-d7af-4f80-b927-ca1368f004a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865825953 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1865825953
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2628041305
Short name T167
Test name
Test status
Simulation time 10619000 ps
CPU time 21.58 seconds
Started May 30 01:13:32 PM PDT 24
Finished May 30 01:13:56 PM PDT 24
Peak memory 273208 kb
Host smart-90ec118a-2f20-4c5a-9352-3cea6f223e2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628041305 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2628041305
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3055991539
Short name T536
Test name
Test status
Simulation time 2198633400 ps
CPU time 69.44 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:10:39 PM PDT 24
Peak memory 259156 kb
Host smart-9aeada85-5b8d-427e-b159-32d2482e3c0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055991539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3055991539
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.2495589635
Short name T92
Test name
Test status
Simulation time 875769400 ps
CPU time 18.06 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:10:20 PM PDT 24
Peak memory 264940 kb
Host smart-7686e13e-458a-4d53-9cd3-7d7bf8bcff57
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495589635 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2495589635
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1157309620
Short name T164
Test name
Test status
Simulation time 99483227000 ps
CPU time 386.85 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:16:13 PM PDT 24
Peak memory 292128 kb
Host smart-9000639f-b343-4685-9be4-072e5465973b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157309620 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.1157309620
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1508332237
Short name T153
Test name
Test status
Simulation time 25806800 ps
CPU time 13.98 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:03 PM PDT 24
Peak memory 260440 kb
Host smart-984c805b-40de-4e52-a086-043f85acb8cc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1508332237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1508332237
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2926471126
Short name T113
Test name
Test status
Simulation time 13068172700 ps
CPU time 2628.1 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:53:18 PM PDT 24
Peak memory 264868 kb
Host smart-3b346719-b433-4bca-b8ef-e73be70ce8bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926471126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2926471126
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1516214971
Short name T161
Test name
Test status
Simulation time 3443351900 ps
CPU time 883.79 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:24:21 PM PDT 24
Peak memory 264420 kb
Host smart-28b2a4d2-2731-4132-8e1b-f9c1b9f89026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516214971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1516214971
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1073284201
Short name T197
Test name
Test status
Simulation time 243418761800 ps
CPU time 2915.17 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:57:56 PM PDT 24
Peak memory 262108 kb
Host smart-9da6acf9-ad4f-4fe2-9f4e-debfedcc9006
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073284201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1073284201
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1334451544
Short name T200
Test name
Test status
Simulation time 501162422400 ps
CPU time 1700.99 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:38:25 PM PDT 24
Peak memory 264932 kb
Host smart-53838643-77aa-491b-9537-43113baabbcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334451544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1334451544
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2093828726
Short name T297
Test name
Test status
Simulation time 1672677700 ps
CPU time 39.12 seconds
Started May 30 01:04:55 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 260536 kb
Host smart-987bd0a2-88dc-47b3-9bab-61062e232de6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093828726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2093828726
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1267402941
Short name T1114
Test name
Test status
Simulation time 1243919600 ps
CPU time 43.01 seconds
Started May 30 01:04:54 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260456 kb
Host smart-f211f222-df9c-4b7e-8578-91d5f9865212
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267402941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1267402941
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1812732894
Short name T1118
Test name
Test status
Simulation time 31215800 ps
CPU time 38.33 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260608 kb
Host smart-ee95da38-e2ef-453c-8218-b23b9a04dcb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812732894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1812732894
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.915797268
Short name T1234
Test name
Test status
Simulation time 102292700 ps
CPU time 17.45 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:05:34 PM PDT 24
Peak memory 271716 kb
Host smart-dd6de29b-9909-4212-9be7-9c609ef650d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915797268 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.915797268
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1247595237
Short name T1127
Test name
Test status
Simulation time 18642500 ps
CPU time 16.71 seconds
Started May 30 01:05:01 PM PDT 24
Finished May 30 01:05:19 PM PDT 24
Peak memory 260476 kb
Host smart-6cce27e9-9b72-40cd-b701-9604083a128a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247595237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1247595237
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.486110429
Short name T1119
Test name
Test status
Simulation time 46821900 ps
CPU time 13.42 seconds
Started May 30 01:04:51 PM PDT 24
Finished May 30 01:05:05 PM PDT 24
Peak memory 262628 kb
Host smart-1b2488ab-dc08-4dd3-bc0f-79f8d38057e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486110429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.486110429
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.711780725
Short name T229
Test name
Test status
Simulation time 48366200 ps
CPU time 13.29 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:05:08 PM PDT 24
Peak memory 264076 kb
Host smart-1a1900f9-e8b8-4c3b-a4d3-ef46817bada2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711780725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.711780725
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1568935942
Short name T1167
Test name
Test status
Simulation time 44501100 ps
CPU time 13.38 seconds
Started May 30 01:04:48 PM PDT 24
Finished May 30 01:05:02 PM PDT 24
Peak memory 262816 kb
Host smart-b728ca31-fff7-4965-b51f-7dfec6ab406a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568935942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1568935942
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1961368867
Short name T1134
Test name
Test status
Simulation time 39118300 ps
CPU time 17.55 seconds
Started May 30 01:04:52 PM PDT 24
Finished May 30 01:05:11 PM PDT 24
Peak memory 260560 kb
Host smart-472690bf-8051-4929-b01c-a3ad4e41a85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961368867 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1961368867
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1922787063
Short name T1100
Test name
Test status
Simulation time 14859800 ps
CPU time 15.33 seconds
Started May 30 01:04:55 PM PDT 24
Finished May 30 01:05:11 PM PDT 24
Peak memory 260608 kb
Host smart-40cb0ee7-be7a-4477-8468-4fa742202165
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922787063 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1922787063
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4233147391
Short name T1135
Test name
Test status
Simulation time 14959500 ps
CPU time 15.57 seconds
Started May 30 01:05:01 PM PDT 24
Finished May 30 01:05:18 PM PDT 24
Peak memory 260608 kb
Host smart-1a5ebb06-fec2-47b9-a285-0fd8c75e5fc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233147391 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.4233147391
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3610688211
Short name T257
Test name
Test status
Simulation time 444712800 ps
CPU time 20.27 seconds
Started May 30 01:05:00 PM PDT 24
Finished May 30 01:05:22 PM PDT 24
Peak memory 264156 kb
Host smart-9f555ca6-7edb-49f6-a7e9-282c2520ccc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610688211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3
610688211
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2482677984
Short name T262
Test name
Test status
Simulation time 244446800 ps
CPU time 382.01 seconds
Started May 30 01:04:54 PM PDT 24
Finished May 30 01:11:18 PM PDT 24
Peak memory 264208 kb
Host smart-fab7189a-30b4-4711-a77d-9c1578cd10d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482677984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2482677984
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3119819629
Short name T417
Test name
Test status
Simulation time 867406200 ps
CPU time 31.08 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 260424 kb
Host smart-4758a887-14ec-41db-997d-793b7a571462
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119819629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3119819629
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.580202019
Short name T1113
Test name
Test status
Simulation time 2421503700 ps
CPU time 69.43 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:06:33 PM PDT 24
Peak memory 260608 kb
Host smart-a67c50a2-3750-4e02-ab4a-4f4d41a4fead
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580202019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_bit_bash.580202019
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4005637406
Short name T1105
Test name
Test status
Simulation time 125214600 ps
CPU time 46.97 seconds
Started May 30 01:04:55 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 260596 kb
Host smart-626dd250-48f3-44f3-bc47-93623583de53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005637406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.4005637406
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3593159273
Short name T1188
Test name
Test status
Simulation time 42490100 ps
CPU time 16.58 seconds
Started May 30 01:04:57 PM PDT 24
Finished May 30 01:05:15 PM PDT 24
Peak memory 280508 kb
Host smart-8bf1a0d3-e1d1-46ea-9e6a-799399bf37b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593159273 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3593159273
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.259122447
Short name T240
Test name
Test status
Simulation time 194660300 ps
CPU time 17.23 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 260496 kb
Host smart-53958727-4a22-4888-9f5e-b7331153ce6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259122447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_csr_rw.259122447
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.834320353
Short name T1149
Test name
Test status
Simulation time 15467300 ps
CPU time 13.54 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:05:11 PM PDT 24
Peak memory 262652 kb
Host smart-9867f4cb-6a3e-491a-a9e4-9cf4a678b5a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834320353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.834320353
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.887710131
Short name T296
Test name
Test status
Simulation time 108213800 ps
CPU time 18.22 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:19 PM PDT 24
Peak memory 260556 kb
Host smart-5ff4f72a-98ce-4d7e-9655-b4af00d929e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887710131 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.887710131
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.403521226
Short name T1182
Test name
Test status
Simulation time 33523400 ps
CPU time 13.46 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:20 PM PDT 24
Peak memory 260544 kb
Host smart-dfb384f3-4c54-41bb-aa2f-22f7f7537dbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403521226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.403521226
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.623687760
Short name T1103
Test name
Test status
Simulation time 34716800 ps
CPU time 15.43 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:16 PM PDT 24
Peak memory 260552 kb
Host smart-1c89587a-e7a6-4431-8ba2-cefcf502f8ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623687760 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.623687760
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3591942511
Short name T1123
Test name
Test status
Simulation time 29997200 ps
CPU time 15.22 seconds
Started May 30 01:04:48 PM PDT 24
Finished May 30 01:05:04 PM PDT 24
Peak memory 264148 kb
Host smart-0621026b-35ce-4434-b037-721a1b8d38a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591942511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
591942511
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1686459304
Short name T358
Test name
Test status
Simulation time 347601400 ps
CPU time 458.74 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:12:33 PM PDT 24
Peak memory 264120 kb
Host smart-e6f4bcbe-42e8-4b80-866c-6030228288ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686459304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1686459304
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1806256614
Short name T224
Test name
Test status
Simulation time 91916000 ps
CPU time 17.23 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 271524 kb
Host smart-627c077e-1ca1-408b-880e-6f46a294d168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806256614 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1806256614
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4088683465
Short name T1209
Test name
Test status
Simulation time 25475900 ps
CPU time 16.47 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 262780 kb
Host smart-b5d24c4d-cc99-413f-b9cd-9ea86e3130d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088683465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.4088683465
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1291235171
Short name T1139
Test name
Test status
Simulation time 47810400 ps
CPU time 13.28 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:14 PM PDT 24
Peak memory 262864 kb
Host smart-5657abad-05bb-4f5f-a0dd-37459d6bd799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291235171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1291235171
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.984143209
Short name T1153
Test name
Test status
Simulation time 88631000 ps
CPU time 18.13 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:28 PM PDT 24
Peak memory 261964 kb
Host smart-9a1a2534-e4ef-414b-9e68-e9886b6b8575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984143209 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.984143209
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2541834569
Short name T1208
Test name
Test status
Simulation time 50335300 ps
CPU time 15.45 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:05:28 PM PDT 24
Peak memory 260532 kb
Host smart-e5fe82ba-d49e-465a-bd3d-4a2a4030e485
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541834569 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2541834569
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1408509938
Short name T1215
Test name
Test status
Simulation time 14118300 ps
CPU time 15.78 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:28 PM PDT 24
Peak memory 260516 kb
Host smart-94482700-6088-43f7-a1d6-3a691da64cc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408509938 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1408509938
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1572403760
Short name T1190
Test name
Test status
Simulation time 36846400 ps
CPU time 15.94 seconds
Started May 30 01:05:13 PM PDT 24
Finished May 30 01:05:30 PM PDT 24
Peak memory 264136 kb
Host smart-22f93867-f24b-4cb5-af2c-386dae417e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572403760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1572403760
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1045575938
Short name T1198
Test name
Test status
Simulation time 1185625000 ps
CPU time 459.17 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:13:03 PM PDT 24
Peak memory 264016 kb
Host smart-b0354980-bec9-4e40-858e-4b7b2d5e245c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045575938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.1045575938
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3295511657
Short name T1228
Test name
Test status
Simulation time 88620800 ps
CPU time 16.68 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 270532 kb
Host smart-9cb011b4-3853-406c-9ded-4c5fefb153b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295511657 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3295511657
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1991840317
Short name T286
Test name
Test status
Simulation time 130035200 ps
CPU time 14.79 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:40 PM PDT 24
Peak memory 260492 kb
Host smart-7398ef34-550d-4cf1-af46-ddd1aa635344
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991840317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1991840317
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.100932610
Short name T1111
Test name
Test status
Simulation time 23892800 ps
CPU time 13.44 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:18 PM PDT 24
Peak memory 262720 kb
Host smart-9042562a-2bb7-4cef-8d92-627ed9bd33b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100932610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.100932610
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1839799372
Short name T1212
Test name
Test status
Simulation time 522798700 ps
CPU time 19.1 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:20 PM PDT 24
Peak memory 262376 kb
Host smart-549d1048-0aca-4d29-aa3b-1883dacfd0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839799372 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1839799372
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4938892
Short name T1130
Test name
Test status
Simulation time 12346200 ps
CPU time 15.35 seconds
Started May 30 01:05:18 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 260572 kb
Host smart-e43b5a71-f9cc-4402-b5da-860085202fc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4938892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ba
se_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.4938892
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2887464534
Short name T1199
Test name
Test status
Simulation time 21710700 ps
CPU time 15.42 seconds
Started May 30 01:05:07 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 260580 kb
Host smart-7313104c-f1b2-4869-9dc1-b2e33bc10da7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887464534 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2887464534
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3117068404
Short name T1225
Test name
Test status
Simulation time 36956300 ps
CPU time 16.14 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 264212 kb
Host smart-b9fd0fb5-3fa0-4ce3-b611-e2f52756dc53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117068404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
3117068404
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3211981765
Short name T1230
Test name
Test status
Simulation time 209327400 ps
CPU time 14.65 seconds
Started May 30 01:05:22 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 270528 kb
Host smart-35d36530-428b-4f06-a2fe-7a0db83a079e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211981765 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3211981765
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.459272895
Short name T1120
Test name
Test status
Simulation time 50845300 ps
CPU time 17.2 seconds
Started May 30 01:05:19 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 260528 kb
Host smart-dd1c6c36-a000-4c7f-b2f1-517d6f9088d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459272895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_csr_rw.459272895
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.924316978
Short name T1145
Test name
Test status
Simulation time 55028300 ps
CPU time 13.49 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:14 PM PDT 24
Peak memory 262948 kb
Host smart-7cd6a9f7-77f3-4ece-bbb6-1b02b5171bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924316978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.924316978
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.620565224
Short name T294
Test name
Test status
Simulation time 538116300 ps
CPU time 19.51 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 260660 kb
Host smart-d789f453-cdfb-4f75-9d66-ab7a637c18f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620565224 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.620565224
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1561533834
Short name T1116
Test name
Test status
Simulation time 24774700 ps
CPU time 15.49 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:15 PM PDT 24
Peak memory 260612 kb
Host smart-d6e87211-fa27-47f2-b53e-1c9af78243e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561533834 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1561533834
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2586902373
Short name T1204
Test name
Test status
Simulation time 34769000 ps
CPU time 15.66 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:05:13 PM PDT 24
Peak memory 260552 kb
Host smart-399b5b36-4ddb-4401-94ac-8f619b33706f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586902373 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2586902373
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3370797511
Short name T256
Test name
Test status
Simulation time 62423900 ps
CPU time 18.47 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:45 PM PDT 24
Peak memory 264200 kb
Host smart-2b2f6b30-c62d-4d18-9f94-eb5e6ba8bdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370797511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3370797511
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.587520860
Short name T1137
Test name
Test status
Simulation time 41141700 ps
CPU time 17.18 seconds
Started May 30 01:05:03 PM PDT 24
Finished May 30 01:05:22 PM PDT 24
Peak memory 272352 kb
Host smart-9f7d1e6a-3cc2-4f2a-89bf-b4b37bc418d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587520860 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.587520860
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1619384283
Short name T73
Test name
Test status
Simulation time 123612300 ps
CPU time 16.58 seconds
Started May 30 01:05:38 PM PDT 24
Finished May 30 01:05:55 PM PDT 24
Peak memory 260564 kb
Host smart-93eb0d53-e17b-4aeb-993f-052c20f58710
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619384283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.1619384283
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.141966599
Short name T1219
Test name
Test status
Simulation time 42782400 ps
CPU time 13.59 seconds
Started May 30 01:05:18 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 262624 kb
Host smart-e091b437-96dc-4706-acf3-7b883d238044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141966599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.141966599
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1635879887
Short name T1133
Test name
Test status
Simulation time 63395300 ps
CPU time 33.19 seconds
Started May 30 01:05:18 PM PDT 24
Finished May 30 01:05:52 PM PDT 24
Peak memory 262184 kb
Host smart-034ae787-6cb1-4945-991b-d0b74a111950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635879887 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1635879887
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3371180953
Short name T1132
Test name
Test status
Simulation time 18060100 ps
CPU time 16.12 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:23 PM PDT 24
Peak memory 260408 kb
Host smart-fc465018-b61b-48cf-b3b0-9e5c91641e75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371180953 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3371180953
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2931731937
Short name T1097
Test name
Test status
Simulation time 33415700 ps
CPU time 15.53 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 260512 kb
Host smart-1d3371a4-0476-4b3f-bbf6-cfcc05d1e869
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931731937 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.2931731937
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3693157081
Short name T261
Test name
Test status
Simulation time 176818300 ps
CPU time 19.96 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 280296 kb
Host smart-3c70c74b-f0cc-4727-b42a-3c03780d8fe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693157081 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3693157081
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.235412243
Short name T1176
Test name
Test status
Simulation time 469726200 ps
CPU time 17.58 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 264068 kb
Host smart-7dd54192-3e54-4d7d-855e-39bb9744871e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235412243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_csr_rw.235412243
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2837447570
Short name T1174
Test name
Test status
Simulation time 67254000 ps
CPU time 33.94 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 260636 kb
Host smart-d5d2543a-3b67-4489-8b84-abb67e5a489f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837447570 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2837447570
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1530996796
Short name T1096
Test name
Test status
Simulation time 66313100 ps
CPU time 15.27 seconds
Started May 30 01:05:10 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 260592 kb
Host smart-61872ed6-2d95-4ffe-b44c-f29e04d1a7d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530996796 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1530996796
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.462468296
Short name T1106
Test name
Test status
Simulation time 14026300 ps
CPU time 13.06 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 260472 kb
Host smart-4b45904a-4d42-4ec1-9560-a65e515f1f71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462468296 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.462468296
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1898201519
Short name T216
Test name
Test status
Simulation time 395653200 ps
CPU time 18.6 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 264128 kb
Host smart-3e562cbe-a468-4491-9e5a-847cbc9e5ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898201519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1898201519
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2131415308
Short name T287
Test name
Test status
Simulation time 207070200 ps
CPU time 19.18 seconds
Started May 30 01:05:25 PM PDT 24
Finished May 30 01:05:45 PM PDT 24
Peak memory 278632 kb
Host smart-db63c87a-e2f7-4789-9d6a-51a7020f3089
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131415308 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2131415308
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.826367281
Short name T1121
Test name
Test status
Simulation time 337255300 ps
CPU time 14.73 seconds
Started May 30 01:05:13 PM PDT 24
Finished May 30 01:05:28 PM PDT 24
Peak memory 260484 kb
Host smart-5b663204-5324-42a5-a79c-48feaf57aee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826367281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.826367281
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1716087809
Short name T1173
Test name
Test status
Simulation time 15624500 ps
CPU time 13.7 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 262664 kb
Host smart-eee00031-a4e8-48f3-93b8-d986a0d2de28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716087809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
1716087809
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1906767021
Short name T1164
Test name
Test status
Simulation time 324813900 ps
CPU time 35.34 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:56 PM PDT 24
Peak memory 262500 kb
Host smart-2ba40fbb-9407-45e5-b567-7ab0ac414dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906767021 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1906767021
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1702020427
Short name T1098
Test name
Test status
Simulation time 25844500 ps
CPU time 15.67 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 260496 kb
Host smart-659a2067-9793-49ef-ab1c-09db41367de9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702020427 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.1702020427
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3946006994
Short name T1099
Test name
Test status
Simulation time 29132100 ps
CPU time 16.44 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 260544 kb
Host smart-5f18e3f5-74d3-4a58-a726-051044844624
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946006994 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3946006994
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.927693170
Short name T361
Test name
Test status
Simulation time 368276100 ps
CPU time 458.24 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:12:54 PM PDT 24
Peak memory 264216 kb
Host smart-eb52a782-6a38-45f3-847c-d644a9640998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927693170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.927693170
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1511529908
Short name T170
Test name
Test status
Simulation time 604522900 ps
CPU time 17.37 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 264196 kb
Host smart-7719153a-91c3-4994-8ce9-68bd6a473e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511529908 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1511529908
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2595681108
Short name T1150
Test name
Test status
Simulation time 28686700 ps
CPU time 14.35 seconds
Started May 30 01:05:22 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 260524 kb
Host smart-69f41f54-644b-4580-9cb5-acaf376c7300
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595681108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.2595681108
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2880596399
Short name T1107
Test name
Test status
Simulation time 137330200 ps
CPU time 17.13 seconds
Started May 30 01:05:33 PM PDT 24
Finished May 30 01:05:51 PM PDT 24
Peak memory 260672 kb
Host smart-6d588e8c-717c-409b-bcbd-4c6c4a5ff6ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880596399 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2880596399
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2697634954
Short name T1197
Test name
Test status
Simulation time 20456400 ps
CPU time 13.6 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:41 PM PDT 24
Peak memory 260484 kb
Host smart-b8e318df-74a7-4321-a43a-970dd106bb3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697634954 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2697634954
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2689360674
Short name T1138
Test name
Test status
Simulation time 44570300 ps
CPU time 16.01 seconds
Started May 30 01:05:16 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 260580 kb
Host smart-2a2de839-68af-4982-838a-0c8263880857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689360674 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2689360674
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2557764548
Short name T1218
Test name
Test status
Simulation time 79995700 ps
CPU time 16.52 seconds
Started May 30 01:05:05 PM PDT 24
Finished May 30 01:05:22 PM PDT 24
Peak memory 264192 kb
Host smart-62884d6a-d621-4e99-b74a-a706c3ab5f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557764548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2557764548
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.842437554
Short name T222
Test name
Test status
Simulation time 49836400 ps
CPU time 19.3 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:46 PM PDT 24
Peak memory 272376 kb
Host smart-e695667f-b1b2-4524-9177-20a4f579a8c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842437554 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.842437554
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3484379011
Short name T1147
Test name
Test status
Simulation time 55642400 ps
CPU time 14.56 seconds
Started May 30 01:05:16 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 260556 kb
Host smart-f2578b17-e604-4a88-8c74-c2fa054bc525
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484379011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.3484379011
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2770109970
Short name T1201
Test name
Test status
Simulation time 27528800 ps
CPU time 13.85 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 262532 kb
Host smart-d711e256-ebc6-4a05-8fbc-6f499fe5cffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770109970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2770109970
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2846513669
Short name T1110
Test name
Test status
Simulation time 61876500 ps
CPU time 18.93 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260640 kb
Host smart-7d1b1a09-970a-4e18-ac36-ef43fc2d19f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846513669 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2846513669
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.188821037
Short name T1202
Test name
Test status
Simulation time 22355700 ps
CPU time 15.43 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:40 PM PDT 24
Peak memory 260492 kb
Host smart-aff74d3b-f9cc-44e7-aa97-d30e46a8d71e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188821037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.188821037
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1616302767
Short name T1142
Test name
Test status
Simulation time 20182900 ps
CPU time 13.29 seconds
Started May 30 01:05:13 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 260516 kb
Host smart-036b174d-9261-459b-8b2b-d15ea6c1e489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616302767 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1616302767
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3101884367
Short name T1194
Test name
Test status
Simulation time 146565200 ps
CPU time 16.65 seconds
Started May 30 01:05:16 PM PDT 24
Finished May 30 01:05:33 PM PDT 24
Peak memory 264128 kb
Host smart-984dda5b-fb86-40df-ac41-7b95207e6e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101884367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
3101884367
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2809693074
Short name T363
Test name
Test status
Simulation time 2762818500 ps
CPU time 897.58 seconds
Started May 30 01:05:37 PM PDT 24
Finished May 30 01:20:36 PM PDT 24
Peak memory 264168 kb
Host smart-90ff056c-7796-4ec5-bfd0-4899e0a27cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809693074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.2809693074
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.893882686
Short name T214
Test name
Test status
Simulation time 312877000 ps
CPU time 16.51 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 270724 kb
Host smart-68760e28-5011-4765-82c7-5811fd5899c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893882686 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.893882686
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.869614489
Short name T1166
Test name
Test status
Simulation time 99907500 ps
CPU time 16.8 seconds
Started May 30 01:05:35 PM PDT 24
Finished May 30 01:05:52 PM PDT 24
Peak memory 260460 kb
Host smart-2f325e9d-702e-4ab4-a0d4-6b76325759bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869614489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_csr_rw.869614489
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3258365228
Short name T1168
Test name
Test status
Simulation time 15669500 ps
CPU time 13.49 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 261792 kb
Host smart-e5ab0028-db14-482c-8ba7-c276a2fc1412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258365228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3258365228
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1798339008
Short name T1205
Test name
Test status
Simulation time 35932600 ps
CPU time 17.63 seconds
Started May 30 01:05:18 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 260600 kb
Host smart-b3d69d3c-6586-47ab-9ca8-b52c0e0f2cb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798339008 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1798339008
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1073615104
Short name T1180
Test name
Test status
Simulation time 88039500 ps
CPU time 13.58 seconds
Started May 30 01:05:28 PM PDT 24
Finished May 30 01:05:42 PM PDT 24
Peak memory 260496 kb
Host smart-bf9ad221-6167-412a-9ba5-b92136c0c17d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073615104 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1073615104
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3848216537
Short name T1156
Test name
Test status
Simulation time 122935200 ps
CPU time 15.76 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 260552 kb
Host smart-0466614d-4a1c-4d3c-a869-b81b4d0abcb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848216537 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3848216537
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4290641724
Short name T1177
Test name
Test status
Simulation time 35469500 ps
CPU time 17.02 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:05:30 PM PDT 24
Peak memory 264124 kb
Host smart-71246477-8077-42a8-861a-99f17e0ee603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290641724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
4290641724
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.375680853
Short name T1191
Test name
Test status
Simulation time 1303200700 ps
CPU time 752.96 seconds
Started May 30 01:05:21 PM PDT 24
Finished May 30 01:17:55 PM PDT 24
Peak memory 264160 kb
Host smart-d6e38e32-2261-40b7-a6b4-78d04756f80e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375680853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_tl_intg_err.375680853
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2525161179
Short name T295
Test name
Test status
Simulation time 239875800 ps
CPU time 16.79 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:41 PM PDT 24
Peak memory 270720 kb
Host smart-c0aea332-3355-452c-86ad-d3278baab8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525161179 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2525161179
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3396037110
Short name T1203
Test name
Test status
Simulation time 209797500 ps
CPU time 17.54 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 260620 kb
Host smart-74eaaa96-95ab-4753-aef1-e5f4c942c822
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396037110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3396037110
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.348860937
Short name T1185
Test name
Test status
Simulation time 24756500 ps
CPU time 13.36 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 262800 kb
Host smart-74175f4a-1987-4f64-806e-42b19f93ae54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348860937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.348860937
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4074245579
Short name T1226
Test name
Test status
Simulation time 119634600 ps
CPU time 19.36 seconds
Started May 30 01:05:30 PM PDT 24
Finished May 30 01:05:50 PM PDT 24
Peak memory 262768 kb
Host smart-05e1b613-b4b9-45f5-b751-012dd8ea8370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074245579 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.4074245579
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.613052873
Short name T1213
Test name
Test status
Simulation time 19867400 ps
CPU time 15.67 seconds
Started May 30 01:05:22 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260524 kb
Host smart-17b82d7d-6452-45be-9496-4893460418fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613052873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.613052873
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.497412654
Short name T1224
Test name
Test status
Simulation time 12383200 ps
CPU time 15.44 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:42 PM PDT 24
Peak memory 260592 kb
Host smart-9b44ee34-b9c4-4345-a0a7-cabe029ce446
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497412654 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.497412654
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3186378670
Short name T248
Test name
Test status
Simulation time 37613300 ps
CPU time 16.2 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 264192 kb
Host smart-5c564791-f95a-49e9-998d-645f253de6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186378670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3186378670
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1016654764
Short name T416
Test name
Test status
Simulation time 642758000 ps
CPU time 36.11 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:46 PM PDT 24
Peak memory 260536 kb
Host smart-99fa5244-7e64-483a-a5d9-c7ae8b5295aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016654764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.1016654764
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2247868712
Short name T293
Test name
Test status
Simulation time 2843544200 ps
CPU time 71.36 seconds
Started May 30 01:05:00 PM PDT 24
Finished May 30 01:06:13 PM PDT 24
Peak memory 260504 kb
Host smart-1e87cc56-309c-42b0-b45e-cb6eb23de5d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247868712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.2247868712
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3314673572
Short name T1193
Test name
Test status
Simulation time 103689100 ps
CPU time 30.55 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:05:28 PM PDT 24
Peak memory 260600 kb
Host smart-3aa5509b-dc5e-454a-a75e-ccd79299cf3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314673572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3314673572
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2002988983
Short name T226
Test name
Test status
Simulation time 99250200 ps
CPU time 17.5 seconds
Started May 30 01:05:01 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 270544 kb
Host smart-6b617bdf-09e3-4da5-883e-d44a21db1f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002988983 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2002988983
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4280192027
Short name T1178
Test name
Test status
Simulation time 62359000 ps
CPU time 16.2 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:05:10 PM PDT 24
Peak memory 260504 kb
Host smart-aeccea55-7ecf-4fbd-b4a2-9ef05f85379f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280192027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.4280192027
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1438914344
Short name T1124
Test name
Test status
Simulation time 49742200 ps
CPU time 14.23 seconds
Started May 30 01:05:16 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 262648 kb
Host smart-5c8cc6a6-5d28-40ba-8fae-a8388c75e95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438914344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1
438914344
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2483265333
Short name T230
Test name
Test status
Simulation time 49374200 ps
CPU time 13.38 seconds
Started May 30 01:05:10 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 264120 kb
Host smart-07ce1719-9a12-4f42-b01f-0ab968b9477c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483265333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2483265333
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.116422628
Short name T1115
Test name
Test status
Simulation time 169733000 ps
CPU time 13.21 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:05:07 PM PDT 24
Peak memory 262724 kb
Host smart-4537ea6e-1041-4033-a44d-c912c22a0785
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116422628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.116422628
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2054558771
Short name T1129
Test name
Test status
Simulation time 231958500 ps
CPU time 19.08 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:05:13 PM PDT 24
Peak memory 262072 kb
Host smart-54d548b4-a686-4815-b504-94a7d963925e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054558771 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2054558771
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2858928714
Short name T1179
Test name
Test status
Simulation time 24164400 ps
CPU time 15.34 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 260564 kb
Host smart-20f08fec-6aca-4612-85f0-14e4d2e28db5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858928714 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2858928714
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.203545629
Short name T1108
Test name
Test status
Simulation time 13338200 ps
CPU time 13.17 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 260612 kb
Host smart-fa372502-7a7b-42f7-964c-2ac5601960ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203545629 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.203545629
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3635419440
Short name T1211
Test name
Test status
Simulation time 65299000 ps
CPU time 16.61 seconds
Started May 30 01:04:53 PM PDT 24
Finished May 30 01:05:11 PM PDT 24
Peak memory 264200 kb
Host smart-f88eb3e4-6923-4334-8957-6da507134999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635419440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
635419440
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1232094386
Short name T1222
Test name
Test status
Simulation time 48143800 ps
CPU time 13.44 seconds
Started May 30 01:05:16 PM PDT 24
Finished May 30 01:05:30 PM PDT 24
Peak memory 262632 kb
Host smart-fb18a18d-5df3-4162-be9f-e541175f275b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232094386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1232094386
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.750928165
Short name T338
Test name
Test status
Simulation time 18113300 ps
CPU time 13.44 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 262840 kb
Host smart-55e54b50-2059-42ee-9eba-e93cd5b844d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750928165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.750928165
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3535028424
Short name T337
Test name
Test status
Simulation time 80023000 ps
CPU time 13.88 seconds
Started May 30 01:05:36 PM PDT 24
Finished May 30 01:05:50 PM PDT 24
Peak memory 262776 kb
Host smart-7880e936-770b-499e-8ac1-a60603b7ee09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535028424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3535028424
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2800339421
Short name T1232
Test name
Test status
Simulation time 27673100 ps
CPU time 13.18 seconds
Started May 30 01:05:25 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 262852 kb
Host smart-c9552dab-1a80-4913-bd3b-10ff1e233b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800339421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2800339421
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2313240465
Short name T1158
Test name
Test status
Simulation time 133359100 ps
CPU time 13.57 seconds
Started May 30 01:05:21 PM PDT 24
Finished May 30 01:05:36 PM PDT 24
Peak memory 262660 kb
Host smart-2cd3e02c-2a11-40d4-b417-42cf5595c42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313240465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2313240465
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.764689332
Short name T1183
Test name
Test status
Simulation time 114672200 ps
CPU time 13.57 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 262952 kb
Host smart-5905d654-b332-43d4-b789-dc31b4b54c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764689332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.764689332
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2814945462
Short name T1112
Test name
Test status
Simulation time 55262400 ps
CPU time 13.37 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 262772 kb
Host smart-bc03634c-1412-4359-a68c-fa96bdc05748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814945462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2814945462
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2683147489
Short name T339
Test name
Test status
Simulation time 16513200 ps
CPU time 13.26 seconds
Started May 30 01:05:24 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 262672 kb
Host smart-a7742664-f352-4822-9b66-76e697de2073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683147489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
2683147489
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2083865703
Short name T1196
Test name
Test status
Simulation time 15404600 ps
CPU time 13.69 seconds
Started May 30 01:05:29 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 262580 kb
Host smart-e634ad33-d887-49a3-b913-d6289d5643f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083865703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
2083865703
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.137679765
Short name T1236
Test name
Test status
Simulation time 16334600 ps
CPU time 13.44 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:34 PM PDT 24
Peak memory 262896 kb
Host smart-c6121e5f-a005-4a38-8786-0ae3f107b018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137679765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.137679765
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3099127878
Short name T1126
Test name
Test status
Simulation time 1804839100 ps
CPU time 53.95 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:54 PM PDT 24
Peak memory 260588 kb
Host smart-ee85b359-7da7-47cf-bb33-e951dca736f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099127878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.3099127878
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2436769991
Short name T1160
Test name
Test status
Simulation time 6391022200 ps
CPU time 43.71 seconds
Started May 30 01:04:54 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 262232 kb
Host smart-3684d971-7d2c-4a84-a3c3-907e40f2d00a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436769991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.2436769991
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3110868233
Short name T1104
Test name
Test status
Simulation time 31070700 ps
CPU time 30.83 seconds
Started May 30 01:05:07 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260504 kb
Host smart-e5651c96-8afe-4a14-9f8a-01d0b3cc25d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110868233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3110868233
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1664409393
Short name T1229
Test name
Test status
Simulation time 89804700 ps
CPU time 17.43 seconds
Started May 30 01:04:57 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 264176 kb
Host smart-7d9d34dd-778a-4dad-92f0-b834f5269184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664409393 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1664409393
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1927417422
Short name T1189
Test name
Test status
Simulation time 21749700 ps
CPU time 16.78 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:20 PM PDT 24
Peak memory 260468 kb
Host smart-85bbd79d-a92f-4d49-982d-c8fcb716459e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927417422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1927417422
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.783594969
Short name T253
Test name
Test status
Simulation time 49473400 ps
CPU time 13.31 seconds
Started May 30 01:04:54 PM PDT 24
Finished May 30 01:05:08 PM PDT 24
Peak memory 262876 kb
Host smart-367364b2-f146-4067-9f76-ba8969742316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783594969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.783594969
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4152652994
Short name T231
Test name
Test status
Simulation time 17626800 ps
CPU time 13.47 seconds
Started May 30 01:05:04 PM PDT 24
Finished May 30 01:05:19 PM PDT 24
Peak memory 263760 kb
Host smart-dd2d7320-4e54-4d88-aef2-11a9938f92da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152652994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.4152652994
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4091601639
Short name T1148
Test name
Test status
Simulation time 53613700 ps
CPU time 13.63 seconds
Started May 30 01:05:19 PM PDT 24
Finished May 30 01:05:33 PM PDT 24
Peak memory 262720 kb
Host smart-02ac844e-c8be-4541-a2e4-62c01b9b1e22
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091601639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.4091601639
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.426722435
Short name T1109
Test name
Test status
Simulation time 1428460500 ps
CPU time 20.51 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 260584 kb
Host smart-cd9d9da0-d036-4458-abd1-5d734858c790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426722435 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.426722435
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1780339989
Short name T1101
Test name
Test status
Simulation time 14062900 ps
CPU time 13.13 seconds
Started May 30 01:05:13 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 260492 kb
Host smart-4e931953-23b2-456f-acf2-27ca8ad09471
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780339989 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1780339989
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1350099357
Short name T1102
Test name
Test status
Simulation time 14920100 ps
CPU time 15.27 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 260612 kb
Host smart-b4004a69-c9ff-4c30-9e39-a9089648c35f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350099357 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.1350099357
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3174168894
Short name T362
Test name
Test status
Simulation time 2104879300 ps
CPU time 460.49 seconds
Started May 30 01:04:52 PM PDT 24
Finished May 30 01:12:34 PM PDT 24
Peak memory 264116 kb
Host smart-d8c4fee7-5445-4432-a262-6d7ff2c37d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174168894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3174168894
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.342827586
Short name T336
Test name
Test status
Simulation time 16475000 ps
CPU time 13.39 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 262848 kb
Host smart-9853a0a5-126b-4412-8b9e-8e0c99d8608e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342827586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.342827586
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1669620346
Short name T335
Test name
Test status
Simulation time 31900100 ps
CPU time 13.46 seconds
Started May 30 01:05:21 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 262804 kb
Host smart-3e5c3d80-93f6-4b02-a798-692a7cdc9e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669620346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1669620346
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3886280476
Short name T1175
Test name
Test status
Simulation time 56832100 ps
CPU time 13.48 seconds
Started May 30 01:05:21 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 262984 kb
Host smart-5cf863fe-6fc5-4b27-ac2f-ad7dcdd112b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886280476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3886280476
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1841345554
Short name T341
Test name
Test status
Simulation time 24541000 ps
CPU time 13.47 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:36 PM PDT 24
Peak memory 262676 kb
Host smart-6588fb49-9105-4389-ad34-6f5fc3ed1d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841345554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1841345554
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4205908801
Short name T1161
Test name
Test status
Simulation time 53743900 ps
CPU time 13.27 seconds
Started May 30 01:05:29 PM PDT 24
Finished May 30 01:05:43 PM PDT 24
Peak memory 262576 kb
Host smart-9f3870f6-f32f-45cd-9116-2b295c47f5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205908801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
4205908801
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2060931840
Short name T1195
Test name
Test status
Simulation time 137282400 ps
CPU time 13.69 seconds
Started May 30 01:05:32 PM PDT 24
Finished May 30 01:05:46 PM PDT 24
Peak memory 262980 kb
Host smart-e3419d47-4c8a-49a6-a7d0-10ea4c98c379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060931840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
2060931840
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3529384825
Short name T1141
Test name
Test status
Simulation time 74979100 ps
CPU time 13.51 seconds
Started May 30 01:05:45 PM PDT 24
Finished May 30 01:05:59 PM PDT 24
Peak memory 262644 kb
Host smart-a83b4c38-93ac-4167-9689-1ebd9d42b408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529384825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3529384825
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1875787181
Short name T1136
Test name
Test status
Simulation time 17929300 ps
CPU time 13.72 seconds
Started May 30 01:05:21 PM PDT 24
Finished May 30 01:05:36 PM PDT 24
Peak memory 262704 kb
Host smart-7041818e-be9a-4969-a1a5-9ad87cffac03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875787181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1875787181
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1802797253
Short name T1235
Test name
Test status
Simulation time 26385000 ps
CPU time 13.59 seconds
Started May 30 01:05:30 PM PDT 24
Finished May 30 01:05:45 PM PDT 24
Peak memory 262632 kb
Host smart-ae51bb1c-f005-4c0a-9e24-4e39c39bd27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802797253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1802797253
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2453955246
Short name T1233
Test name
Test status
Simulation time 35046900 ps
CPU time 13.89 seconds
Started May 30 01:05:30 PM PDT 24
Finished May 30 01:05:45 PM PDT 24
Peak memory 262504 kb
Host smart-cf9370fb-b68f-4d0c-ba7f-38f8562ff2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453955246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2453955246
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4126543920
Short name T1152
Test name
Test status
Simulation time 446989000 ps
CPU time 31.3 seconds
Started May 30 01:05:07 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260484 kb
Host smart-b2c892a4-d936-49ea-a0c1-65037e42b241
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126543920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.4126543920
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2776028477
Short name T290
Test name
Test status
Simulation time 1463963700 ps
CPU time 45.82 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:53 PM PDT 24
Peak memory 262492 kb
Host smart-0a616187-41ab-4632-acce-5a0e6116a190
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776028477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2776028477
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1427874013
Short name T289
Test name
Test status
Simulation time 314285600 ps
CPU time 39.29 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260564 kb
Host smart-004b31d6-31e8-441f-976e-6958089f3268
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427874013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1427874013
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.513815574
Short name T288
Test name
Test status
Simulation time 43717900 ps
CPU time 14.72 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:39 PM PDT 24
Peak memory 260508 kb
Host smart-325a1d01-1d81-4aec-94a8-a0cb1d05fa3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513815574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.513815574
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2866983599
Short name T1162
Test name
Test status
Simulation time 15860000 ps
CPU time 13.35 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 262688 kb
Host smart-ddafd7da-dc1b-4ceb-890e-3fa919f65ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866983599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
866983599
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3632160028
Short name T228
Test name
Test status
Simulation time 34988300 ps
CPU time 13.85 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 263756 kb
Host smart-fb80fc49-80d2-4b21-aae0-9c2575e570a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632160028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.3632160028
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.321271082
Short name T1159
Test name
Test status
Simulation time 42691300 ps
CPU time 13.41 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 262816 kb
Host smart-e081befc-a7b7-4e39-9ea3-8e3b217ba469
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321271082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.321271082
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.226245021
Short name T1210
Test name
Test status
Simulation time 73293400 ps
CPU time 17.24 seconds
Started May 30 01:05:00 PM PDT 24
Finished May 30 01:05:19 PM PDT 24
Peak memory 262972 kb
Host smart-73a55046-4195-4ab7-84db-fa23a94ad53a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226245021 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.226245021
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2265721938
Short name T1170
Test name
Test status
Simulation time 14071200 ps
CPU time 13.13 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 260472 kb
Host smart-9656aa79-afad-4269-860c-0c6ce76b964f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265721938 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2265721938
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2712471302
Short name T1157
Test name
Test status
Simulation time 15059500 ps
CPU time 13.25 seconds
Started May 30 01:04:57 PM PDT 24
Finished May 30 01:05:12 PM PDT 24
Peak memory 260616 kb
Host smart-11613e08-ae1d-4222-9f73-0bcfed0fe6d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712471302 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.2712471302
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3952518147
Short name T169
Test name
Test status
Simulation time 55600600 ps
CPU time 18.56 seconds
Started May 30 01:04:57 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 264156 kb
Host smart-e27870b8-a522-4de9-83b1-e2182fe1c258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952518147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3
952518147
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1021265355
Short name T285
Test name
Test status
Simulation time 826711600 ps
CPU time 389.77 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:11:37 PM PDT 24
Peak memory 264160 kb
Host smart-320766b6-00df-4344-bd5c-768ff85c5583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021265355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1021265355
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2156749989
Short name T1169
Test name
Test status
Simulation time 17000800 ps
CPU time 13.43 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:05:30 PM PDT 24
Peak memory 262900 kb
Host smart-03cc3d25-0f47-47e4-b2a0-013d2a4563fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156749989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2156749989
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3221429524
Short name T1186
Test name
Test status
Simulation time 27026300 ps
CPU time 13.67 seconds
Started May 30 01:05:26 PM PDT 24
Finished May 30 01:05:40 PM PDT 24
Peak memory 262892 kb
Host smart-a9841bc3-6f3a-4464-aa85-5d2d4e54bfb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221429524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3221429524
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3905395349
Short name T252
Test name
Test status
Simulation time 24216000 ps
CPU time 13.59 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:32 PM PDT 24
Peak memory 262784 kb
Host smart-76eeb483-1ca6-4d15-ac17-3e1a3df9cca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905395349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3905395349
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2329373798
Short name T1151
Test name
Test status
Simulation time 30903200 ps
CPU time 13.37 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 262884 kb
Host smart-381bc664-7dc4-46fe-b17e-925396c3bb9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329373798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
2329373798
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3477156600
Short name T1231
Test name
Test status
Simulation time 14774900 ps
CPU time 13.41 seconds
Started May 30 01:05:36 PM PDT 24
Finished May 30 01:05:51 PM PDT 24
Peak memory 262696 kb
Host smart-1ca2c215-fcb9-4886-b354-aefaa2fbcf35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477156600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3477156600
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3533834942
Short name T340
Test name
Test status
Simulation time 46852600 ps
CPU time 13.28 seconds
Started May 30 01:05:28 PM PDT 24
Finished May 30 01:05:42 PM PDT 24
Peak memory 262764 kb
Host smart-02514dcf-047e-48ff-a22e-c23796e68c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533834942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3533834942
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3632197568
Short name T1172
Test name
Test status
Simulation time 15560100 ps
CPU time 13.81 seconds
Started May 30 01:05:31 PM PDT 24
Finished May 30 01:05:46 PM PDT 24
Peak memory 262564 kb
Host smart-16c897ef-5e1f-4ee3-990d-fafeaf468b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632197568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3632197568
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1947605763
Short name T1154
Test name
Test status
Simulation time 31117300 ps
CPU time 13.58 seconds
Started May 30 01:05:38 PM PDT 24
Finished May 30 01:05:53 PM PDT 24
Peak memory 262788 kb
Host smart-02fe6e20-b82f-4d62-b84f-24dd04fa2e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947605763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
1947605763
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1752313955
Short name T1143
Test name
Test status
Simulation time 17375900 ps
CPU time 13.72 seconds
Started May 30 01:05:31 PM PDT 24
Finished May 30 01:05:45 PM PDT 24
Peak memory 262700 kb
Host smart-5eb7930b-2c0b-497c-bccc-5af18e3249bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752313955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1752313955
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.327051119
Short name T1237
Test name
Test status
Simulation time 16879200 ps
CPU time 13.35 seconds
Started May 30 01:05:33 PM PDT 24
Finished May 30 01:05:47 PM PDT 24
Peak memory 262844 kb
Host smart-36b490da-67ae-421e-aeb0-418d47df8326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327051119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.327051119
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3525202453
Short name T1217
Test name
Test status
Simulation time 41787100 ps
CPU time 16.29 seconds
Started May 30 01:05:03 PM PDT 24
Finished May 30 01:05:21 PM PDT 24
Peak memory 272364 kb
Host smart-1a2d0db2-bad1-4ef7-92a6-39e9eaefc550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525202453 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3525202453
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2568905930
Short name T292
Test name
Test status
Simulation time 39418800 ps
CPU time 16.29 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 260492 kb
Host smart-d87fa69b-a093-4747-8b77-c3b61b02904a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568905930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.2568905930
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3294873773
Short name T1227
Test name
Test status
Simulation time 15039700 ps
CPU time 13.33 seconds
Started May 30 01:05:03 PM PDT 24
Finished May 30 01:05:18 PM PDT 24
Peak memory 262916 kb
Host smart-d796caa4-c852-4700-bad8-3f5241dfa1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294873773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3
294873773
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3853400184
Short name T298
Test name
Test status
Simulation time 232435000 ps
CPU time 17.89 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 260592 kb
Host smart-1ddb9911-4a52-4a5e-a6f4-6507896ed89d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853400184 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3853400184
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3784644508
Short name T1131
Test name
Test status
Simulation time 21423800 ps
CPU time 15.34 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 260600 kb
Host smart-af2fb946-7b1b-4ab9-adb9-bbc4858a0328
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784644508 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3784644508
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.337647265
Short name T1122
Test name
Test status
Simulation time 18456900 ps
CPU time 15.61 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:15 PM PDT 24
Peak memory 260572 kb
Host smart-6bda1563-85f0-4e83-ad34-45de3da1fcf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337647265 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.337647265
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1008624687
Short name T255
Test name
Test status
Simulation time 51476000 ps
CPU time 18.53 seconds
Started May 30 01:05:11 PM PDT 24
Finished May 30 01:05:31 PM PDT 24
Peak memory 264216 kb
Host smart-bbc42fcb-2414-44a2-a6d3-2914fba442fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008624687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
008624687
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2303305143
Short name T74
Test name
Test status
Simulation time 460825800 ps
CPU time 463.29 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:12:58 PM PDT 24
Peak memory 261660 kb
Host smart-91011f84-1afd-49e6-a6c9-568302c17407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303305143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2303305143
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1616835739
Short name T1184
Test name
Test status
Simulation time 64394800 ps
CPU time 15.09 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 278236 kb
Host smart-3d01933d-712a-4ae1-83f2-c1b9aac4d556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616835739 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1616835739
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3630095720
Short name T1125
Test name
Test status
Simulation time 24378600 ps
CPU time 14.6 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 260684 kb
Host smart-5554726a-5c08-4522-98dc-286cd5d2802a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630095720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3630095720
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1661239510
Short name T1146
Test name
Test status
Simulation time 169667300 ps
CPU time 13.35 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:34 PM PDT 24
Peak memory 262616 kb
Host smart-862df1ad-8e7a-4786-956f-9682d2398ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661239510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
661239510
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1712647273
Short name T243
Test name
Test status
Simulation time 121355600 ps
CPU time 17.74 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:21 PM PDT 24
Peak memory 260628 kb
Host smart-fbacc6f5-3a10-4b01-af5a-4e3148c4af37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712647273 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1712647273
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1724042573
Short name T1163
Test name
Test status
Simulation time 13076000 ps
CPU time 15.47 seconds
Started May 30 01:05:33 PM PDT 24
Finished May 30 01:05:49 PM PDT 24
Peak memory 260512 kb
Host smart-3b71c31a-85e0-48e2-b427-902274216823
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724042573 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1724042573
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1007355914
Short name T1165
Test name
Test status
Simulation time 25615300 ps
CPU time 13.26 seconds
Started May 30 01:04:58 PM PDT 24
Finished May 30 01:05:13 PM PDT 24
Peak memory 260520 kb
Host smart-a179facd-a374-41a7-b3f7-5adadcefa0e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007355914 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1007355914
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1422558894
Short name T1192
Test name
Test status
Simulation time 56319000 ps
CPU time 18.22 seconds
Started May 30 01:05:17 PM PDT 24
Finished May 30 01:05:36 PM PDT 24
Peak memory 264176 kb
Host smart-fe9f5dc6-3435-44c8-911e-fec40a1d8fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422558894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
422558894
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3056144484
Short name T364
Test name
Test status
Simulation time 1591848300 ps
CPU time 392.99 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:11:46 PM PDT 24
Peak memory 264084 kb
Host smart-0b126339-9f5a-4379-9e3b-16aa48da46c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056144484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3056144484
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1313155726
Short name T221
Test name
Test status
Simulation time 25293200 ps
CPU time 14.97 seconds
Started May 30 01:05:19 PM PDT 24
Finished May 30 01:05:34 PM PDT 24
Peak memory 277768 kb
Host smart-d825d5fe-c981-4db1-b465-599370ec241b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313155726 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1313155726
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.61278996
Short name T1187
Test name
Test status
Simulation time 57715200 ps
CPU time 16.31 seconds
Started May 30 01:05:20 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 260460 kb
Host smart-2243ffa7-42f8-4762-9e9b-dbfdd9de5cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61278996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_csr_rw.61278996
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.638968015
Short name T1207
Test name
Test status
Simulation time 14565400 ps
CPU time 13.4 seconds
Started May 30 01:05:10 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 262972 kb
Host smart-1c9f8a85-92d9-4af9-a1af-6e2605cc9d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638968015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.638968015
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2448286362
Short name T241
Test name
Test status
Simulation time 965416200 ps
CPU time 15.49 seconds
Started May 30 01:04:56 PM PDT 24
Finished May 30 01:05:12 PM PDT 24
Peak memory 260652 kb
Host smart-ee9cd88c-dfcb-46bd-b192-1090954ff592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448286362 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2448286362
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3484718668
Short name T1221
Test name
Test status
Simulation time 12466900 ps
CPU time 15.6 seconds
Started May 30 01:05:02 PM PDT 24
Finished May 30 01:05:18 PM PDT 24
Peak memory 260264 kb
Host smart-e4933bea-78c4-42f6-a221-81610de95a88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484718668 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.3484718668
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.296580944
Short name T1117
Test name
Test status
Simulation time 13079300 ps
CPU time 15.19 seconds
Started May 30 01:05:08 PM PDT 24
Finished May 30 01:05:24 PM PDT 24
Peak memory 260608 kb
Host smart-bbbfb646-739f-4630-ab95-c4a5038c1e49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296580944 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.296580944
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3751685008
Short name T225
Test name
Test status
Simulation time 79197100 ps
CPU time 15.15 seconds
Started May 30 01:04:52 PM PDT 24
Finished May 30 01:05:09 PM PDT 24
Peak memory 264116 kb
Host smart-69482dff-035e-4cc4-a423-6c97c898eb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751685008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3
751685008
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1667152157
Short name T365
Test name
Test status
Simulation time 1103224000 ps
CPU time 457.49 seconds
Started May 30 01:05:07 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 261796 kb
Host smart-8924f81c-a145-4e1a-a11c-38b8dd4983c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667152157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1667152157
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4069866093
Short name T1216
Test name
Test status
Simulation time 1027779600 ps
CPU time 17.76 seconds
Started May 30 01:05:10 PM PDT 24
Finished May 30 01:05:29 PM PDT 24
Peak memory 263144 kb
Host smart-8c24a8be-28e7-4e61-b897-bf23f0fa2b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069866093 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.4069866093
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.589137835
Short name T1200
Test name
Test status
Simulation time 34903600 ps
CPU time 13.94 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:38 PM PDT 24
Peak memory 260508 kb
Host smart-f40d9ad1-89ae-477a-a96c-eb66bf033946
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589137835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_csr_rw.589137835
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4244180548
Short name T343
Test name
Test status
Simulation time 32006600 ps
CPU time 13.49 seconds
Started May 30 01:05:13 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 262640 kb
Host smart-8001f117-70a7-4999-b5ac-caadd00b5bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244180548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.4
244180548
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3937846303
Short name T1128
Test name
Test status
Simulation time 58137100 ps
CPU time 33.33 seconds
Started May 30 01:05:06 PM PDT 24
Finished May 30 01:05:40 PM PDT 24
Peak memory 262304 kb
Host smart-9340f102-3076-448a-9fc8-2da462d7b5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937846303 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3937846303
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.290183389
Short name T1181
Test name
Test status
Simulation time 30104800 ps
CPU time 15.89 seconds
Started May 30 01:04:59 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 260516 kb
Host smart-2524247e-9817-4bc3-9b54-7956b7c32589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290183389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.290183389
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.810549666
Short name T1144
Test name
Test status
Simulation time 15054500 ps
CPU time 15.51 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 260544 kb
Host smart-01dc4c1d-18c6-47c9-9309-43a0db729bc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810549666 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.810549666
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.942379052
Short name T254
Test name
Test status
Simulation time 109468700 ps
CPU time 19.58 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:05:33 PM PDT 24
Peak memory 264152 kb
Host smart-6b9069e4-0244-493a-b603-6d26bab48e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942379052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.942379052
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2401124130
Short name T359
Test name
Test status
Simulation time 197986600 ps
CPU time 384.37 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:11:34 PM PDT 24
Peak memory 260884 kb
Host smart-943da93a-5ef9-4e52-a0e9-da422b72f6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401124130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2401124130
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1751122701
Short name T1223
Test name
Test status
Simulation time 85688700 ps
CPU time 16.2 seconds
Started May 30 01:05:07 PM PDT 24
Finished May 30 01:05:25 PM PDT 24
Peak memory 270640 kb
Host smart-7e64eaf7-926d-4a03-9759-c24b77f43aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751122701 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1751122701
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1490861973
Short name T1220
Test name
Test status
Simulation time 181956400 ps
CPU time 17.03 seconds
Started May 30 01:05:15 PM PDT 24
Finished May 30 01:05:33 PM PDT 24
Peak memory 264132 kb
Host smart-5ebcf8d1-0739-4639-876b-8b4e8d20ffbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490861973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1490861973
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2494907775
Short name T1206
Test name
Test status
Simulation time 14730200 ps
CPU time 13.46 seconds
Started May 30 01:05:23 PM PDT 24
Finished May 30 01:05:37 PM PDT 24
Peak memory 262640 kb
Host smart-62aff4eb-d05a-4bd4-98a2-9cc96e205305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494907775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
494907775
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2976635459
Short name T242
Test name
Test status
Simulation time 61594700 ps
CPU time 16.95 seconds
Started May 30 01:05:09 PM PDT 24
Finished May 30 01:05:27 PM PDT 24
Peak memory 262424 kb
Host smart-4444b7a3-daed-4092-b015-4cd3ee802fbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976635459 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2976635459
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1943550378
Short name T1171
Test name
Test status
Simulation time 104865300 ps
CPU time 13.25 seconds
Started May 30 01:05:12 PM PDT 24
Finished May 30 01:05:26 PM PDT 24
Peak memory 260524 kb
Host smart-12ea8059-6e58-4e12-9ec9-bf31cbe47696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943550378 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1943550378
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2651389969
Short name T1140
Test name
Test status
Simulation time 29617900 ps
CPU time 15.74 seconds
Started May 30 01:05:00 PM PDT 24
Finished May 30 01:05:17 PM PDT 24
Peak memory 260516 kb
Host smart-db990ee8-11d0-4f67-9580-489e756176c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651389969 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2651389969
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1078692977
Short name T249
Test name
Test status
Simulation time 117556200 ps
CPU time 19.39 seconds
Started May 30 01:05:14 PM PDT 24
Finished May 30 01:05:35 PM PDT 24
Peak memory 264120 kb
Host smart-396e66c3-416d-41fe-8f5a-752f4bd33d38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078692977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
078692977
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.519696526
Short name T259
Test name
Test status
Simulation time 1735642100 ps
CPU time 768.18 seconds
Started May 30 01:05:31 PM PDT 24
Finished May 30 01:18:20 PM PDT 24
Peak memory 263008 kb
Host smart-910fafc9-803e-4e4d-8f65-37272cf8fbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519696526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.519696526
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3321660330
Short name T12
Test name
Test status
Simulation time 20438800 ps
CPU time 13.75 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:09:49 PM PDT 24
Peak memory 264796 kb
Host smart-feb0bad7-07a3-4b62-80c7-ef667a662fe8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321660330 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3321660330
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.1478095765
Short name T495
Test name
Test status
Simulation time 56265600 ps
CPU time 13.9 seconds
Started May 30 01:09:39 PM PDT 24
Finished May 30 01:09:54 PM PDT 24
Peak memory 264692 kb
Host smart-6434a5e9-08ac-4110-9eed-024327b57851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478095765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1
478095765
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.3637633151
Short name T922
Test name
Test status
Simulation time 25882100 ps
CPU time 15.65 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:09:48 PM PDT 24
Peak memory 275528 kb
Host smart-0e5e6c8a-9333-465f-8873-3157a5641e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637633151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3637633151
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2452505472
Short name T141
Test name
Test status
Simulation time 12936100 ps
CPU time 20.64 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:09:53 PM PDT 24
Peak memory 273132 kb
Host smart-2c9e3799-1bd3-41fd-9cfb-3f89bc26bc15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452505472 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2452505472
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2265831850
Short name T653
Test name
Test status
Simulation time 1153357300 ps
CPU time 21.72 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:09:51 PM PDT 24
Peak memory 264896 kb
Host smart-33a120f1-bac1-41e5-9ccd-dbbe2cfd7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265831850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2265831850
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.963210051
Short name T734
Test name
Test status
Simulation time 681680200 ps
CPU time 40.96 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:10:15 PM PDT 24
Peak memory 261796 kb
Host smart-618e4c30-625b-47a7-9aa0-e3e6c32c8ed6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963210051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.963210051
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.172753122
Short name T1031
Test name
Test status
Simulation time 100611248800 ps
CPU time 2622.58 seconds
Started May 30 01:09:37 PM PDT 24
Finished May 30 01:53:20 PM PDT 24
Peak memory 262748 kb
Host smart-2a30a7b4-430f-40c4-9517-7bfe02225a53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172753122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_full_mem_access.172753122
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2387081128
Short name T237
Test name
Test status
Simulation time 208698000 ps
CPU time 102.6 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:11:01 PM PDT 24
Peak memory 262128 kb
Host smart-c3b821b5-ea12-46be-a854-ab06cbe195b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387081128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2387081128
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3087429407
Short name T1092
Test name
Test status
Simulation time 10034144800 ps
CPU time 55.71 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:28 PM PDT 24
Peak memory 272356 kb
Host smart-1c71485b-c1bd-455e-963d-021e1a67507a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087429407 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3087429407
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.2531040178
Short name T508
Test name
Test status
Simulation time 186786416100 ps
CPU time 1925.8 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:41:27 PM PDT 24
Peak memory 263608 kb
Host smart-bdf88ec4-7959-4f82-8981-c5e8c6c73067
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531040178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.2531040178
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1896003580
Short name T911
Test name
Test status
Simulation time 200195031300 ps
CPU time 839.6 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:23:14 PM PDT 24
Peak memory 264076 kb
Host smart-41f2878a-56f7-4bf6-a6dd-ae22679d069f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896003580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1896003580
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1022751662
Short name T717
Test name
Test status
Simulation time 3202257100 ps
CPU time 115.96 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:11:11 PM PDT 24
Peak memory 262308 kb
Host smart-c1362062-cbca-4d17-b6a2-f640eb92d9da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022751662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.1022751662
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.724187249
Short name T347
Test name
Test status
Simulation time 4353436700 ps
CPU time 171.75 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:12:24 PM PDT 24
Peak memory 292192 kb
Host smart-870568b8-f6c8-45b3-9005-b83740218c55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724187249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.724187249
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2526364520
Short name T75
Test name
Test status
Simulation time 11904248400 ps
CPU time 118.87 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:11:32 PM PDT 24
Peak memory 291548 kb
Host smart-ce4c66dd-f5f1-475e-92e8-375d4cf0eba8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526364520 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2526364520
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2345359119
Short name T881
Test name
Test status
Simulation time 78290249800 ps
CPU time 227.88 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:13:20 PM PDT 24
Peak memory 259804 kb
Host smart-fedc8edf-f2ef-4a31-a360-12a7a6df6696
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234
5359119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2345359119
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.298218149
Short name T639
Test name
Test status
Simulation time 3878811000 ps
CPU time 86.67 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:11:01 PM PDT 24
Peak memory 259752 kb
Host smart-e4c0481a-dc28-453b-a11a-04d2c957cdd8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298218149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.298218149
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3252343968
Short name T472
Test name
Test status
Simulation time 44696400 ps
CPU time 13.56 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:09:47 PM PDT 24
Peak memory 259968 kb
Host smart-d9554e9f-68e3-4008-8800-b5819273d745
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252343968 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3252343968
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.4104161015
Short name T62
Test name
Test status
Simulation time 5138740300 ps
CPU time 74.69 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:46 PM PDT 24
Peak memory 260512 kb
Host smart-1c8300bd-83e8-4a00-b355-2915bb2e725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104161015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.4104161015
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.994341443
Short name T104
Test name
Test status
Simulation time 49473007800 ps
CPU time 814.14 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:22:55 PM PDT 24
Peak memory 274096 kb
Host smart-93057f68-ec38-46a1-8e26-762e466c895f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994341443 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_mp_regions.994341443
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.3963709867
Short name T388
Test name
Test status
Simulation time 54931900 ps
CPU time 131.17 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:11:26 PM PDT 24
Peak memory 264392 kb
Host smart-60a7b61b-38a0-4320-826c-7e4e8c1e327a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963709867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.3963709867
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3803135637
Short name T576
Test name
Test status
Simulation time 4141190300 ps
CPU time 156.6 seconds
Started May 30 01:09:34 PM PDT 24
Finished May 30 01:12:12 PM PDT 24
Peak memory 281248 kb
Host smart-1c9365be-a52f-4f03-89de-8fcf0931bc8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803135637 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3803135637
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.4149719658
Short name T184
Test name
Test status
Simulation time 93017900 ps
CPU time 58.67 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:10:13 PM PDT 24
Peak memory 262276 kb
Host smart-ff23b73e-b26c-4527-9f27-2824e2e4de25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149719658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.4149719658
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2380978208
Short name T150
Test name
Test status
Simulation time 48384700 ps
CPU time 14.42 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:09:48 PM PDT 24
Peak memory 262024 kb
Host smart-773cc098-708b-4961-8943-14d8872bb5df
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380978208 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2380978208
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.1435174190
Short name T269
Test name
Test status
Simulation time 18826720300 ps
CPU time 207.52 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:13:00 PM PDT 24
Peak memory 264804 kb
Host smart-ce267fe2-1ee1-492e-9365-efe2aaf0360e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435174190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.1435174190
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3416868814
Short name T878
Test name
Test status
Simulation time 11627118200 ps
CPU time 862.61 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:23:39 PM PDT 24
Peak memory 285748 kb
Host smart-2b7c3a97-2dbd-452a-a478-2fdfa2e70b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416868814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3416868814
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1161749004
Short name T787
Test name
Test status
Simulation time 127813300 ps
CPU time 101.82 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:11:03 PM PDT 24
Peak memory 264688 kb
Host smart-42d2de5a-060e-407c-b7e3-b475ea5c45fa
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1161749004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1161749004
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3041369020
Short name T1040
Test name
Test status
Simulation time 153594900 ps
CPU time 31.77 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:04 PM PDT 24
Peak memory 279152 kb
Host smart-1583bd95-acae-4e8d-bdf8-400b3e68f818
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041369020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3041369020
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3772537319
Short name T7
Test name
Test status
Simulation time 47361800 ps
CPU time 42.76 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:15 PM PDT 24
Peak memory 273348 kb
Host smart-1d6ae5dc-053f-4503-b6a0-1d498fe275b7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772537319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3772537319
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.3272403080
Short name T29
Test name
Test status
Simulation time 206266700 ps
CPU time 35.14 seconds
Started May 30 01:09:28 PM PDT 24
Finished May 30 01:10:04 PM PDT 24
Peak memory 273172 kb
Host smart-13cb0eb6-862e-44bc-a2fe-85827208c193
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272403080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.3272403080
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1448283126
Short name T423
Test name
Test status
Simulation time 80194100 ps
CPU time 13.62 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:09:43 PM PDT 24
Peak memory 264748 kb
Host smart-904cd235-b96a-41c9-8493-f4c66129054a
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1448283126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1448283126
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.407878574
Short name T1049
Test name
Test status
Simulation time 58334700 ps
CPU time 22.24 seconds
Started May 30 01:09:34 PM PDT 24
Finished May 30 01:09:58 PM PDT 24
Peak memory 264812 kb
Host smart-ababfadc-025d-4e26-9e5a-8c37d6d8caa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407878574 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.407878574
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3937558415
Short name T304
Test name
Test status
Simulation time 41582900 ps
CPU time 21.11 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:09:53 PM PDT 24
Peak memory 264848 kb
Host smart-f1b57501-4a15-405b-beee-24e8cdfe764c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937558415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3937558415
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2559482933
Short name T157
Test name
Test status
Simulation time 2398920700 ps
CPU time 125.61 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:11:39 PM PDT 24
Peak memory 288944 kb
Host smart-b30a4e71-8a6b-4b0b-9a97-fa06070c6d97
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559482933 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.2559482933
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.593168572
Short name T915
Test name
Test status
Simulation time 1217989800 ps
CPU time 147.15 seconds
Started May 30 01:09:28 PM PDT 24
Finished May 30 01:11:56 PM PDT 24
Peak memory 281248 kb
Host smart-05497040-59ae-4bac-9b38-841439751ba9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
593168572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.593168572
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.4278889097
Short name T558
Test name
Test status
Simulation time 657364300 ps
CPU time 122.34 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:11:32 PM PDT 24
Peak memory 293940 kb
Host smart-1d87bb58-68e2-4d34-8f7e-921c280479d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278889097 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.4278889097
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.1032306706
Short name T201
Test name
Test status
Simulation time 16555703800 ps
CPU time 725.26 seconds
Started May 30 01:09:30 PM PDT 24
Finished May 30 01:21:36 PM PDT 24
Peak memory 327496 kb
Host smart-ff7a61a9-5947-4078-995f-e24b073f627a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032306706 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.1032306706
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4293633303
Short name T1042
Test name
Test status
Simulation time 72961200 ps
CPU time 31.31 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:04 PM PDT 24
Peak memory 274356 kb
Host smart-553460a7-1bb8-4343-a4cb-ed5677976bc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293633303 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4293633303
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.2754498277
Short name T42
Test name
Test status
Simulation time 8762031700 ps
CPU time 479.04 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:17:32 PM PDT 24
Peak memory 311640 kb
Host smart-65e53e62-a229-48e3-9af2-a0334642be2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754498277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.2754498277
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.198915096
Short name T17
Test name
Test status
Simulation time 4114954800 ps
CPU time 4730.41 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 02:28:24 PM PDT 24
Peak memory 286496 kb
Host smart-3420e7f3-4768-4b2c-a800-a17a9ab569ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198915096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.198915096
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.4241757090
Short name T107
Test name
Test status
Simulation time 414988600 ps
CPU time 52.97 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:10:25 PM PDT 24
Peak memory 273080 kb
Host smart-786014f7-1feb-4412-83e6-30343af2e60a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241757090 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.4241757090
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.135240477
Short name T513
Test name
Test status
Simulation time 2145709800 ps
CPU time 73.34 seconds
Started May 30 01:09:37 PM PDT 24
Finished May 30 01:10:52 PM PDT 24
Peak memory 264952 kb
Host smart-010ee8c3-4845-4544-9b31-53605c2458ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135240477 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_counter.135240477
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.850013227
Short name T830
Test name
Test status
Simulation time 56691200 ps
CPU time 74.9 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 275052 kb
Host smart-0745e109-1787-4e6e-b3d3-fb929362a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850013227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.850013227
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2474955341
Short name T24
Test name
Test status
Simulation time 17304800 ps
CPU time 25.81 seconds
Started May 30 01:09:18 PM PDT 24
Finished May 30 01:09:46 PM PDT 24
Peak memory 258772 kb
Host smart-8b91ebe1-77d8-4c60-bf05-a032bb656f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474955341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2474955341
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.949284550
Short name T934
Test name
Test status
Simulation time 360603500 ps
CPU time 888.4 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:24:20 PM PDT 24
Peak memory 284264 kb
Host smart-74641a83-b6cc-41c1-96a3-9ec7611940fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949284550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress
_all.949284550
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1884304466
Short name T1047
Test name
Test status
Simulation time 79117400 ps
CPU time 26.38 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:09:47 PM PDT 24
Peak memory 261252 kb
Host smart-ea99852a-f536-44c7-ac9e-be9d1c2d4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884304466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1884304466
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2133639523
Short name T614
Test name
Test status
Simulation time 5326556300 ps
CPU time 211.77 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:13:04 PM PDT 24
Peak memory 264772 kb
Host smart-ce7b14dc-4096-48fa-90ff-01824022b336
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133639523 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.2133639523
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1446874857
Short name T747
Test name
Test status
Simulation time 139129500 ps
CPU time 15.4 seconds
Started May 30 01:09:26 PM PDT 24
Finished May 30 01:09:42 PM PDT 24
Peak memory 258372 kb
Host smart-b047f3cf-bf1d-4b9b-a72f-41c0de01cedf
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1446874857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.1446874857
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.2670224424
Short name T11
Test name
Test status
Simulation time 14105300 ps
CPU time 13.58 seconds
Started May 30 01:09:46 PM PDT 24
Finished May 30 01:10:00 PM PDT 24
Peak memory 260724 kb
Host smart-0c5c7d6c-966a-4fa9-8346-9d16760d96e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670224424 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2670224424
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3128915778
Short name T626
Test name
Test status
Simulation time 43408100 ps
CPU time 13.96 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:10:01 PM PDT 24
Peak memory 264744 kb
Host smart-4431dca5-f26d-4860-8feb-f6fb18f2d5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128915778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
128915778
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.819009320
Short name T1005
Test name
Test status
Simulation time 14725300 ps
CPU time 15.69 seconds
Started May 30 01:09:43 PM PDT 24
Finished May 30 01:10:00 PM PDT 24
Peak memory 274904 kb
Host smart-7abec96c-7f79-426f-aafe-0c3b3fd68f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819009320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.819009320
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1526602194
Short name T822
Test name
Test status
Simulation time 347744300 ps
CPU time 104.83 seconds
Started May 30 01:09:34 PM PDT 24
Finished May 30 01:11:20 PM PDT 24
Peak memory 274120 kb
Host smart-f8b98a06-d039-4c3f-b5f9-216df518b548
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526602194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1526602194
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3478118009
Short name T1025
Test name
Test status
Simulation time 20805600 ps
CPU time 21.43 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:10:11 PM PDT 24
Peak memory 264656 kb
Host smart-9900d652-6feb-4844-a4c6-263fef592179
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478118009 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3478118009
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3836603354
Short name T1075
Test name
Test status
Simulation time 1210824600 ps
CPU time 237.6 seconds
Started May 30 01:09:31 PM PDT 24
Finished May 30 01:13:30 PM PDT 24
Peak memory 262748 kb
Host smart-90b1261e-13e1-4df9-abdf-2843d27bf48d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836603354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3836603354
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.4029367988
Short name T947
Test name
Test status
Simulation time 8841505500 ps
CPU time 2436.84 seconds
Started May 30 01:09:35 PM PDT 24
Finished May 30 01:50:13 PM PDT 24
Peak memory 264096 kb
Host smart-2426cc8c-cf4b-4646-8b18-8412e94ea05b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029367988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.4029367988
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2253102982
Short name T162
Test name
Test status
Simulation time 1317829500 ps
CPU time 2655.14 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:53:52 PM PDT 24
Peak memory 264556 kb
Host smart-c2e71f0a-0985-47da-a912-269263f801e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253102982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2253102982
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2151602417
Short name T620
Test name
Test status
Simulation time 1551245800 ps
CPU time 893.15 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:24:28 PM PDT 24
Peak memory 273072 kb
Host smart-a4bd5adc-aa97-4878-b97d-73737d90e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151602417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2151602417
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2077899270
Short name T737
Test name
Test status
Simulation time 480825500 ps
CPU time 25.09 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:09:58 PM PDT 24
Peak memory 264888 kb
Host smart-f6001c76-0c85-43e6-bb81-769bf1d06525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077899270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2077899270
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1246390919
Short name T1091
Test name
Test status
Simulation time 159625780700 ps
CPU time 2742.16 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:55:17 PM PDT 24
Peak memory 262704 kb
Host smart-ba0ce4e3-dd4a-459c-a6f5-443570feb3a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246390919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1246390919
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2887554368
Short name T125
Test name
Test status
Simulation time 10039194000 ps
CPU time 61.43 seconds
Started May 30 01:09:55 PM PDT 24
Finished May 30 01:10:57 PM PDT 24
Peak memory 286932 kb
Host smart-12eaf4d2-8dc3-41f1-b22e-cbb8e08e8222
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887554368 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2887554368
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.4085720310
Short name T631
Test name
Test status
Simulation time 170181617500 ps
CPU time 822.5 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:23:20 PM PDT 24
Peak memory 263720 kb
Host smart-6db01da1-41d3-4569-8faa-143c89e48887
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085720310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.4085720310
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.824572674
Short name T494
Test name
Test status
Simulation time 1932375400 ps
CPU time 64.97 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:10:40 PM PDT 24
Peak memory 262392 kb
Host smart-7e4b95cd-fede-427d-af65-5e75e1a55949
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824572674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.824572674
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.558029305
Short name T238
Test name
Test status
Simulation time 18597125600 ps
CPU time 633.42 seconds
Started May 30 01:09:38 PM PDT 24
Finished May 30 01:20:13 PM PDT 24
Peak memory 332828 kb
Host smart-2e3bb4f0-fc6d-464e-9c18-188c3f58ea78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558029305 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_integrity.558029305
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.3353495171
Short name T806
Test name
Test status
Simulation time 8508718000 ps
CPU time 73.73 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:11:00 PM PDT 24
Peak memory 264732 kb
Host smart-b06d0aad-8b76-49e8-bf32-e50fc42ad26a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353495171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.3353495171
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1147315917
Short name T34
Test name
Test status
Simulation time 42724433400 ps
CPU time 212.88 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:13:22 PM PDT 24
Peak memory 264756 kb
Host smart-4460f88e-2aa6-42bb-ab4f-ab92469bc958
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114
7315917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1147315917
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3368290608
Short name T411
Test name
Test status
Simulation time 1935970900 ps
CPU time 89.43 seconds
Started May 30 01:09:38 PM PDT 24
Finished May 30 01:11:09 PM PDT 24
Peak memory 259540 kb
Host smart-03f767aa-26cd-4d9f-8e4d-eb9880848ed6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368290608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3368290608
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.270928032
Short name T281
Test name
Test status
Simulation time 15738300 ps
CPU time 13.38 seconds
Started May 30 01:09:43 PM PDT 24
Finished May 30 01:09:58 PM PDT 24
Peak memory 264812 kb
Host smart-de8a39cd-7862-499a-a7e9-79d14298b511
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270928032 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.270928032
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1972198916
Short name T59
Test name
Test status
Simulation time 1314684000 ps
CPU time 72.23 seconds
Started May 30 01:09:39 PM PDT 24
Finished May 30 01:10:52 PM PDT 24
Peak memory 260624 kb
Host smart-61a9fb6f-77ca-4f50-8be2-2364a6c9525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972198916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1972198916
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2878039049
Short name T116
Test name
Test status
Simulation time 10900118900 ps
CPU time 299.25 seconds
Started May 30 01:09:37 PM PDT 24
Finished May 30 01:14:38 PM PDT 24
Peak memory 273124 kb
Host smart-2c0916e2-6306-4114-a5d1-c5c36a05cb12
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878039049 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2878039049
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.4274790014
Short name T677
Test name
Test status
Simulation time 42470000 ps
CPU time 110.5 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 259320 kb
Host smart-43ebc238-0601-47d3-a1bc-8c81ede98d51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274790014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.4274790014
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3806749932
Short name T998
Test name
Test status
Simulation time 6339645900 ps
CPU time 216.47 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:13:11 PM PDT 24
Peak memory 281236 kb
Host smart-1129ae22-c67c-47d9-8148-dbb91cb40a47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806749932 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3806749932
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2283509391
Short name T605
Test name
Test status
Simulation time 433459700 ps
CPU time 418.8 seconds
Started May 30 01:09:30 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 261380 kb
Host smart-9c8131af-e38e-4c03-91f6-6fbc5157df77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283509391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2283509391
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1711041058
Short name T91
Test name
Test status
Simulation time 758550500 ps
CPU time 20.49 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:10:07 PM PDT 24
Peak memory 264956 kb
Host smart-0dd36e01-7081-46fb-8eac-050b37cd5670
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711041058 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1711041058
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2436041574
Short name T580
Test name
Test status
Simulation time 191775800 ps
CPU time 14.33 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:10:03 PM PDT 24
Peak memory 262120 kb
Host smart-e0086eae-7aa0-4660-b34d-286e7832dbca
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436041574 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2436041574
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1164223857
Short name T20
Test name
Test status
Simulation time 20260900 ps
CPU time 13.72 seconds
Started May 30 01:09:42 PM PDT 24
Finished May 30 01:09:57 PM PDT 24
Peak memory 258432 kb
Host smart-d8305b05-2e1e-4b7f-8b33-8d81a4dbcc08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164223857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1164223857
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3506253827
Short name T585
Test name
Test status
Simulation time 43921500 ps
CPU time 76.65 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:10:53 PM PDT 24
Peak memory 274800 kb
Host smart-965c4d67-e754-406c-bb77-839fd7ff1175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506253827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3506253827
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.572033655
Short name T765
Test name
Test status
Simulation time 55841700 ps
CPU time 101 seconds
Started May 30 01:09:32 PM PDT 24
Finished May 30 01:11:14 PM PDT 24
Peak memory 264816 kb
Host smart-8db64396-7a92-4ed7-97cb-8a62cf9e684c
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=572033655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.572033655
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.3801547375
Short name T353
Test name
Test status
Simulation time 64774900 ps
CPU time 31.73 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:10:17 PM PDT 24
Peak memory 279208 kb
Host smart-01b5a772-b977-4b11-adaf-8096641113fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801547375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.3801547375
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.1470196359
Short name T459
Test name
Test status
Simulation time 1027250200 ps
CPU time 35.95 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:32 PM PDT 24
Peak memory 272964 kb
Host smart-64636119-a3ff-4b97-ac26-7ff43d0b57b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470196359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.1470196359
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1070115545
Short name T941
Test name
Test status
Simulation time 89448900 ps
CPU time 22.53 seconds
Started May 30 01:09:35 PM PDT 24
Finished May 30 01:09:58 PM PDT 24
Peak memory 264024 kb
Host smart-1177bbaf-cf9f-47b9-ae8e-d2acc92a7169
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070115545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1070115545
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1816507429
Short name T133
Test name
Test status
Simulation time 71758354800 ps
CPU time 1219.76 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:30:10 PM PDT 24
Peak memory 492064 kb
Host smart-98f651f4-d406-4f91-87a4-2e429b3971b1
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816507429 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1816507429
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.368014675
Short name T210
Test name
Test status
Simulation time 594924500 ps
CPU time 113.75 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:11:28 PM PDT 24
Peak memory 296540 kb
Host smart-31612f12-ea3c-4cfd-8c04-42904b530536
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368014675 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_ro.368014675
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.3929128302
Short name T271
Test name
Test status
Simulation time 585754900 ps
CPU time 151.14 seconds
Started May 30 01:09:29 PM PDT 24
Finished May 30 01:12:00 PM PDT 24
Peak memory 281284 kb
Host smart-156d08f2-c261-4d94-9538-a4a2e743ccb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3929128302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3929128302
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1533221270
Short name T425
Test name
Test status
Simulation time 715609900 ps
CPU time 131.27 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:12:19 PM PDT 24
Peak memory 293952 kb
Host smart-20522e37-77b0-46a7-82d2-db399cc46af3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533221270 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1533221270
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.3959471567
Short name T500
Test name
Test status
Simulation time 7512084900 ps
CPU time 446.36 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:17:01 PM PDT 24
Peak memory 309228 kb
Host smart-33ad6192-e820-4ccb-92d3-4ca4c642f9ef
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959471567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.3959471567
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.1498761041
Short name T1084
Test name
Test status
Simulation time 14506290500 ps
CPU time 608.11 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:19:43 PM PDT 24
Peak memory 334864 kb
Host smart-79ace38a-24f4-4bee-82c2-d739af210c38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498761041 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.1498761041
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.476254463
Short name T325
Test name
Test status
Simulation time 95054100 ps
CPU time 27.24 seconds
Started May 30 01:09:43 PM PDT 24
Finished May 30 01:10:11 PM PDT 24
Peak memory 274404 kb
Host smart-ca40aac1-efa4-4a5d-9b7d-6f6dc8e3b4b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476254463 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.476254463
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.2889227615
Short name T106
Test name
Test status
Simulation time 58361268200 ps
CPU time 536.19 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:18:30 PM PDT 24
Peak memory 313272 kb
Host smart-ee0bb170-e4cd-4b68-add6-2e054ab140d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889227615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.2889227615
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.4133371632
Short name T380
Test name
Test status
Simulation time 854681500 ps
CPU time 89.26 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:11:03 PM PDT 24
Peak memory 264804 kb
Host smart-0e049258-5da5-4503-88ae-4ae1bcdc9250
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133371632 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.4133371632
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1257414154
Short name T1089
Test name
Test status
Simulation time 2920354600 ps
CPU time 71.08 seconds
Started May 30 01:09:33 PM PDT 24
Finished May 30 01:10:45 PM PDT 24
Peak memory 272496 kb
Host smart-7aac5d64-01f0-4831-8629-879eb407abd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257414154 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1257414154
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2271237987
Short name T444
Test name
Test status
Simulation time 119655100 ps
CPU time 146.03 seconds
Started May 30 01:09:30 PM PDT 24
Finished May 30 01:11:56 PM PDT 24
Peak memory 276036 kb
Host smart-4ccb02c8-3239-464e-b17d-0d821e2c9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271237987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2271237987
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.4181523499
Short name T668
Test name
Test status
Simulation time 16801600 ps
CPU time 26.15 seconds
Started May 30 01:09:34 PM PDT 24
Finished May 30 01:10:01 PM PDT 24
Peak memory 258812 kb
Host smart-cbb958d7-af03-4f2b-8df6-aa9dee91385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181523499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.4181523499
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1860324086
Short name T964
Test name
Test status
Simulation time 46535100 ps
CPU time 38.57 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:10:25 PM PDT 24
Peak memory 259148 kb
Host smart-33dca94e-e556-4df7-8dc9-bb5060efa007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860324086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1860324086
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2499306062
Short name T511
Test name
Test status
Simulation time 35379300 ps
CPU time 24.12 seconds
Started May 30 01:09:36 PM PDT 24
Finished May 30 01:10:01 PM PDT 24
Peak memory 261320 kb
Host smart-e7b0296f-497d-46c2-96bf-93532a6616c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499306062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2499306062
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.2673253204
Short name T983
Test name
Test status
Simulation time 7112915400 ps
CPU time 194.44 seconds
Started May 30 01:09:35 PM PDT 24
Finished May 30 01:12:51 PM PDT 24
Peak memory 258760 kb
Host smart-861632ce-e3ad-4acc-9ea6-653759ed217d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673253204 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.2673253204
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3992809932
Short name T23
Test name
Test status
Simulation time 293964700 ps
CPU time 14.88 seconds
Started May 30 01:09:55 PM PDT 24
Finished May 30 01:10:10 PM PDT 24
Peak memory 259692 kb
Host smart-1fe52805-4e4b-4195-a16b-c823c430ebae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992809932 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3992809932
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1223350608
Short name T306
Test name
Test status
Simulation time 28156400 ps
CPU time 15.44 seconds
Started May 30 01:11:03 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 275540 kb
Host smart-8678c6fc-7dc4-4e23-ad63-d2f6b70fb980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223350608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1223350608
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.4268385098
Short name T493
Test name
Test status
Simulation time 27983800 ps
CPU time 21.83 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:11:24 PM PDT 24
Peak memory 273176 kb
Host smart-b72b30ef-cdd0-41dd-837c-ea1268215318
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268385098 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.4268385098
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1217588707
Short name T1038
Test name
Test status
Simulation time 46672400 ps
CPU time 13.55 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:15 PM PDT 24
Peak memory 257952 kb
Host smart-942b6d14-5d85-4d5f-b21a-3b5453f35138
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217588707 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1217588707
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3779110045
Short name T123
Test name
Test status
Simulation time 40126331300 ps
CPU time 848.96 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:24:57 PM PDT 24
Peak memory 263064 kb
Host smart-9dcbc683-33d9-4832-a24e-74604b73bdc8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779110045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3779110045
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2685366057
Short name T25
Test name
Test status
Simulation time 741898800 ps
CPU time 126.32 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:13:06 PM PDT 24
Peak memory 292688 kb
Host smart-6314031c-fc5d-4279-bf4e-28cc4eb4b431
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685366057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2685366057
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1654125142
Short name T414
Test name
Test status
Simulation time 5969554700 ps
CPU time 137.67 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:13:17 PM PDT 24
Peak memory 293100 kb
Host smart-46654567-9237-4361-8b14-d46ed16ceaf8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654125142 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1654125142
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.754195531
Short name T409
Test name
Test status
Simulation time 2156997000 ps
CPU time 66.77 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:12:07 PM PDT 24
Peak memory 263112 kb
Host smart-c8996aa2-b29d-4ce0-9f5a-ce553d01ef92
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754195531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.754195531
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3447499173
Short name T679
Test name
Test status
Simulation time 66197300 ps
CPU time 13.43 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:11:13 PM PDT 24
Peak memory 264724 kb
Host smart-416e8b36-4b43-42e7-9511-afbf52f6e626
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447499173 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3447499173
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1989474566
Short name T815
Test name
Test status
Simulation time 69249828000 ps
CPU time 318.77 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:16:20 PM PDT 24
Peak memory 274100 kb
Host smart-579be60e-014a-4d4c-8789-5d61b8dfc47f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989474566 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1989474566
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2179677912
Short name T300
Test name
Test status
Simulation time 37521800 ps
CPU time 130.48 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:12:59 PM PDT 24
Peak memory 259924 kb
Host smart-1c0780fc-85ec-438c-91a3-5bf93d0da895
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179677912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2179677912
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3346282702
Short name T567
Test name
Test status
Simulation time 161023100 ps
CPU time 447.37 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 264840 kb
Host smart-5d5cfcb0-a45a-4c5a-8d2c-f817ed840326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346282702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3346282702
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2345434761
Short name T720
Test name
Test status
Simulation time 57623900 ps
CPU time 13.61 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:14 PM PDT 24
Peak memory 258120 kb
Host smart-9a8add1f-a2c2-400d-920f-6db0c75184c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345434761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2345434761
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.887374529
Short name T560
Test name
Test status
Simulation time 247723800 ps
CPU time 374.24 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:17:02 PM PDT 24
Peak memory 280724 kb
Host smart-45c7e35e-9b4e-48b4-a97b-cf0359776b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887374529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.887374529
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2006926366
Short name T469
Test name
Test status
Simulation time 423569600 ps
CPU time 35.64 seconds
Started May 30 01:10:56 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 265964 kb
Host smart-a7034793-f11d-4bb2-9ba1-ffa80c4bf6b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006926366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2006926366
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2637092352
Short name T981
Test name
Test status
Simulation time 8197999300 ps
CPU time 115.59 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:12:56 PM PDT 24
Peak memory 296480 kb
Host smart-999485c0-e20c-4370-9a8f-c455fa850faa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637092352 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2637092352
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2194137259
Short name T902
Test name
Test status
Simulation time 4432273200 ps
CPU time 563.72 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:20:24 PM PDT 24
Peak memory 314092 kb
Host smart-f1bdfb65-a060-4e4a-b148-86294860245f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194137259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.2194137259
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2045144011
Short name T195
Test name
Test status
Simulation time 28022100 ps
CPU time 30.92 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:11:30 PM PDT 24
Peak memory 273088 kb
Host smart-0f9b52bf-376e-45b2-b2ac-be50b42f09d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045144011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2045144011
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2431515685
Short name T532
Test name
Test status
Simulation time 249303300 ps
CPU time 31.01 seconds
Started May 30 01:11:03 PM PDT 24
Finished May 30 01:11:35 PM PDT 24
Peak memory 274336 kb
Host smart-04c3a5de-60c8-4aa6-8021-129934d2379d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431515685 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2431515685
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.1479999277
Short name T399
Test name
Test status
Simulation time 731905100 ps
CPU time 56.44 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:11:57 PM PDT 24
Peak memory 262060 kb
Host smart-18c63a56-c1a6-4115-b6c8-74773a7791ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479999277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1479999277
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.996766744
Short name T51
Test name
Test status
Simulation time 25251600 ps
CPU time 73.79 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:11:59 PM PDT 24
Peak memory 274876 kb
Host smart-1b03e1d5-fdf9-466c-b637-94c7a1303ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996766744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.996766744
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.800929709
Short name T379
Test name
Test status
Simulation time 1694758300 ps
CPU time 135.54 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 258820 kb
Host smart-b51fdd97-8d71-45b8-af8e-c00427512526
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800929709 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.800929709
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1502104
Short name T728
Test name
Test status
Simulation time 84530900 ps
CPU time 13.52 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:14 PM PDT 24
Peak memory 264732 kb
Host smart-0d8de574-f37b-45be-ad24-4931be46019d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1502104
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.4065816549
Short name T1078
Test name
Test status
Simulation time 15782900 ps
CPU time 16.55 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:11:15 PM PDT 24
Peak memory 275556 kb
Host smart-20b36b83-1d84-4a61-9ccf-7d0078d8c86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065816549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.4065816549
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3632495938
Short name T658
Test name
Test status
Simulation time 11987200 ps
CPU time 20.85 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:22 PM PDT 24
Peak memory 273108 kb
Host smart-563473dd-0ad2-48a4-ad93-3715585f555a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632495938 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3632495938
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.930280564
Short name T689
Test name
Test status
Simulation time 10012912800 ps
CPU time 127.22 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:13:10 PM PDT 24
Peak memory 362796 kb
Host smart-09a840d1-c4ac-41de-bbf1-78d879a8517c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930280564 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.930280564
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2000026938
Short name T657
Test name
Test status
Simulation time 25260000 ps
CPU time 13.34 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:15 PM PDT 24
Peak memory 264356 kb
Host smart-6f76c5d6-4eff-4439-9cbb-9c700e50b232
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000026938 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2000026938
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3617208048
Short name T901
Test name
Test status
Simulation time 50118914100 ps
CPU time 827.3 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:24:47 PM PDT 24
Peak memory 263052 kb
Host smart-85ba5979-2b3e-4874-8822-4a299a6a05c2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617208048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3617208048
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.692922516
Short name T671
Test name
Test status
Simulation time 2298051500 ps
CPU time 47.7 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:11:49 PM PDT 24
Peak memory 262316 kb
Host smart-b8724380-8b49-4f39-a25e-c6159789e26c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692922516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h
w_sec_otp.692922516
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3727366476
Short name T783
Test name
Test status
Simulation time 18542841900 ps
CPU time 219.73 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:14:43 PM PDT 24
Peak memory 290496 kb
Host smart-85612f9c-b2d9-49eb-8f3c-08b651b393dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727366476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3727366476
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.890131352
Short name T349
Test name
Test status
Simulation time 27168931300 ps
CPU time 361.8 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 291404 kb
Host smart-bce2f012-7f05-437d-bcbc-ff1571922186
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890131352 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.890131352
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1523997132
Short name T14
Test name
Test status
Simulation time 56018100 ps
CPU time 13.4 seconds
Started May 30 01:11:05 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 260152 kb
Host smart-8a5c7edd-a24c-4ec2-b295-6e80bfbc7344
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523997132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1523997132
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2186139013
Short name T85
Test name
Test status
Simulation time 7689009500 ps
CPU time 597.36 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:20:57 PM PDT 24
Peak memory 274416 kb
Host smart-efb3e2ec-bdaa-46d4-adf3-9707fb83e8df
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186139013 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.2186139013
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.511863755
Short name T1063
Test name
Test status
Simulation time 147542300 ps
CPU time 132.9 seconds
Started May 30 01:10:56 PM PDT 24
Finished May 30 01:13:10 PM PDT 24
Peak memory 259468 kb
Host smart-3bdc3b2b-b6c0-4751-9c8a-3484e1d13b39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511863755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot
p_reset.511863755
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.915393627
Short name T601
Test name
Test status
Simulation time 50665300 ps
CPU time 154.61 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:13:36 PM PDT 24
Peak memory 261296 kb
Host smart-29e0d428-2a72-46fa-8c36-8c28a9b117e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915393627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.915393627
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2223504469
Short name T738
Test name
Test status
Simulation time 315603700 ps
CPU time 13.59 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:11:14 PM PDT 24
Peak memory 264764 kb
Host smart-6554b1b7-cbcb-41d8-97c9-7d27a15db41d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223504469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2223504469
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1196007943
Short name T704
Test name
Test status
Simulation time 254226700 ps
CPU time 1022.68 seconds
Started May 30 01:10:57 PM PDT 24
Finished May 30 01:28:00 PM PDT 24
Peak memory 285020 kb
Host smart-e44b0220-4ab9-4c28-b135-322aea12d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196007943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1196007943
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.237361637
Short name T880
Test name
Test status
Simulation time 116741000 ps
CPU time 34.21 seconds
Started May 30 01:10:59 PM PDT 24
Finished May 30 01:11:35 PM PDT 24
Peak memory 264996 kb
Host smart-8ee3e77e-0a4c-495a-b9e3-37e6075b4750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237361637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.237361637
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2944511876
Short name T912
Test name
Test status
Simulation time 3610420800 ps
CPU time 560.39 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 313208 kb
Host smart-2249b265-3129-4e20-9b31-9c61c4be1c87
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944511876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2944511876
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.575826346
Short name T736
Test name
Test status
Simulation time 27758200 ps
CPU time 31.04 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:11:30 PM PDT 24
Peak memory 273100 kb
Host smart-a7cd01d3-3a17-488a-b580-1b4bd57216e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575826346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_rw_evict.575826346
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1509850152
Short name T456
Test name
Test status
Simulation time 271959300 ps
CPU time 31.96 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:11:31 PM PDT 24
Peak memory 274352 kb
Host smart-56436d65-547e-4820-aa1e-1ef086d431f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509850152 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1509850152
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3294374557
Short name T991
Test name
Test status
Simulation time 332940500 ps
CPU time 122.14 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:13:03 PM PDT 24
Peak memory 275816 kb
Host smart-f415d176-f088-44c7-b11e-749ec096c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294374557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3294374557
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.260985165
Short name T550
Test name
Test status
Simulation time 12105021300 ps
CPU time 221.5 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 264780 kb
Host smart-3f39d436-04b7-4826-919c-c7af65865b13
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260985165 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.260985165
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.94738735
Short name T812
Test name
Test status
Simulation time 31206600 ps
CPU time 13.55 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:29 PM PDT 24
Peak memory 264776 kb
Host smart-351c50d3-a202-43be-9191-43b947e240ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94738735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.94738735
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.4191645840
Short name T709
Test name
Test status
Simulation time 13815500 ps
CPU time 13.31 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 275536 kb
Host smart-2a32e370-754e-4f7e-b847-393141b01256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191645840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.4191645840
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.2281141281
Short name T138
Test name
Test status
Simulation time 28010900 ps
CPU time 20.77 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 279980 kb
Host smart-d45d664e-e8db-47eb-bd22-c7cafc270df2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281141281 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.2281141281
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1527704854
Short name T507
Test name
Test status
Simulation time 10013236400 ps
CPU time 108.62 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:13:03 PM PDT 24
Peak memory 323672 kb
Host smart-d42a17ee-344f-4a8a-851e-52d56c67aa2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527704854 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1527704854
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.3208635306
Short name T1037
Test name
Test status
Simulation time 25817500 ps
CPU time 13.25 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:28 PM PDT 24
Peak memory 264708 kb
Host smart-bf415640-7aee-4252-a591-1d3d3c0be2f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208635306 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.3208635306
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2176534792
Short name T146
Test name
Test status
Simulation time 100157219300 ps
CPU time 881.46 seconds
Started May 30 01:11:02 PM PDT 24
Finished May 30 01:25:45 PM PDT 24
Peak memory 264092 kb
Host smart-620659ad-8191-4888-aa79-86967f3742f0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176534792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.2176534792
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2305981190
Short name T743
Test name
Test status
Simulation time 14077298100 ps
CPU time 127.49 seconds
Started May 30 01:10:58 PM PDT 24
Finished May 30 01:13:06 PM PDT 24
Peak memory 262292 kb
Host smart-7152ae58-8135-4340-af23-377cd1104673
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305981190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2305981190
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.153601209
Short name T496
Test name
Test status
Simulation time 2397218800 ps
CPU time 145.89 seconds
Started May 30 01:11:14 PM PDT 24
Finished May 30 01:13:42 PM PDT 24
Peak memory 292616 kb
Host smart-03f92ada-981d-4beb-965d-96a8a947cb09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153601209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_intr_rd.153601209
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3562069089
Short name T324
Test name
Test status
Simulation time 8191045200 ps
CPU time 208.23 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 283976 kb
Host smart-ec5116eb-ce69-4ea3-b2f8-b3a9279d35bf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562069089 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3562069089
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.3740163372
Short name T110
Test name
Test status
Simulation time 3904075000 ps
CPU time 89.19 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 260452 kb
Host smart-6ec97a68-be48-436d-a5e5-cc751b1456c4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740163372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3
740163372
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1694196866
Short name T86
Test name
Test status
Simulation time 55442232000 ps
CPU time 295.85 seconds
Started May 30 01:11:16 PM PDT 24
Finished May 30 01:16:14 PM PDT 24
Peak memory 272936 kb
Host smart-77958a10-8761-4e8b-b059-6b233c97116b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694196866 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.1694196866
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2103624677
Short name T828
Test name
Test status
Simulation time 64761800 ps
CPU time 133.32 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:13:14 PM PDT 24
Peak memory 264012 kb
Host smart-f702d0fb-fddd-488e-95e8-85c51c21eff7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103624677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2103624677
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1563429583
Short name T186
Test name
Test status
Simulation time 119225300 ps
CPU time 274.83 seconds
Started May 30 01:11:00 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 264892 kb
Host smart-16dd019f-d584-47c6-b25c-3d453f91efa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563429583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1563429583
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.805566703
Short name T761
Test name
Test status
Simulation time 19366300 ps
CPU time 13.32 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:11:25 PM PDT 24
Peak memory 258352 kb
Host smart-b2f93826-da42-49c4-913e-ffd3dde86b82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805566703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_res
et.805566703
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.394276367
Short name T674
Test name
Test status
Simulation time 722668000 ps
CPU time 880.9 seconds
Started May 30 01:11:01 PM PDT 24
Finished May 30 01:25:43 PM PDT 24
Peak memory 282392 kb
Host smart-f7c2ce72-15bf-4e8a-a8e8-a15fe5050b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394276367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.394276367
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.2406146647
Short name T936
Test name
Test status
Simulation time 420321500 ps
CPU time 36.92 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:50 PM PDT 24
Peak memory 273056 kb
Host smart-970a24c4-cc22-495f-91c3-9095b9526007
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406146647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.2406146647
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.4269955160
Short name T686
Test name
Test status
Simulation time 493367700 ps
CPU time 118.95 seconds
Started May 30 01:11:14 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 280656 kb
Host smart-2fa5166a-aba9-4b62-af2d-7acba22d651e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269955160 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.4269955160
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1582252813
Short name T797
Test name
Test status
Simulation time 4955304100 ps
CPU time 602.07 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:21:17 PM PDT 24
Peak memory 314100 kb
Host smart-e4c9b6d9-6c8f-4a48-bdaf-7cd5289e3c7d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582252813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.1582252813
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.2747762355
Short name T1053
Test name
Test status
Simulation time 44992900 ps
CPU time 31.52 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:47 PM PDT 24
Peak memory 272996 kb
Host smart-e6f9402d-e2f7-4166-ad91-9b4e21b29a5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747762355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.2747762355
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3390671644
Short name T690
Test name
Test status
Simulation time 31181400 ps
CPU time 30.84 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:45 PM PDT 24
Peak memory 274372 kb
Host smart-2db6e355-14e0-4724-804a-d634fbaafb51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390671644 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3390671644
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.3311211298
Short name T147
Test name
Test status
Simulation time 1728992200 ps
CPU time 50.3 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:12:02 PM PDT 24
Peak memory 262212 kb
Host smart-c45c286d-d345-4188-8731-11ea8f75c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311211298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3311211298
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2769601370
Short name T428
Test name
Test status
Simulation time 91361200 ps
CPU time 97.79 seconds
Started May 30 01:11:03 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 275092 kb
Host smart-03f88b55-7aef-48de-91b8-a813ea0b3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769601370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2769601370
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3860335868
Short name T762
Test name
Test status
Simulation time 47439500 ps
CPU time 13.56 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 257644 kb
Host smart-1394c31c-a7f7-45a2-8cb1-6e89bba1035b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860335868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3860335868
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.89148100
Short name T622
Test name
Test status
Simulation time 22819300 ps
CPU time 15.64 seconds
Started May 30 01:11:18 PM PDT 24
Finished May 30 01:11:35 PM PDT 24
Peak memory 275376 kb
Host smart-916ef304-e9f5-43d5-98af-42514dd25dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89148100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.89148100
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2151326359
Short name T859
Test name
Test status
Simulation time 10054542100 ps
CPU time 76.77 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:12:30 PM PDT 24
Peak memory 265892 kb
Host smart-4d95b244-c9cc-4e2e-a4c6-24f96907fce4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151326359 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2151326359
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1841743186
Short name T670
Test name
Test status
Simulation time 48565500 ps
CPU time 13.6 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:29 PM PDT 24
Peak memory 265028 kb
Host smart-f691c1ba-ecea-4018-842f-a8550ec5b5bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841743186 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1841743186
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1443073225
Short name T723
Test name
Test status
Simulation time 8188155100 ps
CPU time 82.65 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:12:38 PM PDT 24
Peak memory 262288 kb
Host smart-51a1e65e-af2c-421f-87ba-87b2ec0912c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443073225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.1443073225
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.2264280253
Short name T1039
Test name
Test status
Simulation time 2384994300 ps
CPU time 137.23 seconds
Started May 30 01:11:14 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 292700 kb
Host smart-925d7e11-4d1a-4e2f-8ce1-3128244d51eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264280253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.2264280253
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3123449814
Short name T718
Test name
Test status
Simulation time 26399033200 ps
CPU time 355.08 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 292956 kb
Host smart-ab88eafe-fa93-4eb9-9871-9a24d6115327
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123449814 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.3123449814
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3786409185
Short name T568
Test name
Test status
Simulation time 4029427200 ps
CPU time 92.12 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:12:47 PM PDT 24
Peak memory 259552 kb
Host smart-f8868468-96e3-4a54-a279-8920ac2fbc92
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786409185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
786409185
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.4288782037
Short name T419
Test name
Test status
Simulation time 15227100 ps
CPU time 13.28 seconds
Started May 30 01:11:18 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 264672 kb
Host smart-64f392e0-0eb7-4dc8-91f6-a669df417bf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288782037 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.4288782037
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.3127950501
Short name T898
Test name
Test status
Simulation time 4784401400 ps
CPU time 210.29 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 262508 kb
Host smart-9eea225b-77a0-49a2-8ce0-5d6b5de51171
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127950501 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.3127950501
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.764314508
Short name T937
Test name
Test status
Simulation time 150867500 ps
CPU time 132.01 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:13:27 PM PDT 24
Peak memory 259436 kb
Host smart-2ff5cc49-70be-4f4d-8edb-afe59b17783a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764314508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.764314508
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3517868123
Short name T154
Test name
Test status
Simulation time 106957400 ps
CPU time 57.6 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:12:11 PM PDT 24
Peak memory 262128 kb
Host smart-3bc5530b-e872-43d1-b37b-6873f8c9e5b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517868123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3517868123
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.892661969
Short name T853
Test name
Test status
Simulation time 19503400 ps
CPU time 13.54 seconds
Started May 30 01:11:12 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 258240 kb
Host smart-70f4a8c0-1bde-4630-8950-8ce057e4b796
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892661969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_res
et.892661969
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.2815175773
Short name T117
Test name
Test status
Simulation time 593707000 ps
CPU time 689.14 seconds
Started May 30 01:11:15 PM PDT 24
Finished May 30 01:22:45 PM PDT 24
Peak memory 282548 kb
Host smart-1ef26610-bdea-4342-938d-fd9b01b46afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815175773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2815175773
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2178542306
Short name T458
Test name
Test status
Simulation time 337945200 ps
CPU time 35.84 seconds
Started May 30 01:11:18 PM PDT 24
Finished May 30 01:11:55 PM PDT 24
Peak memory 266944 kb
Host smart-e4913f27-a73a-4828-b4ad-4054ac6269ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178542306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2178542306
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.539514655
Short name T554
Test name
Test status
Simulation time 15080304600 ps
CPU time 549.75 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 309104 kb
Host smart-07488aea-a817-4572-b6dc-fa1c763cda4a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539514655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_rw.539514655
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.19879383
Short name T181
Test name
Test status
Simulation time 39265600 ps
CPU time 30.89 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:11:46 PM PDT 24
Peak memory 272964 kb
Host smart-412117ae-087f-4ebf-ad00-13ce7cee91ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flas
h_ctrl_rw_evict.19879383
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.3497877023
Short name T398
Test name
Test status
Simulation time 4049516400 ps
CPU time 93.57 seconds
Started May 30 01:11:16 PM PDT 24
Finished May 30 01:12:51 PM PDT 24
Peak memory 262204 kb
Host smart-a6058ecb-32bc-44ec-a36b-c86786d1d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497877023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3497877023
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.3930920355
Short name T375
Test name
Test status
Simulation time 51604500 ps
CPU time 196.23 seconds
Started May 30 01:11:11 PM PDT 24
Finished May 30 01:14:28 PM PDT 24
Peak memory 279688 kb
Host smart-4d085439-0947-4b1f-8664-4d6df307ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930920355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3930920355
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3823193513
Short name T272
Test name
Test status
Simulation time 6865120000 ps
CPU time 216.7 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 258524 kb
Host smart-4494a565-15e8-49e1-b7a3-fe4d091d7809
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823193513 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.3823193513
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.342109143
Short name T918
Test name
Test status
Simulation time 454982400 ps
CPU time 13.57 seconds
Started May 30 01:11:30 PM PDT 24
Finished May 30 01:11:45 PM PDT 24
Peak memory 264812 kb
Host smart-fce1ec5f-9989-40b5-9ad4-21e770cb5820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342109143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.342109143
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.1480656371
Short name T193
Test name
Test status
Simulation time 29827800 ps
CPU time 13.28 seconds
Started May 30 01:11:28 PM PDT 24
Finished May 30 01:11:42 PM PDT 24
Peak memory 275780 kb
Host smart-903f0cf6-d6ce-4fd0-b21f-263e76b050c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480656371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1480656371
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.2207959133
Short name T721
Test name
Test status
Simulation time 12663800 ps
CPU time 21.68 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:11:50 PM PDT 24
Peak memory 279932 kb
Host smart-7f5e384a-54a6-49d8-8d66-da6d5257e45d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207959133 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.2207959133
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2100328157
Short name T278
Test name
Test status
Simulation time 10035664200 ps
CPU time 99.28 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:13:09 PM PDT 24
Peak memory 273788 kb
Host smart-84c1f204-8535-4066-bacf-a464e57408f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100328157 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2100328157
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.503171669
Short name T354
Test name
Test status
Simulation time 15561400 ps
CPU time 13.41 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:11:43 PM PDT 24
Peak memory 258816 kb
Host smart-a1078ee9-31de-4a04-b94e-4cca1c01a231
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503171669 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.503171669
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.4217637474
Short name T386
Test name
Test status
Simulation time 50128302000 ps
CPU time 874.58 seconds
Started May 30 01:11:28 PM PDT 24
Finished May 30 01:26:04 PM PDT 24
Peak memory 263196 kb
Host smart-9467f00b-d69f-44ce-91ec-40d48955feae
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217637474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.4217637474
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.60960233
Short name T434
Test name
Test status
Simulation time 7084967700 ps
CPU time 133.93 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:13:44 PM PDT 24
Peak memory 262328 kb
Host smart-78d4abe3-76e9-47bd-978f-88d79dd094bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60960233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw
_sec_otp.60960233
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.24893867
Short name T816
Test name
Test status
Simulation time 3562739500 ps
CPU time 198.47 seconds
Started May 30 01:11:28 PM PDT 24
Finished May 30 01:14:47 PM PDT 24
Peak memory 289452 kb
Host smart-cc8a1822-f93a-4efd-aca8-ff75a1dea7f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash
_ctrl_intr_rd.24893867
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3144482076
Short name T466
Test name
Test status
Simulation time 33923901100 ps
CPU time 159.25 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:14:08 PM PDT 24
Peak memory 291972 kb
Host smart-dfb18313-ad55-4a78-a436-33a24a9c6a85
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144482076 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3144482076
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1301600380
Short name T443
Test name
Test status
Simulation time 1009827600 ps
CPU time 91.09 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:12:59 PM PDT 24
Peak memory 260272 kb
Host smart-88b4b308-0316-4024-b841-40f64bb18085
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301600380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
301600380
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2062840729
Short name T916
Test name
Test status
Simulation time 81201800 ps
CPU time 13.3 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:11:43 PM PDT 24
Peak memory 260124 kb
Host smart-d1ec4e0e-8eec-43eb-96e6-612151d589a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062840729 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2062840729
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.4062897538
Short name T378
Test name
Test status
Simulation time 13725345300 ps
CPU time 126.15 seconds
Started May 30 01:11:26 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 262572 kb
Host smart-b282f890-9e65-4797-8755-02d535130b38
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062897538 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.4062897538
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3542557641
Short name T1029
Test name
Test status
Simulation time 149763400 ps
CPU time 129.16 seconds
Started May 30 01:11:26 PM PDT 24
Finished May 30 01:13:36 PM PDT 24
Peak memory 260844 kb
Host smart-8a39ff36-d2d7-49d3-8045-e23d23592485
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542557641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3542557641
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.1648271749
Short name T1058
Test name
Test status
Simulation time 123376000 ps
CPU time 146.78 seconds
Started May 30 01:11:15 PM PDT 24
Finished May 30 01:13:43 PM PDT 24
Peak memory 262052 kb
Host smart-0a5cb3d6-4598-4640-b4cb-ece869e4efa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648271749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1648271749
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.2155110392
Short name T665
Test name
Test status
Simulation time 63160700 ps
CPU time 13.32 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:11:43 PM PDT 24
Peak memory 258420 kb
Host smart-b4331b4c-481e-45c5-8d8d-171ffed5d0aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155110392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.2155110392
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.2437747045
Short name T636
Test name
Test status
Simulation time 1139766600 ps
CPU time 1198.63 seconds
Started May 30 01:11:13 PM PDT 24
Finished May 30 01:31:14 PM PDT 24
Peak memory 286524 kb
Host smart-b60c33a6-8610-4121-abc7-9f943acc8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437747045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2437747045
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3740930206
Short name T326
Test name
Test status
Simulation time 97287400 ps
CPU time 36.31 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:12:05 PM PDT 24
Peak memory 274332 kb
Host smart-7b0379d3-a99a-4c05-a758-1d76d064f7be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740930206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3740930206
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1166371785
Short name T808
Test name
Test status
Simulation time 507103100 ps
CPU time 107.35 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 280716 kb
Host smart-0d83b101-834f-4abe-aa81-a0c533394493
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166371785 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.1166371785
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2964328435
Short name T836
Test name
Test status
Simulation time 85500700 ps
CPU time 31.53 seconds
Started May 30 01:11:28 PM PDT 24
Finished May 30 01:12:00 PM PDT 24
Peak memory 275160 kb
Host smart-7cb243c6-880f-425f-b6a0-e0a08e31f19c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964328435 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2964328435
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.579123457
Short name T312
Test name
Test status
Simulation time 12696551500 ps
CPU time 74.85 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:12:45 PM PDT 24
Peak memory 263036 kb
Host smart-bd626dbf-56c4-4ecc-a6f3-1915ca8cdf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579123457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.579123457
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.1005814469
Short name T860
Test name
Test status
Simulation time 1394604000 ps
CPU time 82.2 seconds
Started May 30 01:11:17 PM PDT 24
Finished May 30 01:12:40 PM PDT 24
Peak memory 276508 kb
Host smart-8398e6ff-d0a0-44fa-b87c-c35932102c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005814469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1005814469
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.472331613
Short name T467
Test name
Test status
Simulation time 9327824100 ps
CPU time 205.23 seconds
Started May 30 01:11:26 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 264820 kb
Host smart-eafbf940-3c5f-4236-996b-57905e0da7e9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472331613 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.flash_ctrl_wo.472331613
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2046254071
Short name T3
Test name
Test status
Simulation time 41009400 ps
CPU time 13.78 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:11:55 PM PDT 24
Peak memory 257812 kb
Host smart-5c77118a-e6ce-4ce1-b5d3-5d3e843cdf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046254071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2046254071
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.4121632812
Short name T869
Test name
Test status
Simulation time 34730500 ps
CPU time 15.74 seconds
Started May 30 01:11:43 PM PDT 24
Finished May 30 01:11:59 PM PDT 24
Peak memory 275468 kb
Host smart-51706938-fd77-4b9f-b823-0c728c310509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121632812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.4121632812
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3433275468
Short name T745
Test name
Test status
Simulation time 10027144300 ps
CPU time 67.32 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 300112 kb
Host smart-52914820-d99c-4d09-bc1f-99f381bd7826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433275468 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3433275468
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.162296352
Short name T710
Test name
Test status
Simulation time 148715700 ps
CPU time 13.38 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:11:54 PM PDT 24
Peak memory 257988 kb
Host smart-af6f0f55-3392-475b-b46a-15ad1b46a998
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162296352 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.162296352
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.3799208998
Short name T526
Test name
Test status
Simulation time 90147979500 ps
CPU time 889.88 seconds
Started May 30 01:11:34 PM PDT 24
Finished May 30 01:26:24 PM PDT 24
Peak memory 263624 kb
Host smart-4d3c1350-07f7-40e1-b1cf-c345b9158627
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799208998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.3799208998
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3880469936
Short name T705
Test name
Test status
Simulation time 2410321900 ps
CPU time 204.71 seconds
Started May 30 01:11:28 PM PDT 24
Finished May 30 01:14:53 PM PDT 24
Peak memory 262280 kb
Host smart-9ae2349c-2c34-4fd0-8e5c-50fdd5b70d94
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880469936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.3880469936
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.4026422024
Short name T273
Test name
Test status
Simulation time 1131499000 ps
CPU time 140.88 seconds
Started May 30 01:11:30 PM PDT 24
Finished May 30 01:13:52 PM PDT 24
Peak memory 292612 kb
Host smart-8b51d3c3-8ca2-40b7-8447-21e91d7373ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026422024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.4026422024
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.105191591
Short name T533
Test name
Test status
Simulation time 46516052900 ps
CPU time 291.43 seconds
Started May 30 01:11:31 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 291356 kb
Host smart-c7e281d4-7a9c-4a65-9bbf-d150907f671f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105191591 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.105191591
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.3471804700
Short name T726
Test name
Test status
Simulation time 11576994700 ps
CPU time 68.27 seconds
Started May 30 01:11:30 PM PDT 24
Finished May 30 01:12:39 PM PDT 24
Peak memory 260324 kb
Host smart-76594040-2cae-45f5-a3ee-b7a13d935b46
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471804700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3
471804700
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3868772194
Short name T282
Test name
Test status
Simulation time 138866200 ps
CPU time 13.78 seconds
Started May 30 01:11:41 PM PDT 24
Finished May 30 01:11:56 PM PDT 24
Peak memory 259224 kb
Host smart-bb4dee62-18e4-40f9-82a8-f75a5114efb0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868772194 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3868772194
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1061261529
Short name T103
Test name
Test status
Simulation time 9434987100 ps
CPU time 283.5 seconds
Started May 30 01:11:34 PM PDT 24
Finished May 30 01:16:18 PM PDT 24
Peak memory 273424 kb
Host smart-2f59dbe7-d422-4b30-973b-466fdd93a730
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061261529 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1061261529
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2153280760
Short name T473
Test name
Test status
Simulation time 138471700 ps
CPU time 132.08 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:13:42 PM PDT 24
Peak memory 259524 kb
Host smart-35644341-284f-4efa-94e9-e2f63069b6c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153280760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2153280760
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.4026843399
Short name T842
Test name
Test status
Simulation time 2016265900 ps
CPU time 280.11 seconds
Started May 30 01:11:34 PM PDT 24
Finished May 30 01:16:15 PM PDT 24
Peak memory 264872 kb
Host smart-3f3133e8-a03a-43bb-b9a1-1def9ada476d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026843399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.4026843399
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.3862634995
Short name T844
Test name
Test status
Simulation time 34136400 ps
CPU time 13.54 seconds
Started May 30 01:11:36 PM PDT 24
Finished May 30 01:11:50 PM PDT 24
Peak memory 258260 kb
Host smart-bfe83772-ef0d-449b-8f8b-8785f46e1188
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862634995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.3862634995
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3153580839
Short name T88
Test name
Test status
Simulation time 713178100 ps
CPU time 763.87 seconds
Started May 30 01:11:27 PM PDT 24
Finished May 30 01:24:12 PM PDT 24
Peak memory 282592 kb
Host smart-3fc941fe-2486-49eb-be5e-6386fedae3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153580839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3153580839
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.3017960013
Short name T502
Test name
Test status
Simulation time 72063600 ps
CPU time 35.15 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:12:16 PM PDT 24
Peak memory 269632 kb
Host smart-4fce1945-8c4a-492e-8d1b-5147b31b6d59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017960013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.3017960013
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2377230597
Short name T640
Test name
Test status
Simulation time 1075053700 ps
CPU time 117.64 seconds
Started May 30 01:11:35 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 296872 kb
Host smart-3985e2ad-5225-46d2-8415-d70374955cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377230597 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2377230597
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2110340434
Short name T188
Test name
Test status
Simulation time 18954263500 ps
CPU time 460.36 seconds
Started May 30 01:11:34 PM PDT 24
Finished May 30 01:19:16 PM PDT 24
Peak memory 313468 kb
Host smart-088f0564-f51f-4e99-9963-dd60c325c8fd
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110340434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.2110340434
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.1297006191
Short name T925
Test name
Test status
Simulation time 32109200 ps
CPU time 31.44 seconds
Started May 30 01:11:36 PM PDT 24
Finished May 30 01:12:08 PM PDT 24
Peak memory 273116 kb
Host smart-5e2239dc-2357-48cf-a79e-5ce13f8695e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297006191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.1297006191
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.4179760247
Short name T573
Test name
Test status
Simulation time 44333800 ps
CPU time 31.23 seconds
Started May 30 01:11:33 PM PDT 24
Finished May 30 01:12:05 PM PDT 24
Peak memory 275156 kb
Host smart-9d42b761-f3a5-4633-b802-93069b3e6cdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179760247 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.4179760247
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1348348517
Short name T404
Test name
Test status
Simulation time 17056852700 ps
CPU time 82.63 seconds
Started May 30 01:11:43 PM PDT 24
Finished May 30 01:13:06 PM PDT 24
Peak memory 262132 kb
Host smart-1c9109c2-87fa-4199-a22c-39f055abbb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348348517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1348348517
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.702757532
Short name T692
Test name
Test status
Simulation time 103446000 ps
CPU time 147.29 seconds
Started May 30 01:11:33 PM PDT 24
Finished May 30 01:14:01 PM PDT 24
Peak memory 277136 kb
Host smart-78eac366-ee20-4f15-8be3-5f5a391d76b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702757532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.702757532
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.3016460638
Short name T661
Test name
Test status
Simulation time 2388782900 ps
CPU time 163.22 seconds
Started May 30 01:11:29 PM PDT 24
Finished May 30 01:14:13 PM PDT 24
Peak memory 258520 kb
Host smart-32eb8de4-b216-464b-86ff-7f1744eca216
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016460638 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.3016460638
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3324751684
Short name T1024
Test name
Test status
Simulation time 106731000 ps
CPU time 13.61 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:12:10 PM PDT 24
Peak memory 257844 kb
Host smart-44dcce59-2ab0-4c8f-9a34-6e2a40977ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324751684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3324751684
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2240590341
Short name T609
Test name
Test status
Simulation time 22497300 ps
CPU time 15.35 seconds
Started May 30 01:11:42 PM PDT 24
Finished May 30 01:11:59 PM PDT 24
Peak memory 275844 kb
Host smart-e9f0c0e8-ab9e-4567-af5c-7ccfee83489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240590341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2240590341
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.3275498168
Short name T873
Test name
Test status
Simulation time 11018600 ps
CPU time 22.63 seconds
Started May 30 01:11:39 PM PDT 24
Finished May 30 01:12:02 PM PDT 24
Peak memory 264812 kb
Host smart-ba6aa44f-22d9-4464-82f0-76be03b8d246
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275498168 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.3275498168
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2581815557
Short name T355
Test name
Test status
Simulation time 15254600 ps
CPU time 13.37 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:12:10 PM PDT 24
Peak memory 264696 kb
Host smart-197e36d2-6a76-4cbe-acbf-76f84c9e4519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581815557 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2581815557
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2183220480
Short name T132
Test name
Test status
Simulation time 160176439100 ps
CPU time 899.99 seconds
Started May 30 01:11:38 PM PDT 24
Finished May 30 01:26:39 PM PDT 24
Peak memory 263060 kb
Host smart-bb54cb5e-a459-4432-ab40-9e4249e2fe7b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183220480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.2183220480
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2834458086
Short name T917
Test name
Test status
Simulation time 7255998000 ps
CPU time 76.05 seconds
Started May 30 01:11:47 PM PDT 24
Finished May 30 01:13:04 PM PDT 24
Peak memory 262376 kb
Host smart-21ab799e-9e14-4a97-89a7-113272e0a2b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834458086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2834458086
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.155410318
Short name T352
Test name
Test status
Simulation time 774572600 ps
CPU time 128.59 seconds
Started May 30 01:11:44 PM PDT 24
Finished May 30 01:13:53 PM PDT 24
Peak memory 290472 kb
Host smart-cc107e7f-8986-454a-aca4-6a47453e0ffe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155410318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.155410318
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3625836687
Short name T865
Test name
Test status
Simulation time 5687580900 ps
CPU time 126.23 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:13:47 PM PDT 24
Peak memory 291620 kb
Host smart-aefbd154-1181-4503-9615-fbde725e6a26
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625836687 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3625836687
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.1133947522
Short name T675
Test name
Test status
Simulation time 6539150300 ps
CPU time 64.1 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:12:45 PM PDT 24
Peak memory 260368 kb
Host smart-b35548b6-dd46-4952-a8e7-4a152c5598df
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133947522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1
133947522
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2585127290
Short name T792
Test name
Test status
Simulation time 79645100 ps
CPU time 13.36 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:12:08 PM PDT 24
Peak memory 259188 kb
Host smart-ff4a029a-5f32-4a07-a4fe-68eac14506c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585127290 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2585127290
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1890682296
Short name T958
Test name
Test status
Simulation time 23576699800 ps
CPU time 742.54 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:24:04 PM PDT 24
Peak memory 273392 kb
Host smart-e2394dca-92a9-4ef4-91dd-9fbed19dbe5b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890682296 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.1890682296
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.3086442897
Short name T920
Test name
Test status
Simulation time 40079300 ps
CPU time 131.5 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:13:53 PM PDT 24
Peak memory 259896 kb
Host smart-aa9c4986-590d-4653-b0c9-9dabf8e47e8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086442897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.3086442897
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.248747092
Short name T187
Test name
Test status
Simulation time 129189600 ps
CPU time 111.58 seconds
Started May 30 01:11:42 PM PDT 24
Finished May 30 01:13:35 PM PDT 24
Peak memory 264864 kb
Host smart-0ca556d7-fced-4666-b7c1-4c8612f5c7ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248747092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.248747092
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2900939859
Short name T572
Test name
Test status
Simulation time 7940000100 ps
CPU time 173.37 seconds
Started May 30 01:11:42 PM PDT 24
Finished May 30 01:14:36 PM PDT 24
Peak memory 264840 kb
Host smart-b4cefed4-13e4-4014-9fc1-010f0fbc0a7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900939859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2900939859
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2172962984
Short name T750
Test name
Test status
Simulation time 174219500 ps
CPU time 758.92 seconds
Started May 30 01:11:39 PM PDT 24
Finished May 30 01:24:19 PM PDT 24
Peak memory 282596 kb
Host smart-638d682e-4ddd-4391-9fb5-ceaffffeb763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172962984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2172962984
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3280884925
Short name T486
Test name
Test status
Simulation time 184629000 ps
CPU time 37.68 seconds
Started May 30 01:11:41 PM PDT 24
Finished May 30 01:12:20 PM PDT 24
Peak memory 273056 kb
Host smart-c7863816-5e09-4d12-a1b2-f5de34f0928d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280884925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3280884925
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2704375987
Short name T1082
Test name
Test status
Simulation time 2321589600 ps
CPU time 119.85 seconds
Started May 30 01:11:39 PM PDT 24
Finished May 30 01:13:40 PM PDT 24
Peak memory 281320 kb
Host smart-3b00d40e-3b09-42f8-bf5d-cd0389f4d130
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704375987 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2704375987
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2341612596
Short name T984
Test name
Test status
Simulation time 3465452900 ps
CPU time 558.04 seconds
Started May 30 01:11:39 PM PDT 24
Finished May 30 01:20:58 PM PDT 24
Peak memory 314048 kb
Host smart-40d5748a-846b-4af2-9f30-b3c5c005855c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341612596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2341612596
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.916051131
Short name T739
Test name
Test status
Simulation time 29325500 ps
CPU time 31.16 seconds
Started May 30 01:11:40 PM PDT 24
Finished May 30 01:12:12 PM PDT 24
Peak memory 273428 kb
Host smart-c10f2811-9d43-4089-80c6-e72b2135bd02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916051131 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.916051131
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1639117076
Short name T775
Test name
Test status
Simulation time 1699782000 ps
CPU time 58.59 seconds
Started May 30 01:11:43 PM PDT 24
Finished May 30 01:12:42 PM PDT 24
Peak memory 262168 kb
Host smart-ad811752-1c13-445d-a2b3-aca952f73351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639117076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1639117076
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1199817497
Short name T1086
Test name
Test status
Simulation time 183716800 ps
CPU time 74.77 seconds
Started May 30 01:11:42 PM PDT 24
Finished May 30 01:12:58 PM PDT 24
Peak memory 275896 kb
Host smart-d6cfdec2-d51c-4207-b9d5-78300ce7ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199817497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1199817497
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.3755403075
Short name T268
Test name
Test status
Simulation time 3215404800 ps
CPU time 142.55 seconds
Started May 30 01:11:42 PM PDT 24
Finished May 30 01:14:06 PM PDT 24
Peak memory 264756 kb
Host smart-c6719f1b-120d-42c2-b8d7-ec65e220667e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755403075 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.3755403075
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.4225764628
Short name T462
Test name
Test status
Simulation time 67251100 ps
CPU time 14.04 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:12:10 PM PDT 24
Peak memory 264812 kb
Host smart-ebdaced7-2ce0-4df2-ba7f-326b5887ceb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225764628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
4225764628
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.657512138
Short name T1001
Test name
Test status
Simulation time 13273800 ps
CPU time 15.75 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:12:12 PM PDT 24
Peak memory 275872 kb
Host smart-3104b11b-dcf8-4db7-a9b8-431e77580f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657512138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.657512138
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1800082138
Short name T384
Test name
Test status
Simulation time 10373700 ps
CPU time 21.8 seconds
Started May 30 01:11:53 PM PDT 24
Finished May 30 01:12:15 PM PDT 24
Peak memory 264336 kb
Host smart-cc35a111-1080-45b4-bf56-3f2f024c5f80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800082138 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1800082138
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2716298279
Short name T277
Test name
Test status
Simulation time 10012221100 ps
CPU time 103.86 seconds
Started May 30 01:11:56 PM PDT 24
Finished May 30 01:13:41 PM PDT 24
Peak memory 275800 kb
Host smart-b13ccbd9-a5de-4985-81f5-1ef1f07b7d16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716298279 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2716298279
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.4166441109
Short name T82
Test name
Test status
Simulation time 47112700 ps
CPU time 14.03 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:12:10 PM PDT 24
Peak memory 264744 kb
Host smart-cf12c401-6776-4a03-a7c6-c05be307c2c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166441109 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.4166441109
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.597411139
Short name T1051
Test name
Test status
Simulation time 80138314200 ps
CPU time 829.19 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:25:46 PM PDT 24
Peak memory 264072 kb
Host smart-8787453a-f9ab-42eb-9c3d-6201f49bc26e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597411139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_hw_rma_reset.597411139
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1503586030
Short name T478
Test name
Test status
Simulation time 1369518300 ps
CPU time 51.14 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:12:47 PM PDT 24
Peak memory 262440 kb
Host smart-7afb8aa4-1972-4caa-9976-98f69856161f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503586030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1503586030
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2891022613
Short name T1073
Test name
Test status
Simulation time 6346163000 ps
CPU time 222.51 seconds
Started May 30 01:11:56 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 289452 kb
Host smart-1bcfa2a2-5cee-423a-bde3-2a697b78ab9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891022613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2891022613
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.379211247
Short name T450
Test name
Test status
Simulation time 23692003000 ps
CPU time 148.91 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 291568 kb
Host smart-b61826c2-3610-424b-9753-fec030d69e6f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379211247 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.379211247
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.2856298263
Short name T410
Test name
Test status
Simulation time 9105994000 ps
CPU time 60.09 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:12:57 PM PDT 24
Peak memory 260500 kb
Host smart-081e2f92-f6f5-4580-a791-9090aeb72f87
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856298263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2
856298263
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2912016799
Short name T453
Test name
Test status
Simulation time 50725400 ps
CPU time 13.07 seconds
Started May 30 01:11:52 PM PDT 24
Finished May 30 01:12:06 PM PDT 24
Peak memory 260088 kb
Host smart-13f113d4-e660-449e-af1f-cec57c054933
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912016799 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2912016799
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.3781747290
Short name T101
Test name
Test status
Simulation time 15849405300 ps
CPU time 346.25 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:17:42 PM PDT 24
Peak memory 274144 kb
Host smart-45f9e162-2387-4676-a930-75ccb8a4c55f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781747290 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.3781747290
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.4073560040
Short name T694
Test name
Test status
Simulation time 5341777800 ps
CPU time 306.42 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:17:02 PM PDT 24
Peak memory 262088 kb
Host smart-7adec357-4800-45ac-a17a-ccc5fc3dcc58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073560040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.4073560040
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.4066525902
Short name T514
Test name
Test status
Simulation time 3837598600 ps
CPU time 161.51 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:14:37 PM PDT 24
Peak memory 258860 kb
Host smart-93924c73-c682-4c84-a89d-77d9007e7d16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066525902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.4066525902
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2874551755
Short name T506
Test name
Test status
Simulation time 58365400 ps
CPU time 106.5 seconds
Started May 30 01:11:53 PM PDT 24
Finished May 30 01:13:40 PM PDT 24
Peak memory 272612 kb
Host smart-60ae9a8d-9076-4da0-b2e7-d246663c1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874551755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2874551755
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.244454067
Short name T413
Test name
Test status
Simulation time 438402500 ps
CPU time 38.3 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:12:34 PM PDT 24
Peak memory 273112 kb
Host smart-f1d4bdda-b058-4131-9dc5-1c80ea35b677
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244454067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.244454067
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.2566385761
Short name T517
Test name
Test status
Simulation time 2061814500 ps
CPU time 95.88 seconds
Started May 30 01:11:52 PM PDT 24
Finished May 30 01:13:29 PM PDT 24
Peak memory 281336 kb
Host smart-cfb9e978-7714-467e-813b-4353678b748a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566385761 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.2566385761
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.776024950
Short name T660
Test name
Test status
Simulation time 3796694900 ps
CPU time 456.93 seconds
Started May 30 01:11:52 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 309048 kb
Host smart-e412a5cd-b368-482b-815a-774018ccca77
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776024950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_rw.776024950
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1384707104
Short name T1066
Test name
Test status
Simulation time 1006720500 ps
CPU time 59.64 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:12:55 PM PDT 24
Peak memory 263000 kb
Host smart-c6e87870-6fa8-49b9-95be-8f6d95659ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384707104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1384707104
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1940374342
Short name T645
Test name
Test status
Simulation time 26301000 ps
CPU time 98.78 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:13:35 PM PDT 24
Peak memory 275048 kb
Host smart-647702b1-6f76-43da-8cc0-c71ab9a2ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940374342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1940374342
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2763425966
Short name T986
Test name
Test status
Simulation time 10893171100 ps
CPU time 210.39 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:15:26 PM PDT 24
Peak memory 259972 kb
Host smart-d79e9d26-2c46-4020-9ecc-19aa40b246e5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763425966 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.2763425966
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2048554616
Short name T233
Test name
Test status
Simulation time 65297500 ps
CPU time 13.49 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:12:28 PM PDT 24
Peak memory 257848 kb
Host smart-0c9e696d-0a1f-4b1a-9c7e-af10a3fd748b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048554616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2048554616
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.174566176
Short name T943
Test name
Test status
Simulation time 26394500 ps
CPU time 15.39 seconds
Started May 30 01:12:15 PM PDT 24
Finished May 30 01:12:32 PM PDT 24
Peak memory 275780 kb
Host smart-2dbace4e-37d0-43c7-b283-7be54c5a6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174566176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.174566176
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.3113348608
Short name T1036
Test name
Test status
Simulation time 27275100 ps
CPU time 22.33 seconds
Started May 30 01:12:07 PM PDT 24
Finished May 30 01:12:30 PM PDT 24
Peak memory 273168 kb
Host smart-ba3c9a13-2ab9-4591-a9fc-1e0137e599d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113348608 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.3113348608
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.716632220
Short name T651
Test name
Test status
Simulation time 15660500 ps
CPU time 13.34 seconds
Started May 30 01:12:09 PM PDT 24
Finished May 30 01:12:23 PM PDT 24
Peak memory 264732 kb
Host smart-62ab44c8-7f3e-4bf6-af5b-45708518cc47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716632220 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.716632220
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.159236047
Short name T811
Test name
Test status
Simulation time 80148294400 ps
CPU time 824.68 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:25:59 PM PDT 24
Peak memory 263864 kb
Host smart-d1dc9f12-44a2-4697-9fa0-f5218ab00899
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159236047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.159236047
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.148561162
Short name T1000
Test name
Test status
Simulation time 3582098200 ps
CPU time 189.05 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:15:17 PM PDT 24
Peak memory 262292 kb
Host smart-26a03be9-e932-4cf2-a71c-690d9b1ece89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148561162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h
w_sec_otp.148561162
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1334443177
Short name T702
Test name
Test status
Simulation time 23287444700 ps
CPU time 136.05 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:14:30 PM PDT 24
Peak memory 293056 kb
Host smart-545a3edf-d778-4338-92ca-155e72e39b79
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334443177 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1334443177
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2314636538
Short name T1026
Test name
Test status
Simulation time 26539400 ps
CPU time 13.11 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:12:28 PM PDT 24
Peak memory 259300 kb
Host smart-cb60db04-093e-4bf2-b2ca-0cdcea82862f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314636538 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2314636538
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.665698223
Short name T114
Test name
Test status
Simulation time 11388165600 ps
CPU time 330.84 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:17:39 PM PDT 24
Peak memory 274660 kb
Host smart-fbc901d0-24f1-49c9-8206-b3f0f109f189
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665698223 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.665698223
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.2942586836
Short name T299
Test name
Test status
Simulation time 48919600 ps
CPU time 130.9 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:14:20 PM PDT 24
Peak memory 260012 kb
Host smart-3e4e8d5e-630b-4c6d-aed4-7bafc7d7f47b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942586836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.2942586836
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1349468705
Short name T559
Test name
Test status
Simulation time 742346500 ps
CPU time 336.23 seconds
Started May 30 01:12:12 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 262196 kb
Host smart-7353106e-cb5f-4ca6-ad97-fe12a91c03a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349468705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1349468705
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1763559804
Short name T589
Test name
Test status
Simulation time 26047800 ps
CPU time 13.53 seconds
Started May 30 01:12:12 PM PDT 24
Finished May 30 01:12:27 PM PDT 24
Peak memory 258316 kb
Host smart-0dcb6046-3d6c-4e80-9bdb-7ba4c919a050
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763559804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.1763559804
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.783125415
Short name T1088
Test name
Test status
Simulation time 792142900 ps
CPU time 849.23 seconds
Started May 30 01:11:54 PM PDT 24
Finished May 30 01:26:05 PM PDT 24
Peak memory 284276 kb
Host smart-9205cc56-d804-45ce-a05e-e9b8ba5682d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783125415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.783125415
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2515015242
Short name T868
Test name
Test status
Simulation time 144664500 ps
CPU time 33.02 seconds
Started May 30 01:12:09 PM PDT 24
Finished May 30 01:12:43 PM PDT 24
Peak memory 272172 kb
Host smart-91fa573b-ad7e-4bb7-ae27-ca6f9ded30be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515015242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2515015242
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2900818782
Short name T791
Test name
Test status
Simulation time 614615000 ps
CPU time 123.73 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:14:19 PM PDT 24
Peak memory 280708 kb
Host smart-c6be5903-8f0f-4ae3-b525-aa149cb0ae86
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900818782 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2900818782
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1449796906
Short name T1046
Test name
Test status
Simulation time 4245693400 ps
CPU time 577.31 seconds
Started May 30 01:12:11 PM PDT 24
Finished May 30 01:21:49 PM PDT 24
Peak memory 312480 kb
Host smart-01c4874a-fb09-47c8-938e-ea01c934fb26
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449796906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.1449796906
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.712761223
Short name T1035
Test name
Test status
Simulation time 29055700 ps
CPU time 31.36 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:12:40 PM PDT 24
Peak memory 273112 kb
Host smart-61774521-3f88-4364-8ef6-235596e6fde5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712761223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.712761223
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2396231977
Short name T67
Test name
Test status
Simulation time 305667500 ps
CPU time 31.46 seconds
Started May 30 01:12:09 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 274288 kb
Host smart-54f55d35-946b-461d-91f2-8df6a6cae7f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396231977 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2396231977
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.3614233849
Short name T490
Test name
Test status
Simulation time 239444300 ps
CPU time 123.11 seconds
Started May 30 01:11:55 PM PDT 24
Finished May 30 01:13:59 PM PDT 24
Peak memory 278584 kb
Host smart-300faa1a-293b-4d6d-ac20-d8420e18d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614233849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3614233849
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.4020730693
Short name T695
Test name
Test status
Simulation time 9545720200 ps
CPU time 189.78 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:15:25 PM PDT 24
Peak memory 259108 kb
Host smart-77edbd49-0661-4ff7-86c1-cb1610e397bf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020730693 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.4020730693
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.96689715
Short name T987
Test name
Test status
Simulation time 77366500 ps
CPU time 13.74 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:12:36 PM PDT 24
Peak memory 264816 kb
Host smart-edf6cc38-a972-4d80-ae5a-0b5eb1bca9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96689715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.96689715
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.1629470668
Short name T1085
Test name
Test status
Simulation time 16121000 ps
CPU time 15.89 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:12:31 PM PDT 24
Peak memory 274876 kb
Host smart-32aba2e3-63a2-4a3e-8b6d-a4770ea90145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629470668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1629470668
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.3359148828
Short name T307
Test name
Test status
Simulation time 11478000 ps
CPU time 22.42 seconds
Started May 30 01:12:07 PM PDT 24
Finished May 30 01:12:30 PM PDT 24
Peak memory 273176 kb
Host smart-ab3b627b-2bb7-4ffd-a1d3-2a7374474c6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359148828 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.3359148828
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.120882951
Short name T217
Test name
Test status
Simulation time 10014640200 ps
CPU time 114.58 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:14:18 PM PDT 24
Peak memory 351712 kb
Host smart-22b9b9e1-cb96-48b3-a54b-8885ff210337
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120882951 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.120882951
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1368115831
Short name T593
Test name
Test status
Simulation time 63139600 ps
CPU time 13.36 seconds
Started May 30 01:12:20 PM PDT 24
Finished May 30 01:12:35 PM PDT 24
Peak memory 264976 kb
Host smart-aaedf05f-79bc-4b71-af67-5b3299cc1542
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368115831 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1368115831
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2811704626
Short name T143
Test name
Test status
Simulation time 80151966200 ps
CPU time 864.49 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:26:40 PM PDT 24
Peak memory 259700 kb
Host smart-80d5e81b-14c0-4e46-adc7-d60e62a5900f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811704626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2811704626
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1155651209
Short name T492
Test name
Test status
Simulation time 2045445400 ps
CPU time 65.27 seconds
Started May 30 01:12:09 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 262288 kb
Host smart-76024072-86f9-49cf-ae5d-602c6e91d891
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155651209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1155651209
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3512615184
Short name T627
Test name
Test status
Simulation time 7521720200 ps
CPU time 208.47 seconds
Started May 30 01:12:17 PM PDT 24
Finished May 30 01:15:46 PM PDT 24
Peak memory 283668 kb
Host smart-05d850d3-2521-4f8b-ad1d-e2c43cf15e1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512615184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3512615184
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1761166535
Short name T813
Test name
Test status
Simulation time 5875909500 ps
CPU time 139.63 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 293032 kb
Host smart-ea7ea4c7-1fcb-44dc-bc3c-30f1de017518
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761166535 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1761166535
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.680553425
Short name T602
Test name
Test status
Simulation time 4171588900 ps
CPU time 63.92 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:13:18 PM PDT 24
Peak memory 259748 kb
Host smart-8769fbe3-9780-44cb-9eb7-571b3e29d426
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680553425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.680553425
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.3328426365
Short name T452
Test name
Test status
Simulation time 69218200 ps
CPU time 109.84 seconds
Started May 30 01:12:06 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 260924 kb
Host smart-1ab5ebf9-c751-419c-ba91-cab942153d43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328426365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.3328426365
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1625370748
Short name T914
Test name
Test status
Simulation time 96207800 ps
CPU time 463.16 seconds
Started May 30 01:12:13 PM PDT 24
Finished May 30 01:19:58 PM PDT 24
Peak memory 264788 kb
Host smart-d87ddc44-ed19-42b4-ae91-8d87261331d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625370748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1625370748
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.4201114139
Short name T475
Test name
Test status
Simulation time 7959966000 ps
CPU time 144.52 seconds
Started May 30 01:12:12 PM PDT 24
Finished May 30 01:14:38 PM PDT 24
Peak memory 259428 kb
Host smart-040a6bcf-6ba7-4af2-9ae3-c78a759ced16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201114139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.4201114139
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.3677311161
Short name T587
Test name
Test status
Simulation time 63567600 ps
CPU time 197.81 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 274872 kb
Host smart-92120a94-ef64-4ea4-88af-aeb4a96b9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677311161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3677311161
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1272158576
Short name T612
Test name
Test status
Simulation time 1132919700 ps
CPU time 36.74 seconds
Started May 30 01:12:15 PM PDT 24
Finished May 30 01:12:52 PM PDT 24
Peak memory 274136 kb
Host smart-ca348a91-c39b-487d-a195-ec9852697aab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272158576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1272158576
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.1480447977
Short name T652
Test name
Test status
Simulation time 1062636800 ps
CPU time 125.54 seconds
Started May 30 01:12:14 PM PDT 24
Finished May 30 01:14:21 PM PDT 24
Peak memory 281376 kb
Host smart-ae380479-53fb-4f35-b17e-a9f36f0696da
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480447977 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.1480447977
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3167082335
Short name T213
Test name
Test status
Simulation time 7415145500 ps
CPU time 525.28 seconds
Started May 30 01:12:10 PM PDT 24
Finished May 30 01:20:56 PM PDT 24
Peak memory 309148 kb
Host smart-279239a1-850a-442a-9b73-a682ac5467c0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167082335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.3167082335
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.90453656
Short name T588
Test name
Test status
Simulation time 38204700 ps
CPU time 30.56 seconds
Started May 30 01:12:08 PM PDT 24
Finished May 30 01:12:39 PM PDT 24
Peak memory 273108 kb
Host smart-733d5702-8401-4fa7-a4de-3c1afbc7e865
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90453656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_rw_evict.90453656
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.363996120
Short name T931
Test name
Test status
Simulation time 73857500 ps
CPU time 28.49 seconds
Started May 30 01:12:15 PM PDT 24
Finished May 30 01:12:44 PM PDT 24
Peak memory 275868 kb
Host smart-7e1b9c1a-f1aa-4ac6-aaec-134e1cc24bfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363996120 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.363996120
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3150025618
Short name T26
Test name
Test status
Simulation time 1412456800 ps
CPU time 220.01 seconds
Started May 30 01:12:10 PM PDT 24
Finished May 30 01:15:51 PM PDT 24
Peak memory 281188 kb
Host smart-7f858714-2b60-49f6-aef6-dd3e8e643148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150025618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3150025618
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.3880833268
Short name T574
Test name
Test status
Simulation time 1894773500 ps
CPU time 156.94 seconds
Started May 30 01:12:07 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 264796 kb
Host smart-7581c715-3d13-4de3-9e25-963bea3463ab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880833268 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.3880833268
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.3276670701
Short name T727
Test name
Test status
Simulation time 41717600 ps
CPU time 13.56 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:20 PM PDT 24
Peak memory 264800 kb
Host smart-939105ee-1898-4bc9-9fab-d30c1605c6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276670701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3
276670701
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1396633537
Short name T731
Test name
Test status
Simulation time 43372400 ps
CPU time 15.54 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:10:03 PM PDT 24
Peak memory 275652 kb
Host smart-6bf07b92-54ad-42d1-8df1-10fb6caac60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396633537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1396633537
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.1973997024
Short name T913
Test name
Test status
Simulation time 122384300 ps
CPU time 99.66 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:11:48 PM PDT 24
Peak memory 281180 kb
Host smart-f7ef6575-35bd-42ec-91e6-bd327e9641f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973997024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.1973997024
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3991198197
Short name T142
Test name
Test status
Simulation time 27256100 ps
CPU time 22.06 seconds
Started May 30 01:09:43 PM PDT 24
Finished May 30 01:10:06 PM PDT 24
Peak memory 273148 kb
Host smart-ebdc6b93-0642-40a2-b488-fec45a313ce3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991198197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3991198197
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.3220516168
Short name T63
Test name
Test status
Simulation time 3314397400 ps
CPU time 413.14 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 262748 kb
Host smart-471df4cb-543a-4fd5-b9e2-e8d3076d273f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220516168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3220516168
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3454052086
Short name T499
Test name
Test status
Simulation time 5188271000 ps
CPU time 2207.88 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:46:37 PM PDT 24
Peak memory 264628 kb
Host smart-c23cb655-ff23-4eeb-876c-0bce8a3236b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454052086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3454052086
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1484418920
Short name T158
Test name
Test status
Simulation time 600453800 ps
CPU time 1683.24 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:38:08 PM PDT 24
Peak memory 264820 kb
Host smart-dcc9617a-58d4-4827-ab4e-57f81e7f5675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484418920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1484418920
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.3196689782
Short name T551
Test name
Test status
Simulation time 844847000 ps
CPU time 941.25 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:25:34 PM PDT 24
Peak memory 273012 kb
Host smart-6c6ae614-c5bd-448d-b876-0dd00b8b0947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196689782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3196689782
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.1455692891
Short name T56
Test name
Test status
Simulation time 669785500 ps
CPU time 26.07 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:15 PM PDT 24
Peak memory 264740 kb
Host smart-94c2fffc-ef08-48c0-9616-63fd35c8e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455692891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.1455692891
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2627888745
Short name T333
Test name
Test status
Simulation time 2479769000 ps
CPU time 38.81 seconds
Started May 30 01:09:50 PM PDT 24
Finished May 30 01:10:30 PM PDT 24
Peak memory 261544 kb
Host smart-b34b910c-e669-4e76-adb3-c00393c26f21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627888745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2627888745
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.3247954859
Short name T111
Test name
Test status
Simulation time 143803637200 ps
CPU time 4113.54 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 02:18:23 PM PDT 24
Peak memory 264772 kb
Host smart-447edec0-ac6b-4758-b3b0-295d43ee2555
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247954859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.3247954859
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3889723479
Short name T202
Test name
Test status
Simulation time 249094898100 ps
CPU time 2694.36 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:55:00 PM PDT 24
Peak memory 264464 kb
Host smart-78511492-cb8c-440a-ab46-810b6507b331
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889723479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3889723479
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4026856802
Short name T1065
Test name
Test status
Simulation time 36733100 ps
CPU time 58.2 seconds
Started May 30 01:09:52 PM PDT 24
Finished May 30 01:10:52 PM PDT 24
Peak memory 264856 kb
Host smart-4404089a-61c3-4f4b-b40f-43687f6d9566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026856802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4026856802
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.172008965
Short name T889
Test name
Test status
Simulation time 10012549100 ps
CPU time 281.94 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:14:46 PM PDT 24
Peak memory 313316 kb
Host smart-1648a2cd-0fc4-4dca-bfd2-4fd4b5b9f414
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172008965 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.172008965
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2529105287
Short name T886
Test name
Test status
Simulation time 46383900 ps
CPU time 13.25 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:20 PM PDT 24
Peak memory 257864 kb
Host smart-b9928ab9-29a4-4478-a9c0-21faaac36254
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529105287 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2529105287
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.68381033
Short name T98
Test name
Test status
Simulation time 85293939100 ps
CPU time 1784.53 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:39:30 PM PDT 24
Peak memory 263668 kb
Host smart-328eb4bc-94ff-4ca6-8346-4534c50b3e3d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68381033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_hw_rma.68381033
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3428455964
Short name T482
Test name
Test status
Simulation time 40120268900 ps
CPU time 847.12 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:23:56 PM PDT 24
Peak memory 264288 kb
Host smart-0294b7e0-f48d-4a26-b1af-909d9e413985
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428455964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3428455964
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.3240564438
Short name T1054
Test name
Test status
Simulation time 2617175000 ps
CPU time 212.44 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:13:21 PM PDT 24
Peak memory 262308 kb
Host smart-e94ea6ca-95c3-42db-adf9-eaa65b9bb9bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240564438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.3240564438
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2835037463
Short name T239
Test name
Test status
Simulation time 15551396800 ps
CPU time 489.06 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:17:57 PM PDT 24
Peak memory 335560 kb
Host smart-c18feca8-fd13-48d9-8d64-3e93c325aa9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835037463 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2835037463
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2491117746
Short name T707
Test name
Test status
Simulation time 3676975800 ps
CPU time 184.44 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:13:11 PM PDT 24
Peak memory 289436 kb
Host smart-c5d763eb-f8ad-4689-8e9d-2b0ce5652573
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491117746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2491117746
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.4172483189
Short name T547
Test name
Test status
Simulation time 7564984300 ps
CPU time 113.26 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:12:01 PM PDT 24
Peak memory 291604 kb
Host smart-206df05f-3c3a-4ea0-9a8b-bdba2091be92
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172483189 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.4172483189
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.2720041868
Short name T952
Test name
Test status
Simulation time 8784871500 ps
CPU time 64.65 seconds
Started May 30 01:10:00 PM PDT 24
Finished May 30 01:11:05 PM PDT 24
Peak memory 260532 kb
Host smart-bd494be0-ee7a-4931-8df3-dd7e3d0cf059
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720041868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.2720041868
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1492872575
Short name T770
Test name
Test status
Simulation time 75814299700 ps
CPU time 170.47 seconds
Started May 30 01:09:55 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 259924 kb
Host smart-ffdae7b3-864a-470b-ac13-9b25e304a83b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149
2872575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1492872575
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3815425078
Short name T1009
Test name
Test status
Simulation time 23260121400 ps
CPU time 86.05 seconds
Started May 30 01:09:52 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 260448 kb
Host smart-dbaf1398-361f-41be-aded-6c35169b00cc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815425078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3815425078
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1028058468
Short name T595
Test name
Test status
Simulation time 47593800 ps
CPU time 13.47 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:10:00 PM PDT 24
Peak memory 264820 kb
Host smart-21d2d7bb-560f-40b7-9650-90b48d433e95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028058468 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1028058468
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.259230668
Short name T60
Test name
Test status
Simulation time 2559249000 ps
CPU time 68.84 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:10:54 PM PDT 24
Peak memory 260664 kb
Host smart-01b54604-ef70-4098-9bd0-d7a201d13df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259230668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.259230668
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2288801155
Short name T795
Test name
Test status
Simulation time 18861063600 ps
CPU time 137.43 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:12:07 PM PDT 24
Peak memory 261972 kb
Host smart-5432c7ee-0533-46de-a5e8-3a1c3d40c3e1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288801155 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2288801155
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.685358833
Short name T527
Test name
Test status
Simulation time 37603700 ps
CPU time 112.09 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:11:41 PM PDT 24
Peak memory 259552 kb
Host smart-423ccc99-9841-4f5a-a450-3dfb9147a7a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685358833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp
_reset.685358833
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2131539091
Short name T152
Test name
Test status
Simulation time 43963600 ps
CPU time 14.1 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:10:00 PM PDT 24
Peak memory 265048 kb
Host smart-489b829f-f7f1-48a7-876b-ef97236da01d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2131539091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2131539091
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.2556697679
Short name T539
Test name
Test status
Simulation time 740833100 ps
CPU time 285.81 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 262224 kb
Host smart-da3d61fd-2286-41b1-ac74-bf73c419441d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556697679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2556697679
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.91078956
Short name T538
Test name
Test status
Simulation time 29037900 ps
CPU time 13.5 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:10:04 PM PDT 24
Peak memory 264780 kb
Host smart-2f259081-3758-4516-8fb0-7b2e0af13efd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91078956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset
.91078956
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.31469917
Short name T80
Test name
Test status
Simulation time 3284397100 ps
CPU time 1055.33 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:27:24 PM PDT 24
Peak memory 286020 kb
Host smart-acfba7e0-3967-4c95-b5d0-5af0d392f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31469917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.31469917
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.3554844109
Short name T776
Test name
Test status
Simulation time 719786000 ps
CPU time 148.37 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:12:17 PM PDT 24
Peak memory 264952 kb
Host smart-d723fe72-21af-4e4e-be62-6e33ac575b00
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554844109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.3554844109
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3662711108
Short name T209
Test name
Test status
Simulation time 214549800 ps
CPU time 31.38 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:10:30 PM PDT 24
Peak memory 275656 kb
Host smart-059afad1-1030-49ce-91bf-059a465c2421
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662711108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3662711108
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2482246992
Short name T681
Test name
Test status
Simulation time 56021200 ps
CPU time 33.05 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 273080 kb
Host smart-27927a92-b98c-49ad-8a6a-dfb122081e75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482246992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2482246992
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.3386570612
Short name T819
Test name
Test status
Simulation time 45726900 ps
CPU time 21.26 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:10:25 PM PDT 24
Peak memory 264616 kb
Host smart-b13b92d2-bdcf-4b13-a661-95a24cc010a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386570612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.3386570612
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2841665058
Short name T124
Test name
Test status
Simulation time 163830428500 ps
CPU time 952.48 seconds
Started May 30 01:09:41 PM PDT 24
Finished May 30 01:25:34 PM PDT 24
Peak memory 259040 kb
Host smart-0fcf6f80-5f60-4dc2-beec-71276714bdba
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841665058 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2841665058
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.4097439892
Short name T794
Test name
Test status
Simulation time 2234598100 ps
CPU time 123.22 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:11:52 PM PDT 24
Peak memory 281280 kb
Host smart-c3a7c66a-36bc-48ad-812d-680bb58e6233
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097439892 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.4097439892
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1923384816
Short name T198
Test name
Test status
Simulation time 7325822200 ps
CPU time 129.36 seconds
Started May 30 01:09:46 PM PDT 24
Finished May 30 01:11:56 PM PDT 24
Peak memory 281712 kb
Host smart-e200b249-2dd1-45da-8998-f1a772a06539
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1923384816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1923384816
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.2258499434
Short name T435
Test name
Test status
Simulation time 555783500 ps
CPU time 137.93 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:12:04 PM PDT 24
Peak memory 293644 kb
Host smart-7a149540-5d65-4355-841d-e0221eaaa384
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258499434 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2258499434
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.370272675
Short name T769
Test name
Test status
Simulation time 3862873900 ps
CPU time 551.38 seconds
Started May 30 01:09:44 PM PDT 24
Finished May 30 01:18:56 PM PDT 24
Peak memory 309132 kb
Host smart-50dd0658-6393-4c28-93df-d8ecad0a779d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370272675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_rw.370272675
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.644610140
Short name T189
Test name
Test status
Simulation time 6767731300 ps
CPU time 562.86 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:19:11 PM PDT 24
Peak memory 337784 kb
Host smart-2e2d2104-78bc-4bbb-a35c-a565ecfbde31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644610140 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_rw_derr.644610140
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2167306231
Short name T509
Test name
Test status
Simulation time 32449500 ps
CPU time 30.38 seconds
Started May 30 01:09:43 PM PDT 24
Finished May 30 01:10:14 PM PDT 24
Peak memory 274348 kb
Host smart-610c25ab-e3de-4734-9177-be15434787e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167306231 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2167306231
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2181014613
Short name T796
Test name
Test status
Simulation time 4396625100 ps
CPU time 561.38 seconds
Started May 30 01:09:54 PM PDT 24
Finished May 30 01:19:17 PM PDT 24
Peak memory 311952 kb
Host smart-6191db31-311d-44db-82e0-3f3ae8b480f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181014613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.2181014613
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3468292371
Short name T563
Test name
Test status
Simulation time 756329700 ps
CPU time 72.49 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:11:18 PM PDT 24
Peak memory 264884 kb
Host smart-f0efa708-356a-4dad-bf16-5d8e42ca8bf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468292371 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3468292371
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3749504470
Short name T5
Test name
Test status
Simulation time 927561200 ps
CPU time 93.3 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:11:24 PM PDT 24
Peak memory 264968 kb
Host smart-ea7d118c-ce0e-4ba4-8329-dc913329fd0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749504470 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3749504470
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.220383570
Short name T455
Test name
Test status
Simulation time 24371800 ps
CPU time 75.96 seconds
Started May 30 01:09:54 PM PDT 24
Finished May 30 01:11:11 PM PDT 24
Peak memory 276240 kb
Host smart-76a65132-6451-4612-8523-cea91c50e8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220383570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.220383570
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2771184435
Short name T437
Test name
Test status
Simulation time 26751200 ps
CPU time 23.78 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:13 PM PDT 24
Peak memory 258784 kb
Host smart-18ab2d1b-351c-4cd0-b490-bf14bf12e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771184435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2771184435
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2857344415
Short name T871
Test name
Test status
Simulation time 1267579900 ps
CPU time 1382.02 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:32:50 PM PDT 24
Peak memory 288280 kb
Host smart-459e4486-dfa5-4152-a958-6e7c8ecd87a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857344415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2857344415
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.2103357964
Short name T541
Test name
Test status
Simulation time 21943200 ps
CPU time 26.88 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:24 PM PDT 24
Peak memory 261164 kb
Host smart-c86da3f5-bd3b-40de-a1a2-6982d0214786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103357964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2103357964
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.899865004
Short name T491
Test name
Test status
Simulation time 2533828400 ps
CPU time 213.15 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:13:24 PM PDT 24
Peak memory 259168 kb
Host smart-57c0e5e2-05ee-4df1-9a9f-d722ca5694b1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899865004 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_wo.899865004
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2440763959
Short name T21
Test name
Test status
Simulation time 45147700 ps
CPU time 14.82 seconds
Started May 30 01:09:50 PM PDT 24
Finished May 30 01:10:06 PM PDT 24
Peak memory 259452 kb
Host smart-304b00da-aae3-4318-babb-9a8582a66949
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440763959 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2440763959
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1845970816
Short name T407
Test name
Test status
Simulation time 107540000 ps
CPU time 13.61 seconds
Started May 30 01:12:27 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 257972 kb
Host smart-52ef3eee-0b6e-48e2-bc7f-8ee602020efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845970816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1845970816
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.489200505
Short name T719
Test name
Test status
Simulation time 73541700 ps
CPU time 15.7 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:12:42 PM PDT 24
Peak memory 275424 kb
Host smart-0ac13e64-3e8a-4f16-9b89-c16addcac6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489200505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.489200505
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.843845275
Short name T799
Test name
Test status
Simulation time 10574700 ps
CPU time 21.58 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 273144 kb
Host smart-15282d0b-8471-43fa-a502-f9e97ccdbbef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843845275 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.843845275
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.716511334
Short name T693
Test name
Test status
Simulation time 6548089400 ps
CPU time 168.78 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:15:12 PM PDT 24
Peak memory 262320 kb
Host smart-568c4e18-f527-4d91-8415-498a37711b5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716511334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_h
w_sec_otp.716511334
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.1782590174
Short name T758
Test name
Test status
Simulation time 3603510300 ps
CPU time 204.71 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 290492 kb
Host smart-d77c3f0e-e2d1-424a-87df-21b80ed9dd5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782590174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.1782590174
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4246765996
Short name T938
Test name
Test status
Simulation time 24234283400 ps
CPU time 332.4 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 292696 kb
Host smart-a879bd82-a23e-4df8-8e1b-8699b2226360
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246765996 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.4246765996
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1743938995
Short name T1055
Test name
Test status
Simulation time 151178300 ps
CPU time 131.63 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:14:36 PM PDT 24
Peak memory 259732 kb
Host smart-59061109-9f8d-4ab8-9e0a-dc93eb02ae2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743938995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1743938995
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3773979132
Short name T771
Test name
Test status
Simulation time 11100648900 ps
CPU time 186.51 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:15:29 PM PDT 24
Peak memory 258940 kb
Host smart-3eca1f89-c903-413c-a75d-889b1c28dce7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773979132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.3773979132
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.2279352408
Short name T928
Test name
Test status
Simulation time 30005900 ps
CPU time 30.58 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:12:56 PM PDT 24
Peak memory 274116 kb
Host smart-ab95cb70-e6dc-4961-8f40-65f269f99d3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279352408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.2279352408
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3118849787
Short name T546
Test name
Test status
Simulation time 304327000 ps
CPU time 30.91 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:12:53 PM PDT 24
Peak memory 274260 kb
Host smart-3bda963b-afa3-495f-94ed-dd844408bd0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118849787 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3118849787
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1708909007
Short name T405
Test name
Test status
Simulation time 537953900 ps
CPU time 54.98 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:13:20 PM PDT 24
Peak memory 262392 kb
Host smart-abffca1f-ed93-4bd8-a3ef-6575d9589b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708909007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1708909007
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2232592973
Short name T927
Test name
Test status
Simulation time 35118600 ps
CPU time 217.9 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:16:05 PM PDT 24
Peak memory 280976 kb
Host smart-d61e631b-b12d-48ff-bae6-a02294b426d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232592973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2232592973
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2170841096
Short name T1050
Test name
Test status
Simulation time 52001900 ps
CPU time 13.75 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:12:38 PM PDT 24
Peak memory 264808 kb
Host smart-1a19a6b6-d0a2-449e-bfea-24bfe1b27b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170841096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2170841096
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2263509175
Short name T629
Test name
Test status
Simulation time 40993300 ps
CPU time 13.41 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:12:40 PM PDT 24
Peak memory 274656 kb
Host smart-01ea69b0-3f0a-48e7-8a2f-b6ab46d1c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263509175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2263509175
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1194524358
Short name T1016
Test name
Test status
Simulation time 9802106200 ps
CPU time 79.53 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:13:42 PM PDT 24
Peak memory 262124 kb
Host smart-e1790844-e86c-47cf-b5a5-428fa8718ff2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194524358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1194524358
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1969295030
Short name T166
Test name
Test status
Simulation time 11894179000 ps
CPU time 233.07 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:16:18 PM PDT 24
Peak memory 291840 kb
Host smart-2c0ed043-f3ce-4ef5-ad5a-3b7d8b05b778
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969295030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1969295030
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2130911237
Short name T40
Test name
Test status
Simulation time 13511558800 ps
CPU time 297.66 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:17:22 PM PDT 24
Peak memory 283720 kb
Host smart-b23aea03-af36-45ed-bccc-1a0590dcbfa4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130911237 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2130911237
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.827132921
Short name T759
Test name
Test status
Simulation time 39589800 ps
CPU time 130.04 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:14:32 PM PDT 24
Peak memory 259460 kb
Host smart-09f20bc6-ee4e-4a6b-a8bd-07087dc3743c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827132921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.827132921
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.412078616
Short name T682
Test name
Test status
Simulation time 18474000 ps
CPU time 13.4 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:12:38 PM PDT 24
Peak memory 264212 kb
Host smart-164dcd75-3ae1-4224-980b-23bb984e913c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412078616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.412078616
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.393714855
Short name T999
Test name
Test status
Simulation time 26723000 ps
CPU time 30.68 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:12:55 PM PDT 24
Peak memory 275212 kb
Host smart-5e302b20-797d-4d61-8a04-0d78ebf8d443
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393714855 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.393714855
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2924526752
Short name T752
Test name
Test status
Simulation time 7608253400 ps
CPU time 74.83 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:13:38 PM PDT 24
Peak memory 262632 kb
Host smart-874a453e-1bc9-4989-aaa7-e63d01a5e6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924526752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2924526752
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2082009222
Short name T1059
Test name
Test status
Simulation time 98199200 ps
CPU time 95.55 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:14:02 PM PDT 24
Peak memory 275328 kb
Host smart-c3666606-1c78-4cd6-aa7b-097d7699bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082009222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2082009222
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.4119029560
Short name T800
Test name
Test status
Simulation time 75802800 ps
CPU time 13.44 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 264796 kb
Host smart-40ebd9c5-09a0-4a16-aa7d-df402ecf944a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119029560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
4119029560
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2795523765
Short name T994
Test name
Test status
Simulation time 22415200 ps
CPU time 15.58 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:12:43 PM PDT 24
Peak memory 274696 kb
Host smart-a857161d-cf45-4d79-861e-b6d0a33adeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795523765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2795523765
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.4185083906
Short name T597
Test name
Test status
Simulation time 61481300 ps
CPU time 20.24 seconds
Started May 30 01:12:22 PM PDT 24
Finished May 30 01:12:44 PM PDT 24
Peak memory 273052 kb
Host smart-e3f240fb-9a95-4b30-a27a-541360497b96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185083906 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.4185083906
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2645480914
Short name T891
Test name
Test status
Simulation time 2217458100 ps
CPU time 74.67 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:13:39 PM PDT 24
Peak memory 262272 kb
Host smart-2cab700d-df5a-4feb-a78b-06d794353c93
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645480914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2645480914
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.193696009
Short name T350
Test name
Test status
Simulation time 1324682200 ps
CPU time 183.39 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:15:28 PM PDT 24
Peak memory 291964 kb
Host smart-7917e832-d22e-4077-a470-a87b4ec5c5eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193696009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.193696009
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2948276044
Short name T345
Test name
Test status
Simulation time 24194200200 ps
CPU time 147.9 seconds
Started May 30 01:12:23 PM PDT 24
Finished May 30 01:14:53 PM PDT 24
Peak memory 293004 kb
Host smart-4d9f1fa3-1cd1-41ac-9ad8-5a3326aca0ff
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948276044 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2948276044
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.3249520021
Short name T774
Test name
Test status
Simulation time 679885800 ps
CPU time 131.8 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:14:38 PM PDT 24
Peak memory 259844 kb
Host smart-833212e0-6c28-4395-99a1-01264601209d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249520021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.3249520021
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.3109829690
Short name T332
Test name
Test status
Simulation time 177522300 ps
CPU time 28.75 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:12:51 PM PDT 24
Peak memory 266820 kb
Host smart-3fd75adc-6633-403f-b043-50d54c975edf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109829690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.3109829690
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2214721743
Short name T44
Test name
Test status
Simulation time 89642800 ps
CPU time 30.79 seconds
Started May 30 01:12:24 PM PDT 24
Finished May 30 01:12:56 PM PDT 24
Peak memory 274304 kb
Host smart-8b223c7f-0d9c-41a2-81fc-0af90827042b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214721743 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2214721743
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.3596052350
Short name T489
Test name
Test status
Simulation time 2706109700 ps
CPU time 63.53 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:13:31 PM PDT 24
Peak memory 262764 kb
Host smart-c628bea5-f356-446f-a87f-6d28500f7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596052350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3596052350
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.2308644117
Short name T687
Test name
Test status
Simulation time 63988900 ps
CPU time 193.1 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 276740 kb
Host smart-d20012ce-07c2-4257-83d9-5eb824d03d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308644117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2308644117
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.742815339
Short name T896
Test name
Test status
Simulation time 35517400 ps
CPU time 13.81 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 264788 kb
Host smart-dd9e6777-aa1f-48e6-80fd-5d7200b9e210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742815339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.742815339
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3746661658
Short name T701
Test name
Test status
Simulation time 26316700 ps
CPU time 15.66 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:12:52 PM PDT 24
Peak memory 275516 kb
Host smart-0eb7068d-684e-42bb-bbfe-fa12b1c7a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746661658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3746661658
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2109110035
Short name T849
Test name
Test status
Simulation time 28287800 ps
CPU time 20.95 seconds
Started May 30 01:12:37 PM PDT 24
Finished May 30 01:12:59 PM PDT 24
Peak memory 273196 kb
Host smart-979cc2d7-809b-48ba-9082-8f0dee26a85e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109110035 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2109110035
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1898411135
Short name T50
Test name
Test status
Simulation time 9831372100 ps
CPU time 48.98 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:13:16 PM PDT 24
Peak memory 259756 kb
Host smart-23612348-5ee0-41f1-b73d-5a270513746e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898411135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1898411135
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.2768620928
Short name T37
Test name
Test status
Simulation time 1290559400 ps
CPU time 124.62 seconds
Started May 30 01:12:25 PM PDT 24
Finished May 30 01:14:31 PM PDT 24
Peak memory 292860 kb
Host smart-ae7d92e2-8a39-45d2-ba9c-4a8f27ce59a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768620928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.2768620928
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3245046050
Short name T540
Test name
Test status
Simulation time 13240998300 ps
CPU time 271.95 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 291408 kb
Host smart-680f81d9-be0f-4df6-90fe-fd1fc6ed03ec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245046050 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.3245046050
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.2213273813
Short name T805
Test name
Test status
Simulation time 36337000 ps
CPU time 130.05 seconds
Started May 30 01:12:26 PM PDT 24
Finished May 30 01:14:38 PM PDT 24
Peak memory 259828 kb
Host smart-93de0509-0b70-44ef-bb7c-e7fb5e043dad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213273813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.2213273813
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3808861217
Short name T1062
Test name
Test status
Simulation time 20394600 ps
CPU time 13.41 seconds
Started May 30 01:12:36 PM PDT 24
Finished May 30 01:12:50 PM PDT 24
Peak memory 258428 kb
Host smart-f432a000-b607-4aab-a865-ea5ff334099e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808861217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3808861217
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.16798643
Short name T177
Test name
Test status
Simulation time 99255700 ps
CPU time 31.19 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:13:05 PM PDT 24
Peak memory 274132 kb
Host smart-18d37454-eff4-413a-8643-0920bab8277b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16798643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas
h_ctrl_rw_evict.16798643
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3166123645
Short name T613
Test name
Test status
Simulation time 45579100 ps
CPU time 31.14 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:13:06 PM PDT 24
Peak memory 275000 kb
Host smart-b0d39e11-001c-4c37-8b89-2cf15f6abdab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166123645 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3166123645
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1694304666
Short name T862
Test name
Test status
Simulation time 347408200 ps
CPU time 51.28 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:13:26 PM PDT 24
Peak memory 261656 kb
Host smart-ed384d94-1140-414e-862e-a97dd31cdb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694304666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1694304666
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.4039974388
Short name T529
Test name
Test status
Simulation time 66981800 ps
CPU time 170.19 seconds
Started May 30 01:12:21 PM PDT 24
Finished May 30 01:15:12 PM PDT 24
Peak memory 276540 kb
Host smart-4605f71e-80cf-4ede-8de2-1fc57f10bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039974388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.4039974388
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.4092216274
Short name T890
Test name
Test status
Simulation time 190852400 ps
CPU time 13.66 seconds
Started May 30 01:12:36 PM PDT 24
Finished May 30 01:12:51 PM PDT 24
Peak memory 257900 kb
Host smart-f0f73a9b-27ac-422b-899f-775ec4551e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092216274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
4092216274
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2720007620
Short name T616
Test name
Test status
Simulation time 50714000 ps
CPU time 16.16 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:12:52 PM PDT 24
Peak memory 274768 kb
Host smart-00546ce6-8e28-4949-ac6c-9a5cd61efc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720007620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2720007620
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.647143246
Short name T318
Test name
Test status
Simulation time 4885310100 ps
CPU time 75.75 seconds
Started May 30 01:12:36 PM PDT 24
Finished May 30 01:13:53 PM PDT 24
Peak memory 262352 kb
Host smart-20ace4db-210c-4a6f-bac0-506b1f23b059
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647143246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h
w_sec_otp.647143246
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1444048380
Short name T346
Test name
Test status
Simulation time 1246713300 ps
CPU time 206.94 seconds
Started May 30 01:12:36 PM PDT 24
Finished May 30 01:16:04 PM PDT 24
Peak memory 291744 kb
Host smart-9268f0fd-b203-4847-b6ab-ad8c56da4bd0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444048380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1444048380
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3427252815
Short name T872
Test name
Test status
Simulation time 12835840500 ps
CPU time 250.46 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 283948 kb
Host smart-e853a966-b9dc-4460-a796-2e335df5d46f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427252815 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3427252815
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.2560481351
Short name T440
Test name
Test status
Simulation time 41458900 ps
CPU time 108.53 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 260924 kb
Host smart-a2c58e53-ddb5-42b0-a714-0184f48f9311
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560481351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.2560481351
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.1807171030
Short name T831
Test name
Test status
Simulation time 2040269600 ps
CPU time 173.82 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:15:29 PM PDT 24
Peak memory 264740 kb
Host smart-04850a40-4d85-4618-8468-13e6a5e54baf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807171030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.1807171030
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3357208882
Short name T802
Test name
Test status
Simulation time 1331772100 ps
CPU time 68.57 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:13:43 PM PDT 24
Peak memory 263172 kb
Host smart-394ceedf-1fb0-4d6c-8cd9-e59e4024d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357208882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3357208882
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1702736025
Short name T688
Test name
Test status
Simulation time 246478800 ps
CPU time 147.46 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:15:03 PM PDT 24
Peak memory 275852 kb
Host smart-c1a41c71-83ee-4d4b-8b74-f9d189abdae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702736025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1702736025
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2904778746
Short name T594
Test name
Test status
Simulation time 72039100 ps
CPU time 13.58 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:13:14 PM PDT 24
Peak memory 264804 kb
Host smart-70933a4f-df4b-481b-9875-b79874b393d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904778746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2904778746
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2847002180
Short name T418
Test name
Test status
Simulation time 49198100 ps
CPU time 15.77 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:13:19 PM PDT 24
Peak memory 275836 kb
Host smart-62fae558-2360-4c0f-a479-6a4515190f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847002180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2847002180
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3968354224
Short name T1079
Test name
Test status
Simulation time 19429100 ps
CPU time 21.77 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:13:24 PM PDT 24
Peak memory 273204 kb
Host smart-7fa27ce1-981a-4af8-9d71-56004e1916d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968354224 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3968354224
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1501291802
Short name T850
Test name
Test status
Simulation time 4199399700 ps
CPU time 53.75 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:13:29 PM PDT 24
Peak memory 261776 kb
Host smart-cfb4ca0c-ea97-4193-a99e-292fdb3272bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501291802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1501291802
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.193068290
Short name T733
Test name
Test status
Simulation time 862511900 ps
CPU time 130.06 seconds
Started May 30 01:12:38 PM PDT 24
Finished May 30 01:14:49 PM PDT 24
Peak memory 292988 kb
Host smart-f956ea70-2e31-4213-b011-06f70e9a01d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193068290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.193068290
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.146484313
Short name T866
Test name
Test status
Simulation time 12213324500 ps
CPU time 136.67 seconds
Started May 30 01:12:37 PM PDT 24
Finished May 30 01:14:54 PM PDT 24
Peak memory 293012 kb
Host smart-ef9cede1-c026-4f6b-87ea-78928cb8c8ff
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146484313 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.146484313
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2002547830
Short name T128
Test name
Test status
Simulation time 103611400 ps
CPU time 131.09 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:14:47 PM PDT 24
Peak memory 259776 kb
Host smart-b1645da5-dc82-4cb9-99ed-587b82b8e6af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002547830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2002547830
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.1507111112
Short name T381
Test name
Test status
Simulation time 31721300 ps
CPU time 13.71 seconds
Started May 30 01:12:34 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 258404 kb
Host smart-e3a149df-47e5-409c-8187-540d3d371977
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507111112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.1507111112
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.4218691859
Short name T43
Test name
Test status
Simulation time 41483700 ps
CPU time 31.16 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:13:34 PM PDT 24
Peak memory 274316 kb
Host smart-1765d327-8146-4985-a10e-a2486b6da2e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218691859 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.4218691859
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.2393773700
Short name T149
Test name
Test status
Simulation time 473206000 ps
CPU time 53.13 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:13:56 PM PDT 24
Peak memory 262152 kb
Host smart-ec7cc2b8-2ddc-4741-bc25-5b8932660610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393773700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2393773700
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.2604018133
Short name T946
Test name
Test status
Simulation time 84577200 ps
CPU time 97.71 seconds
Started May 30 01:12:35 PM PDT 24
Finished May 30 01:14:13 PM PDT 24
Peak memory 275060 kb
Host smart-c014e7da-90e4-4ec6-b4c0-a18739bc42aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604018133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2604018133
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.2054275173
Short name T1008
Test name
Test status
Simulation time 29476800 ps
CPU time 13.69 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:13:18 PM PDT 24
Peak memory 264804 kb
Host smart-555f7751-61fe-4c50-af4f-893993513907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054275173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
2054275173
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.2795688394
Short name T826
Test name
Test status
Simulation time 50893000 ps
CPU time 15.43 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 275928 kb
Host smart-1ce67e13-79b2-4f9b-9676-3d12a3540015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795688394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2795688394
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3368172032
Short name T391
Test name
Test status
Simulation time 36437300 ps
CPU time 21.71 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:13:25 PM PDT 24
Peak memory 273120 kb
Host smart-558d3929-45e9-4947-949c-68074d6af68b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368172032 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3368172032
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3143987431
Short name T644
Test name
Test status
Simulation time 1719692300 ps
CPU time 69.97 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:14:13 PM PDT 24
Peak memory 262460 kb
Host smart-d257152f-44de-4a7e-9c18-66fa33ab1b34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143987431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3143987431
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.2664705833
Short name T270
Test name
Test status
Simulation time 15212321100 ps
CPU time 207.45 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 289416 kb
Host smart-057b3657-aac6-4347-add1-3bd9fa9a4a67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664705833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.2664705833
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1573486545
Short name T763
Test name
Test status
Simulation time 23243094300 ps
CPU time 147.18 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:15:26 PM PDT 24
Peak memory 291452 kb
Host smart-c447322c-bfc7-422d-8a1e-e11f63a9a0c6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573486545 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1573486545
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.2710899356
Short name T962
Test name
Test status
Simulation time 68826800 ps
CPU time 129.99 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:15:10 PM PDT 24
Peak memory 260868 kb
Host smart-a1734ddb-c242-4611-b7e6-e590d4e07af3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710899356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.2710899356
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.3951691290
Short name T470
Test name
Test status
Simulation time 17866100 ps
CPU time 13.75 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:13:16 PM PDT 24
Peak memory 264792 kb
Host smart-b1febe00-dc3d-4b73-83ad-0dbb0a605cd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951691290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.3951691290
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.206206220
Short name T582
Test name
Test status
Simulation time 43122400 ps
CPU time 30.9 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:13:32 PM PDT 24
Peak memory 275048 kb
Host smart-1dd1b4ce-0460-4dfa-9108-e21f425df0d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206206220 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.206206220
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.848242449
Short name T227
Test name
Test status
Simulation time 1469144500 ps
CPU time 63.17 seconds
Started May 30 01:12:57 PM PDT 24
Finished May 30 01:14:01 PM PDT 24
Peak memory 262296 kb
Host smart-c92e0775-2860-4e81-b352-1770d1cd5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848242449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.848242449
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.2478647701
Short name T966
Test name
Test status
Simulation time 46959800 ps
CPU time 72.76 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:14:14 PM PDT 24
Peak memory 275760 kb
Host smart-31115dc1-da4d-477b-a96a-43a616901cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478647701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2478647701
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3049540663
Short name T782
Test name
Test status
Simulation time 52382200 ps
CPU time 13.91 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:13:15 PM PDT 24
Peak memory 257780 kb
Host smart-97ec6943-07dc-46ff-a596-cc8773d8236d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049540663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3049540663
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3288643116
Short name T477
Test name
Test status
Simulation time 24063900 ps
CPU time 13.38 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:13:17 PM PDT 24
Peak memory 274828 kb
Host smart-404afc0c-72ee-4a42-bec4-8025937e7e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288643116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3288643116
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.307699282
Short name T49
Test name
Test status
Simulation time 21287000 ps
CPU time 20.43 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:13:22 PM PDT 24
Peak memory 264792 kb
Host smart-3ed18c57-a8a5-4cb5-960d-5ed950e19013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307699282 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.307699282
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3894264290
Short name T820
Test name
Test status
Simulation time 3675010300 ps
CPU time 100.74 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 262344 kb
Host smart-6553d890-121c-4414-823a-cd2c03e9e479
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894264290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3894264290
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.4237170726
Short name T926
Test name
Test status
Simulation time 3210705200 ps
CPU time 186.73 seconds
Started May 30 01:13:02 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 289412 kb
Host smart-2d73945c-632c-4629-ba62-7a487c41d637
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237170726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.4237170726
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.64083482
Short name T754
Test name
Test status
Simulation time 6033989600 ps
CPU time 119.46 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:15:01 PM PDT 24
Peak memory 291616 kb
Host smart-dc8fac52-48cf-44c0-a79e-65403b8848df
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64083482 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.64083482
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.2540814733
Short name T1064
Test name
Test status
Simulation time 208998700 ps
CPU time 130.9 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:15:13 PM PDT 24
Peak memory 259404 kb
Host smart-76397206-5ac3-4701-934b-11f3f393e2a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540814733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.2540814733
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.2414644509
Short name T684
Test name
Test status
Simulation time 37481600 ps
CPU time 13.45 seconds
Started May 30 01:12:58 PM PDT 24
Finished May 30 01:13:12 PM PDT 24
Peak memory 258476 kb
Host smart-7c91aad1-92ef-4d2b-b740-ad8eaa507461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414644509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.2414644509
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1037105389
Short name T566
Test name
Test status
Simulation time 29775900 ps
CPU time 31.12 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 274372 kb
Host smart-3b495856-4a8f-4f1d-ae23-2731fdd9425c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037105389 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1037105389
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.4104565424
Short name T575
Test name
Test status
Simulation time 1778623700 ps
CPU time 73.37 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:14:15 PM PDT 24
Peak memory 264728 kb
Host smart-a40816b8-b958-433e-91c1-e1e6beef4fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104565424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.4104565424
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.590398561
Short name T519
Test name
Test status
Simulation time 76974200 ps
CPU time 166.84 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:15:50 PM PDT 24
Peak memory 280160 kb
Host smart-450241d5-8682-47c4-8125-e555238aaf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590398561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.590398561
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3882034237
Short name T321
Test name
Test status
Simulation time 96537600 ps
CPU time 13.54 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:13:36 PM PDT 24
Peak memory 257792 kb
Host smart-2c9c6e7d-6e91-408b-b8a3-6821ebe42b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882034237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3882034237
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.3087351815
Short name T600
Test name
Test status
Simulation time 46813600 ps
CPU time 15.52 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:35 PM PDT 24
Peak memory 275844 kb
Host smart-20ddead4-ec3f-4266-9504-76301753fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087351815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3087351815
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.4192727148
Short name T8
Test name
Test status
Simulation time 3290656100 ps
CPU time 117.81 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:15:01 PM PDT 24
Peak memory 262428 kb
Host smart-068ef4d6-9439-4f78-a3f4-6a903e0fe0d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192727148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.4192727148
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.993571203
Short name T659
Test name
Test status
Simulation time 6832171600 ps
CPU time 203.82 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 283768 kb
Host smart-8904d3de-4179-4dea-8a03-97b3749994db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993571203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.993571203
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.918273129
Short name T357
Test name
Test status
Simulation time 12309040000 ps
CPU time 241.46 seconds
Started May 30 01:13:03 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 292936 kb
Host smart-e68d906a-bb78-480e-a9e4-71697aab80df
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918273129 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.918273129
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2894654484
Short name T708
Test name
Test status
Simulation time 71115900 ps
CPU time 135.9 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:15:15 PM PDT 24
Peak memory 259592 kb
Host smart-1bb4f734-8019-425f-86dd-e0c02ab24c33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894654484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2894654484
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.1740237243
Short name T801
Test name
Test status
Simulation time 38601200 ps
CPU time 13.34 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:13:14 PM PDT 24
Peak memory 264752 kb
Host smart-7bc8e63b-0303-46e1-b3c8-a76f2eea2a92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740237243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.1740237243
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.694316795
Short name T586
Test name
Test status
Simulation time 35819000 ps
CPU time 31.23 seconds
Started May 30 01:12:59 PM PDT 24
Finished May 30 01:13:31 PM PDT 24
Peak memory 266936 kb
Host smart-c7ca7a01-6bd8-405d-923c-017ddf7c9d7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694316795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_rw_evict.694316795
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1897170361
Short name T1093
Test name
Test status
Simulation time 40031900 ps
CPU time 28.14 seconds
Started May 30 01:12:58 PM PDT 24
Finished May 30 01:13:27 PM PDT 24
Peak memory 274256 kb
Host smart-c02d18ff-2c20-4e07-a16e-d106c97b7890
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897170361 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1897170361
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3507729748
Short name T1043
Test name
Test status
Simulation time 1496331800 ps
CPU time 67.87 seconds
Started May 30 01:13:00 PM PDT 24
Finished May 30 01:14:08 PM PDT 24
Peak memory 262116 kb
Host smart-2688f06b-0cc2-4be2-8cfa-3a349e6d9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507729748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3507729748
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.3900390543
Short name T834
Test name
Test status
Simulation time 26896800 ps
CPU time 169.34 seconds
Started May 30 01:13:01 PM PDT 24
Finished May 30 01:15:51 PM PDT 24
Peak memory 279580 kb
Host smart-184d7a1a-e094-4e16-89d1-4e22c0d12446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900390543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3900390543
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2722588556
Short name T845
Test name
Test status
Simulation time 78280900 ps
CPU time 13.79 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:31 PM PDT 24
Peak memory 264768 kb
Host smart-b8219586-4065-4fcb-a8d8-e11b460d1073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722588556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2722588556
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.238730773
Short name T454
Test name
Test status
Simulation time 17060400 ps
CPU time 16.14 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 274948 kb
Host smart-ac407e52-7b79-454f-ae01-068521c59ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238730773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.238730773
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3862730677
Short name T894
Test name
Test status
Simulation time 10705300 ps
CPU time 20.71 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:38 PM PDT 24
Peak memory 273144 kb
Host smart-85ff07f9-c2b9-4a45-9ebc-81d6c6f5dc61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862730677 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3862730677
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3551236313
Short name T488
Test name
Test status
Simulation time 3276181800 ps
CPU time 79.49 seconds
Started May 30 01:13:14 PM PDT 24
Finished May 30 01:14:35 PM PDT 24
Peak memory 262244 kb
Host smart-2a3a6ef2-03e6-492a-97a2-20773ac8bb7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551236313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3551236313
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1822780433
Short name T39
Test name
Test status
Simulation time 6635625700 ps
CPU time 211.71 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:16:50 PM PDT 24
Peak memory 283532 kb
Host smart-a955c158-b7e4-4bb8-ba04-5c48c8ec020c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822780433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1822780433
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1107814057
Short name T713
Test name
Test status
Simulation time 12474009600 ps
CPU time 238.39 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 291452 kb
Host smart-a2264f8f-20d9-4669-a440-433581f9abb7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107814057 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1107814057
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.4073098517
Short name T301
Test name
Test status
Simulation time 39508500 ps
CPU time 134.13 seconds
Started May 30 01:13:14 PM PDT 24
Finished May 30 01:15:29 PM PDT 24
Peak memory 259596 kb
Host smart-439af54f-4d18-45b0-b858-44e8ef97545d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073098517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.4073098517
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.29570396
Short name T887
Test name
Test status
Simulation time 30176400 ps
CPU time 13.39 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:13:30 PM PDT 24
Peak memory 258264 kb
Host smart-98a8de55-a565-43d0-955c-6662f2292721
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_rese
t.29570396
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3420714902
Short name T982
Test name
Test status
Simulation time 28216900 ps
CPU time 30.18 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:13:52 PM PDT 24
Peak memory 275164 kb
Host smart-2d440a69-8356-4f9e-8d51-b40b817e44b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420714902 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3420714902
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2611851941
Short name T441
Test name
Test status
Simulation time 1320624900 ps
CPU time 70.78 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:14:29 PM PDT 24
Peak memory 263860 kb
Host smart-8920ce4a-141c-4c47-8891-703ff2e56def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611851941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2611851941
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3646668751
Short name T624
Test name
Test status
Simulation time 41264000 ps
CPU time 74.78 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 274664 kb
Host smart-3e3d2950-2c44-4816-9667-1ad19692a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646668751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3646668751
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.2873950896
Short name T429
Test name
Test status
Simulation time 146515100 ps
CPU time 13.77 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:10:11 PM PDT 24
Peak memory 264768 kb
Host smart-74c432e4-98b4-4b65-aff3-ca3b3e54c0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873950896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2
873950896
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.2865042699
Short name T366
Test name
Test status
Simulation time 21062100 ps
CPU time 13.78 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:10:18 PM PDT 24
Peak memory 261044 kb
Host smart-4df1d0ba-b6e2-40ed-8ad6-d15580e25f87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865042699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.2865042699
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2386539044
Short name T531
Test name
Test status
Simulation time 45028000 ps
CPU time 15.94 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 275376 kb
Host smart-51dfbcf2-7ff6-4abe-9032-d5395455d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386539044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2386539044
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.566011688
Short name T89
Test name
Test status
Simulation time 1147112000 ps
CPU time 102.57 seconds
Started May 30 01:09:50 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 281388 kb
Host smart-542cf4eb-c31b-4743-ab62-a08b097bf556
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566011688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_derr_detect.566011688
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.3305266437
Short name T385
Test name
Test status
Simulation time 24524400 ps
CPU time 21.59 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:10:27 PM PDT 24
Peak memory 272868 kb
Host smart-5c9d7043-4800-4178-8f01-595bb1369cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305266437 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.3305266437
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2676609321
Short name T81
Test name
Test status
Simulation time 2863394900 ps
CPU time 454.91 seconds
Started May 30 01:09:54 PM PDT 24
Finished May 30 01:17:30 PM PDT 24
Peak memory 261064 kb
Host smart-78bbd87c-7289-41f5-a1da-ef2fbebeeb1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676609321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2676609321
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.3343919232
Short name T841
Test name
Test status
Simulation time 4345472700 ps
CPU time 2458.69 seconds
Started May 30 01:09:53 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 262356 kb
Host smart-5aa1c574-ebaa-4a60-a428-3eeb7417e4e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343919232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.3343919232
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2527282542
Short name T997
Test name
Test status
Simulation time 3354642300 ps
CPU time 2535.54 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:52:05 PM PDT 24
Peak memory 264736 kb
Host smart-35bdb660-3cc7-4cd0-8cb3-0fc6e9e8c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527282542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2527282542
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3973303922
Short name T284
Test name
Test status
Simulation time 1340058800 ps
CPU time 805.74 seconds
Started May 30 01:10:00 PM PDT 24
Finished May 30 01:23:27 PM PDT 24
Peak memory 264700 kb
Host smart-9f35b99e-96bf-410b-9c95-6f8265b72928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973303922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3973303922
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2841773604
Short name T70
Test name
Test status
Simulation time 496055400 ps
CPU time 20.64 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:10 PM PDT 24
Peak memory 264740 kb
Host smart-b9071a85-5389-4d7a-80cb-fd94fc77ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841773604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2841773604
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.3264165144
Short name T1074
Test name
Test status
Simulation time 313062085700 ps
CPU time 2505.6 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:51:50 PM PDT 24
Peak memory 264840 kb
Host smart-6d626ae5-66ff-4a07-b00a-4351d0116bae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264165144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.3264165144
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3189793097
Short name T27
Test name
Test status
Simulation time 1190055011500 ps
CPU time 1790.69 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:39:40 PM PDT 24
Peak memory 261992 kb
Host smart-dd3189eb-28ba-4677-82a1-9b12c0619173
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189793097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3189793097
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2507980142
Short name T664
Test name
Test status
Simulation time 56885100 ps
CPU time 102.09 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:11:30 PM PDT 24
Peak memory 262236 kb
Host smart-8a342c6f-e977-4378-87bd-c8eda27bea60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507980142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2507980142
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1064848205
Short name T276
Test name
Test status
Simulation time 10045639700 ps
CPU time 44.31 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:10:49 PM PDT 24
Peak memory 264888 kb
Host smart-ab111cd2-8246-4d42-8f6f-6ef823492071
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064848205 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1064848205
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.820134073
Short name T274
Test name
Test status
Simulation time 45164000 ps
CPU time 13.24 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:10:15 PM PDT 24
Peak memory 264980 kb
Host smart-d16848ab-5880-401f-8e63-d996c8df766a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820134073 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.820134073
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.904038903
Short name T548
Test name
Test status
Simulation time 80135436100 ps
CPU time 799.93 seconds
Started May 30 01:09:46 PM PDT 24
Finished May 30 01:23:08 PM PDT 24
Peak memory 264228 kb
Host smart-3f1faeb1-c102-4330-99a8-b85af3e0f2bf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904038903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.904038903
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3722165015
Short name T604
Test name
Test status
Simulation time 51475408300 ps
CPU time 165.11 seconds
Started May 30 01:09:53 PM PDT 24
Finished May 30 01:12:39 PM PDT 24
Peak memory 262316 kb
Host smart-000a2c68-ed19-464d-8284-89586e1a01c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722165015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3722165015
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1441367120
Short name T322
Test name
Test status
Simulation time 8875300100 ps
CPU time 185.29 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:13:09 PM PDT 24
Peak memory 293148 kb
Host smart-578d1a38-4a60-4d2b-ac79-52fe94eaf7e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441367120 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1441367120
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.2959206121
Short name T33
Test name
Test status
Simulation time 18165895100 ps
CPU time 86.74 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 259804 kb
Host smart-edca46c8-798c-499e-a20e-a133f687e514
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959206121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.2959206121
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3203479081
Short name T786
Test name
Test status
Simulation time 79982123200 ps
CPU time 195.63 seconds
Started May 30 01:09:54 PM PDT 24
Finished May 30 01:13:11 PM PDT 24
Peak memory 264836 kb
Host smart-e8809d3c-7d81-485a-bd9c-e4da39b94caf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320
3479081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3203479081
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.686193251
Short name T100
Test name
Test status
Simulation time 2109720000 ps
CPU time 61.92 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:10:52 PM PDT 24
Peak memory 260212 kb
Host smart-9129aae0-1108-4e3b-8f6f-0183a8b759ca
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686193251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.686193251
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3748992235
Short name T118
Test name
Test status
Simulation time 15665000 ps
CPU time 13.17 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 264816 kb
Host smart-a2a544b3-db74-40b5-90c8-6220174567a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748992235 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3748992235
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.286894366
Short name T561
Test name
Test status
Simulation time 9532419400 ps
CPU time 219.01 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 262080 kb
Host smart-452fa6df-844b-4fd8-bb9f-b6aff653d714
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286894366 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_mp_regions.286894366
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.2873712729
Short name T742
Test name
Test status
Simulation time 41609300 ps
CPU time 133.52 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:12:21 PM PDT 24
Peak memory 259504 kb
Host smart-cc5ab800-0b5e-4726-9b7c-9c95d6e00378
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873712729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.2873712729
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.91984387
Short name T71
Test name
Test status
Simulation time 36396500 ps
CPU time 13.8 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:10:23 PM PDT 24
Peak memory 276052 kb
Host smart-fac5c3aa-aa9e-4fe2-a218-b8a784c99191
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=91984387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.91984387
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.169592941
Short name T220
Test name
Test status
Simulation time 1017522100 ps
CPU time 345.46 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:15:53 PM PDT 24
Peak memory 261420 kb
Host smart-62f6c1b8-abbe-4f69-b777-9f33395e6b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169592941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.169592941
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3666676834
Short name T1033
Test name
Test status
Simulation time 15329400 ps
CPU time 14.35 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:10:14 PM PDT 24
Peak memory 261976 kb
Host smart-4a4f78e5-ba7c-44b6-87a4-3d3e5a514fb9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666676834 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3666676834
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.2874080332
Short name T382
Test name
Test status
Simulation time 46233800 ps
CPU time 13.39 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:10:19 PM PDT 24
Peak memory 258296 kb
Host smart-d3fc7acc-dc64-4a51-969a-8997d3cbb599
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874080332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.2874080332
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.218549657
Short name T1012
Test name
Test status
Simulation time 141476200 ps
CPU time 1064.29 seconds
Started May 30 01:09:42 PM PDT 24
Finished May 30 01:27:28 PM PDT 24
Peak memory 285860 kb
Host smart-446c761b-ff61-4cf3-a3d4-bfa74bfe63a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218549657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.218549657
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.601286828
Short name T1056
Test name
Test status
Simulation time 96247700 ps
CPU time 99.72 seconds
Started May 30 01:09:47 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 264724 kb
Host smart-0e134dfc-cd57-4b3e-b242-e7ef5b3b324b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601286828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.601286828
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.715975569
Short name T980
Test name
Test status
Simulation time 136964000 ps
CPU time 34.16 seconds
Started May 30 01:09:55 PM PDT 24
Finished May 30 01:10:30 PM PDT 24
Peak memory 266928 kb
Host smart-ad5c4491-d3ca-4b5f-b28a-13f34fe703d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715975569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.715975569
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3194794754
Short name T615
Test name
Test status
Simulation time 266543100 ps
CPU time 22.03 seconds
Started May 30 01:09:50 PM PDT 24
Finished May 30 01:10:13 PM PDT 24
Peak memory 264808 kb
Host smart-43dcb468-db50-43ca-b181-bb6c6974631b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194794754 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3194794754
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3403851000
Short name T907
Test name
Test status
Simulation time 75237900 ps
CPU time 22.49 seconds
Started May 30 01:10:00 PM PDT 24
Finished May 30 01:10:24 PM PDT 24
Peak memory 264600 kb
Host smart-a4562baa-9aa8-45d9-afb5-42af3cbd4e17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403851000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3403851000
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.4268693867
Short name T9
Test name
Test status
Simulation time 642318200 ps
CPU time 110.62 seconds
Started May 30 01:09:45 PM PDT 24
Finished May 30 01:11:37 PM PDT 24
Peak memory 296648 kb
Host smart-74b943cb-22b9-4c47-8794-983444da886f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268693867 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.4268693867
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2331452972
Short name T858
Test name
Test status
Simulation time 2503414200 ps
CPU time 115.94 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:12:05 PM PDT 24
Peak memory 281084 kb
Host smart-7f179783-eb99-422a-8d07-a7382ee8cd08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2331452972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2331452972
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.3598611719
Short name T714
Test name
Test status
Simulation time 2967931400 ps
CPU time 130.38 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:12:02 PM PDT 24
Peak memory 293980 kb
Host smart-cf9d9ce0-6048-4709-af8f-701dc1c82d5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598611719 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3598611719
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.2769857808
Short name T923
Test name
Test status
Simulation time 21925067000 ps
CPU time 516.2 seconds
Started May 30 01:09:57 PM PDT 24
Finished May 30 01:18:34 PM PDT 24
Peak memory 308960 kb
Host smart-c7f0d204-3acf-490f-a26e-de952fa4b946
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769857808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.2769857808
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.4200029394
Short name T207
Test name
Test status
Simulation time 5045654000 ps
CPU time 570.68 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 323332 kb
Host smart-88260760-7bd4-41fc-9c9a-221ecc7a9bec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200029394 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.4200029394
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2050110103
Short name T696
Test name
Test status
Simulation time 29539600 ps
CPU time 31.58 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 274336 kb
Host smart-d1a11a83-1efd-489f-a66f-a0d9290f43f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050110103 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2050110103
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.2859408853
Short name T683
Test name
Test status
Simulation time 7641202600 ps
CPU time 566.88 seconds
Started May 30 01:09:51 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 319808 kb
Host smart-f54031de-6bee-4ef6-8b98-fd2d78ee84ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859408853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.2859408853
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1090711128
Short name T174
Test name
Test status
Simulation time 2006996700 ps
CPU time 4761.13 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 02:29:23 PM PDT 24
Peak memory 286360 kb
Host smart-28e60932-c5be-4dfd-b246-fcbc7cb04448
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090711128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1090711128
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1217371605
Short name T498
Test name
Test status
Simulation time 855237600 ps
CPU time 61.39 seconds
Started May 30 01:09:57 PM PDT 24
Finished May 30 01:11:00 PM PDT 24
Peak memory 261356 kb
Host smart-8e448f09-c097-4b81-9db3-2206689354b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217371605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1217371605
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.207505546
Short name T817
Test name
Test status
Simulation time 1133868100 ps
CPU time 88.15 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:11:27 PM PDT 24
Peak memory 273076 kb
Host smart-421e3965-0aa9-4159-b7bc-576fecffa4e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207505546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.207505546
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.2661739921
Short name T461
Test name
Test status
Simulation time 2283120800 ps
CPU time 103.6 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:11:53 PM PDT 24
Peak memory 273796 kb
Host smart-f804803c-8ab8-4eac-8a19-bdb8f7bb11f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661739921 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.2661739921
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.2238433763
Short name T46
Test name
Test status
Simulation time 66747500 ps
CPU time 169.18 seconds
Started May 30 01:09:49 PM PDT 24
Finished May 30 01:12:39 PM PDT 24
Peak memory 278512 kb
Host smart-a4032aad-4bdc-405a-abf7-ad2015f8790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238433763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2238433763
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.870600398
Short name T69
Test name
Test status
Simulation time 28203000 ps
CPU time 25.43 seconds
Started May 30 01:09:48 PM PDT 24
Finished May 30 01:10:15 PM PDT 24
Peak memory 258808 kb
Host smart-faec6db1-9f2e-48af-a6b5-564195a70d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870600398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.870600398
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.2443771014
Short name T672
Test name
Test status
Simulation time 354544100 ps
CPU time 1508.44 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:35:11 PM PDT 24
Peak memory 289548 kb
Host smart-547cb56c-3855-4034-850f-b16225a3cf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443771014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.2443771014
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3845960019
Short name T824
Test name
Test status
Simulation time 43665700 ps
CPU time 25.81 seconds
Started May 30 01:09:46 PM PDT 24
Finished May 30 01:10:13 PM PDT 24
Peak memory 258688 kb
Host smart-e57c88bd-dc3b-4e55-af50-9df30dd96e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845960019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3845960019
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.471326249
Short name T606
Test name
Test status
Simulation time 3495478700 ps
CPU time 158.86 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 258800 kb
Host smart-6f536e1a-550c-4d5a-94f5-c2ae57280fc0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471326249 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_wo.471326249
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.90925641
Short name T512
Test name
Test status
Simulation time 28690400 ps
CPU time 13.42 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 257784 kb
Host smart-983e4781-8b62-48de-b1a7-1bca451d9d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90925641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.90925641
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2609920669
Short name T530
Test name
Test status
Simulation time 45790500 ps
CPU time 13.17 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:13:30 PM PDT 24
Peak memory 275552 kb
Host smart-4552642a-4732-4b4c-9ba1-98e14c4eb4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609920669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2609920669
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2936524990
Short name T1020
Test name
Test status
Simulation time 21022500 ps
CPU time 22.21 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:41 PM PDT 24
Peak memory 280032 kb
Host smart-5a78ec04-4503-4010-bf2a-032db13e69e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936524990 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2936524990
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1627264794
Short name T648
Test name
Test status
Simulation time 9903008400 ps
CPU time 86.8 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:14:46 PM PDT 24
Peak memory 262360 kb
Host smart-a5d7cbdd-1ea4-4e6b-996d-3ad52b6569fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627264794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1627264794
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2966700030
Short name T1019
Test name
Test status
Simulation time 3102002500 ps
CPU time 148.91 seconds
Started May 30 01:13:22 PM PDT 24
Finished May 30 01:15:53 PM PDT 24
Peak memory 289436 kb
Host smart-eb72fde9-ca21-4860-83d9-4fdbafafd6dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966700030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2966700030
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1917332031
Short name T617
Test name
Test status
Simulation time 23325000700 ps
CPU time 255.53 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 283976 kb
Host smart-38048f84-79ef-4cd2-b3e2-03eda924b101
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917332031 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.1917332031
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2640189949
Short name T1030
Test name
Test status
Simulation time 69209200 ps
CPU time 130.04 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:15:30 PM PDT 24
Peak memory 263428 kb
Host smart-c3b029a4-5708-40c8-a3f7-b1c8b44acaf2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640189949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2640189949
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.419475671
Short name T109
Test name
Test status
Simulation time 218269200 ps
CPU time 28.85 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:46 PM PDT 24
Peak memory 273092 kb
Host smart-bd7bfd0a-12cc-4e4b-90ad-8de321849004
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419475671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_rw_evict.419475671
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2844518027
Short name T484
Test name
Test status
Simulation time 1523576200 ps
CPU time 62.86 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:14:22 PM PDT 24
Peak memory 264408 kb
Host smart-f1552678-5ac8-4978-9814-a90b7d0c4b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844518027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2844518027
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.576402634
Short name T870
Test name
Test status
Simulation time 40491800 ps
CPU time 121.31 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 275576 kb
Host smart-b027f06a-10c8-4a8f-aeb2-cccb943f39f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576402634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.576402634
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2652769498
Short name T608
Test name
Test status
Simulation time 102067400 ps
CPU time 13.57 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 257844 kb
Host smart-4ead84de-7db0-44f0-8db8-c8ba72ad2f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652769498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2652769498
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3920125464
Short name T673
Test name
Test status
Simulation time 16999300 ps
CPU time 15.46 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:13:32 PM PDT 24
Peak memory 275508 kb
Host smart-d5c6136e-f35c-4836-9cdd-b7107cdae127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920125464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3920125464
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2784457769
Short name T310
Test name
Test status
Simulation time 6388563200 ps
CPU time 258.33 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:17:38 PM PDT 24
Peak memory 261744 kb
Host smart-92dfbba8-a527-4d61-a254-f25a62d7c7a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784457769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.2784457769
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1117519807
Short name T236
Test name
Test status
Simulation time 72735079600 ps
CPU time 333.33 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:18:52 PM PDT 24
Peak memory 292980 kb
Host smart-0aedb31d-5aa2-408d-9f32-869a157f8c3f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117519807 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1117519807
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.1960117337
Short name T129
Test name
Test status
Simulation time 158819700 ps
CPU time 130.31 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:15:27 PM PDT 24
Peak memory 259828 kb
Host smart-53c60a91-b2ea-4d8e-a172-b686d787de29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960117337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.1960117337
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3458676595
Short name T655
Test name
Test status
Simulation time 28048900 ps
CPU time 31.34 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:13:51 PM PDT 24
Peak memory 274416 kb
Host smart-bef576d7-d861-4bb2-96a2-0a589f8bc54e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458676595 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3458676595
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2851294720
Short name T809
Test name
Test status
Simulation time 14088069900 ps
CPU time 72.8 seconds
Started May 30 01:13:22 PM PDT 24
Finished May 30 01:14:36 PM PDT 24
Peak memory 262472 kb
Host smart-6d588fa2-23ac-4d4c-82af-5f40e1145dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851294720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2851294720
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1888810250
Short name T447
Test name
Test status
Simulation time 52622900 ps
CPU time 170.44 seconds
Started May 30 01:13:20 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 276584 kb
Host smart-c7f22686-c705-4d1a-ba22-c2c30d0b8fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888810250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1888810250
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2340181018
Short name T590
Test name
Test status
Simulation time 25544000 ps
CPU time 13.5 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:31 PM PDT 24
Peak memory 264636 kb
Host smart-87cdeec0-977d-49b5-8f17-f703513f4f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340181018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2340181018
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.1185126157
Short name T598
Test name
Test status
Simulation time 24462300 ps
CPU time 15.82 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:34 PM PDT 24
Peak memory 274776 kb
Host smart-9cff482b-031b-4e88-96a0-a61b527541ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185126157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1185126157
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1013365628
Short name T542
Test name
Test status
Simulation time 87359700 ps
CPU time 21.12 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:40 PM PDT 24
Peak memory 273296 kb
Host smart-4af19bd0-89fc-484a-a45e-bfc785e6795e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013365628 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1013365628
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.2105811380
Short name T957
Test name
Test status
Simulation time 1169424200 ps
CPU time 100.95 seconds
Started May 30 01:13:20 PM PDT 24
Finished May 30 01:15:02 PM PDT 24
Peak memory 262376 kb
Host smart-30fb1eb4-bb53-4d83-8f94-9c30eb1c02df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105811380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.2105811380
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1196383931
Short name T348
Test name
Test status
Simulation time 1578326900 ps
CPU time 216.65 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 283704 kb
Host smart-1004ed1e-1f62-438b-81b7-298fe8538e2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196383931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.1196383931
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3609936932
Short name T351
Test name
Test status
Simulation time 33495010500 ps
CPU time 260.72 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:17:39 PM PDT 24
Peak memory 290484 kb
Host smart-c0476d7b-838e-4a70-bcb8-325d376f4707
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609936932 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.3609936932
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.664128391
Short name T954
Test name
Test status
Simulation time 147304800 ps
CPU time 131.08 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 261960 kb
Host smart-443b0133-a5f4-4d27-8906-8fb1e3fdfb95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664128391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.664128391
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2731965375
Short name T204
Test name
Test status
Simulation time 41398200 ps
CPU time 28.04 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:13:51 PM PDT 24
Peak memory 274188 kb
Host smart-609638ff-d6d3-436f-be7e-60691b398c8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731965375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2731965375
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1601185676
Short name T814
Test name
Test status
Simulation time 33422000 ps
CPU time 30.81 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:50 PM PDT 24
Peak memory 274448 kb
Host smart-21b09dea-8fb7-431b-bad4-7ae54722ac07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601185676 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1601185676
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.180182933
Short name T903
Test name
Test status
Simulation time 4992628300 ps
CPU time 62.51 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:14:21 PM PDT 24
Peak memory 264312 kb
Host smart-96c9fb15-a4fc-40f5-81d1-fb4f106408b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180182933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.180182933
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.4162562690
Short name T725
Test name
Test status
Simulation time 26516300 ps
CPU time 217.62 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:16:56 PM PDT 24
Peak memory 280640 kb
Host smart-77abc00d-a8ba-4e19-b383-4845e4f245f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162562690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.4162562690
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.428201673
Short name T989
Test name
Test status
Simulation time 196904200 ps
CPU time 14.3 seconds
Started May 30 01:13:15 PM PDT 24
Finished May 30 01:13:30 PM PDT 24
Peak memory 258824 kb
Host smart-5066a64c-e83f-4579-893f-e16cac5cea77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428201673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.428201673
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1928196157
Short name T599
Test name
Test status
Simulation time 42528400 ps
CPU time 15.81 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:34 PM PDT 24
Peak memory 275964 kb
Host smart-03faeecd-6548-439b-9374-a4a5b3078f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928196157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1928196157
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3200891604
Short name T784
Test name
Test status
Simulation time 32592800 ps
CPU time 21.81 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:41 PM PDT 24
Peak memory 279968 kb
Host smart-3ebc211d-c9c3-4132-9931-3a0749cf7dda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200891604 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3200891604
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2224097890
Short name T1018
Test name
Test status
Simulation time 713998700 ps
CPU time 146.13 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:15:45 PM PDT 24
Peak memory 293860 kb
Host smart-32288a20-a421-41e8-897d-320a925fee48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224097890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2224097890
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3397662111
Short name T471
Test name
Test status
Simulation time 22443958600 ps
CPU time 170.62 seconds
Started May 30 01:13:22 PM PDT 24
Finished May 30 01:16:14 PM PDT 24
Peak memory 291668 kb
Host smart-42e41a60-ad64-4986-a140-6520e4264c77
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397662111 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3397662111
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.145157379
Short name T505
Test name
Test status
Simulation time 42359300 ps
CPU time 129.77 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 259960 kb
Host smart-e9c43542-db99-4db0-9d5b-26d50980ff5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145157379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.145157379
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1590340549
Short name T840
Test name
Test status
Simulation time 27059800 ps
CPU time 28.18 seconds
Started May 30 01:13:20 PM PDT 24
Finished May 30 01:13:49 PM PDT 24
Peak memory 273108 kb
Host smart-e8598a5e-d6dc-4dfb-8e18-0257e2ca2749
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590340549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1590340549
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1350189650
Short name T31
Test name
Test status
Simulation time 69507100 ps
CPU time 30.3 seconds
Started May 30 01:13:16 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 274464 kb
Host smart-21202af6-c343-42da-a2fe-25346041307c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350189650 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1350189650
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1008386128
Short name T400
Test name
Test status
Simulation time 8481290300 ps
CPU time 73.81 seconds
Started May 30 01:13:18 PM PDT 24
Finished May 30 01:14:33 PM PDT 24
Peak memory 262456 kb
Host smart-b0d9a393-45dd-4ccc-a11a-53ccec7798cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008386128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1008386128
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.1324810923
Short name T570
Test name
Test status
Simulation time 95886000 ps
CPU time 121.67 seconds
Started May 30 01:13:21 PM PDT 24
Finished May 30 01:15:25 PM PDT 24
Peak memory 275832 kb
Host smart-4b5e5d74-767f-4965-b26d-4a760ef0c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324810923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1324810923
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.4259202287
Short name T545
Test name
Test status
Simulation time 36701000 ps
CPU time 13.49 seconds
Started May 30 01:13:32 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 264816 kb
Host smart-e16e918a-cfdd-4879-a4c8-57415fa06df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259202287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
4259202287
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1035928986
Short name T420
Test name
Test status
Simulation time 13084400 ps
CPU time 15.73 seconds
Started May 30 01:13:28 PM PDT 24
Finished May 30 01:13:47 PM PDT 24
Peak memory 275868 kb
Host smart-89afa2a0-4f82-4241-9dae-b4fcce2359fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035928986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1035928986
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2733999723
Short name T663
Test name
Test status
Simulation time 11093500 ps
CPU time 20.27 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:13:53 PM PDT 24
Peak memory 273168 kb
Host smart-d6a032af-c821-4291-8968-e406ffcfc99f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733999723 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2733999723
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2957880131
Short name T977
Test name
Test status
Simulation time 1877412100 ps
CPU time 36.05 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:13:55 PM PDT 24
Peak memory 262480 kb
Host smart-747d62c2-88e4-4a31-8163-2d020fab04a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957880131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2957880131
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2544631888
Short name T861
Test name
Test status
Simulation time 57273729800 ps
CPU time 331.67 seconds
Started May 30 01:13:28 PM PDT 24
Finished May 30 01:19:02 PM PDT 24
Peak memory 292408 kb
Host smart-ef6f4f13-a473-4854-9349-bbcff2a53b0b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544631888 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.2544631888
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.1333531990
Short name T755
Test name
Test status
Simulation time 41862600 ps
CPU time 130.84 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 259796 kb
Host smart-3fbb4e42-99da-403a-b581-a1ee517028f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333531990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.1333531990
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.731715440
Short name T740
Test name
Test status
Simulation time 72971800 ps
CPU time 30.91 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:04 PM PDT 24
Peak memory 273152 kb
Host smart-9ab0945b-f80d-4019-a0c8-feab02e3019e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731715440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_rw_evict.731715440
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1119724005
Short name T329
Test name
Test status
Simulation time 101541500 ps
CPU time 32.01 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:14:01 PM PDT 24
Peak memory 275040 kb
Host smart-92dae4c0-cde6-47f5-97bf-f105a8502ded
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119724005 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1119724005
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.352318520
Short name T402
Test name
Test status
Simulation time 9179994000 ps
CPU time 76.88 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:50 PM PDT 24
Peak memory 262136 kb
Host smart-340102cd-10df-4df5-b9ad-845b6bf7c251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352318520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.352318520
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3308067757
Short name T741
Test name
Test status
Simulation time 52491900 ps
CPU time 170.36 seconds
Started May 30 01:13:17 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 279344 kb
Host smart-96668a8b-3f49-4b9b-88e8-1079d13255a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308067757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3308067757
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.1475479637
Short name T810
Test name
Test status
Simulation time 36023200 ps
CPU time 13.79 seconds
Started May 30 01:13:28 PM PDT 24
Finished May 30 01:13:45 PM PDT 24
Peak memory 264796 kb
Host smart-d0213c82-b1d0-42e7-b95d-d474b5c28075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475479637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
1475479637
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2593189848
Short name T864
Test name
Test status
Simulation time 42402300 ps
CPU time 13.33 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:13:47 PM PDT 24
Peak memory 274796 kb
Host smart-46d5efda-e41b-4c92-beb0-ca72125ebfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593189848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2593189848
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2353945754
Short name T390
Test name
Test status
Simulation time 10912200 ps
CPU time 21.63 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:13:51 PM PDT 24
Peak memory 279936 kb
Host smart-ff143172-ab36-4a8c-b5aa-34738cee58dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353945754 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2353945754
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.1697803863
Short name T666
Test name
Test status
Simulation time 3325263600 ps
CPU time 166.99 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:16:21 PM PDT 24
Peak memory 261780 kb
Host smart-4eb74b82-8408-403d-8b16-f6d612978f4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697803863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.1697803863
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.3968470135
Short name T948
Test name
Test status
Simulation time 675827300 ps
CPU time 123.84 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 293656 kb
Host smart-898a8343-639b-4ead-a9d3-28bd0ad3afa9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968470135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.3968470135
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3302447042
Short name T647
Test name
Test status
Simulation time 72381811100 ps
CPU time 136.5 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:15:46 PM PDT 24
Peak memory 292416 kb
Host smart-3dd3df01-12a1-4dc0-897d-e3ecab7ef7b5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302447042 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3302447042
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.1038711711
Short name T426
Test name
Test status
Simulation time 94451500 ps
CPU time 111.13 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:15:24 PM PDT 24
Peak memory 260764 kb
Host smart-ff316e61-61a4-463d-8bbb-bcf766fed589
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038711711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.1038711711
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.1068733947
Short name T965
Test name
Test status
Simulation time 80929100 ps
CPU time 31 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:05 PM PDT 24
Peak memory 273160 kb
Host smart-e126598a-0726-4d92-a8c2-2fb567cd682d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068733947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.1068733947
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1717341529
Short name T746
Test name
Test status
Simulation time 1523656800 ps
CPU time 56.14 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:14:28 PM PDT 24
Peak memory 262816 kb
Host smart-00c02257-dce0-4ac0-9526-70ca686de1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717341529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1717341529
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1421936318
Short name T1052
Test name
Test status
Simulation time 36933800 ps
CPU time 49.33 seconds
Started May 30 01:13:28 PM PDT 24
Finished May 30 01:14:20 PM PDT 24
Peak memory 270416 kb
Host smart-33808d5d-251d-4f19-bd12-a451b2447030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421936318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1421936318
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.213778688
Short name T431
Test name
Test status
Simulation time 65239500 ps
CPU time 13.59 seconds
Started May 30 01:13:33 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 264196 kb
Host smart-3a6ef5d3-5a42-4a46-b429-b92a44ffc091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213778688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.213778688
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3974365091
Short name T970
Test name
Test status
Simulation time 13947500 ps
CPU time 15.79 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:13:45 PM PDT 24
Peak memory 275852 kb
Host smart-4b39cd90-7cd2-49f1-a2b1-c24097f7cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974365091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3974365091
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1655675800
Short name T372
Test name
Test status
Simulation time 11629500 ps
CPU time 20.22 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:13:54 PM PDT 24
Peak memory 274424 kb
Host smart-ffdd55b0-049f-47bb-a56e-f32896dd5405
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655675800 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1655675800
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1590705163
Short name T309
Test name
Test status
Simulation time 1630230700 ps
CPU time 52.12 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:14:24 PM PDT 24
Peak memory 262288 kb
Host smart-9c933f59-8634-4f56-90f7-d9934be95987
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590705163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1590705163
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.1219418523
Short name T960
Test name
Test status
Simulation time 5082863100 ps
CPU time 173.42 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 290432 kb
Host smart-69110e46-40b8-4385-8490-d79fb8bcd034
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219418523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.1219418523
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.3895924105
Short name T945
Test name
Test status
Simulation time 29831000 ps
CPU time 30.52 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:14:02 PM PDT 24
Peak memory 274068 kb
Host smart-c5b4e7a8-9aef-4dd5-886c-3443b3cbf21b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895924105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.3895924105
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1892267554
Short name T32
Test name
Test status
Simulation time 45579300 ps
CPU time 28.09 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 275128 kb
Host smart-aa090212-d22f-4577-acdc-baaf9d0231d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892267554 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1892267554
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3403793423
Short name T406
Test name
Test status
Simulation time 1182868200 ps
CPU time 53.38 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:26 PM PDT 24
Peak memory 262080 kb
Host smart-2705800e-b223-4be2-98d2-3bbbf7a7d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403793423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3403793423
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.1406953045
Short name T439
Test name
Test status
Simulation time 71718400 ps
CPU time 147.36 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 276192 kb
Host smart-09efa8a4-33b9-4b24-bb1d-8d972dfb4fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406953045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1406953045
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1182698288
Short name T57
Test name
Test status
Simulation time 44817600 ps
CPU time 13.54 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:13:46 PM PDT 24
Peak memory 257936 kb
Host smart-df81beda-bfa7-402e-8a70-4682e0180c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182698288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1182698288
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.3326911970
Short name T641
Test name
Test status
Simulation time 14894600 ps
CPU time 13.32 seconds
Started May 30 01:13:32 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 275936 kb
Host smart-d78d1919-b9fb-4fdf-be37-e301f62f0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326911970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3326911970
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.4100172167
Short name T1090
Test name
Test status
Simulation time 2215778200 ps
CPU time 171.05 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 259140 kb
Host smart-63f855f2-b8f1-49aa-be8f-f69387d440e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100172167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.4100172167
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.4201489740
Short name T522
Test name
Test status
Simulation time 6294133600 ps
CPU time 167.1 seconds
Started May 30 01:13:32 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 289476 kb
Host smart-0f69f96a-a467-40e5-9e0a-af9021b614c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201489740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.4201489740
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2580202307
Short name T591
Test name
Test status
Simulation time 5987930400 ps
CPU time 153.13 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:16:07 PM PDT 24
Peak memory 292960 kb
Host smart-39881a16-3d50-43b9-94b1-284f3033693c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580202307 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2580202307
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.1699157707
Short name T108
Test name
Test status
Simulation time 247075700 ps
CPU time 109.97 seconds
Started May 30 01:13:31 PM PDT 24
Finished May 30 01:15:24 PM PDT 24
Peak memory 259852 kb
Host smart-9d10f0a1-62ef-44f6-bb66-3035b34e9136
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699157707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.1699157707
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.3749246772
Short name T175
Test name
Test status
Simulation time 36020700 ps
CPU time 28.01 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:01 PM PDT 24
Peak memory 266952 kb
Host smart-b2c9e8fe-e1e9-4c0b-aab0-d0975d8ba311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749246772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.3749246772
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1801479833
Short name T847
Test name
Test status
Simulation time 685075600 ps
CPU time 69.11 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 263032 kb
Host smart-b8275b6b-218a-4ecc-bcbc-d505a20a169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801479833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1801479833
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.353239801
Short name T724
Test name
Test status
Simulation time 70461200 ps
CPU time 166.02 seconds
Started May 30 01:13:27 PM PDT 24
Finished May 30 01:16:15 PM PDT 24
Peak memory 276388 kb
Host smart-230d92af-5319-44f6-afb6-a75bc728d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353239801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.353239801
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3657950175
Short name T483
Test name
Test status
Simulation time 71395500 ps
CPU time 13.55 seconds
Started May 30 01:13:40 PM PDT 24
Finished May 30 01:13:54 PM PDT 24
Peak memory 257752 kb
Host smart-d4417411-7433-4e44-a9c7-421863c89461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657950175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3657950175
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2579729282
Short name T1022
Test name
Test status
Simulation time 16910300 ps
CPU time 13.35 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 275524 kb
Host smart-59d050a8-5f1a-44a8-bc8a-ee5302f871c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579729282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2579729282
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.2556618741
Short name T525
Test name
Test status
Simulation time 35516900 ps
CPU time 20.03 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:02 PM PDT 24
Peak memory 273176 kb
Host smart-d203aba1-b2b4-4b67-b584-9748804a2eb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556618741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.2556618741
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2158763688
Short name T520
Test name
Test status
Simulation time 21071342200 ps
CPU time 160.96 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:16:13 PM PDT 24
Peak memory 262248 kb
Host smart-c87f7f28-1c7b-44ae-b530-1f84335b4561
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158763688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2158763688
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.4042695688
Short name T1014
Test name
Test status
Simulation time 1060306500 ps
CPU time 114.76 seconds
Started May 30 01:13:32 PM PDT 24
Finished May 30 01:15:29 PM PDT 24
Peak memory 289452 kb
Host smart-ddefb136-5a5d-4244-9853-afec32678ab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042695688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.4042695688
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.619248703
Short name T711
Test name
Test status
Simulation time 27783815500 ps
CPU time 131.32 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 293012 kb
Host smart-0fbe81d3-4f64-40d1-9735-30a33fc255c1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619248703 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.619248703
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.248423640
Short name T96
Test name
Test status
Simulation time 71418200 ps
CPU time 131.03 seconds
Started May 30 01:13:29 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 259492 kb
Host smart-1c9fdd3c-3f8a-419e-87d0-021df43ee022
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248423640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.248423640
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.4029058818
Short name T442
Test name
Test status
Simulation time 32188400 ps
CPU time 28.89 seconds
Started May 30 01:13:30 PM PDT 24
Finished May 30 01:14:02 PM PDT 24
Peak memory 266904 kb
Host smart-005ce20c-e280-4948-8764-2f4e8a90bcf2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029058818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.4029058818
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3052082598
Short name T206
Test name
Test status
Simulation time 54444300 ps
CPU time 31.49 seconds
Started May 30 01:13:33 PM PDT 24
Finished May 30 01:14:06 PM PDT 24
Peak memory 275156 kb
Host smart-d550c6cd-779c-4bd9-93d1-bb537559ce73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052082598 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3052082598
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.2557082527
Short name T821
Test name
Test status
Simulation time 754385300 ps
CPU time 60.26 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 262428 kb
Host smart-06f90af2-0a7b-4a69-8d67-ba9bcdf8e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557082527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2557082527
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.2038013443
Short name T789
Test name
Test status
Simulation time 94619100 ps
CPU time 120.48 seconds
Started May 30 01:13:33 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 275580 kb
Host smart-47f61bcc-bafa-4971-9108-5bde23e0d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038013443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2038013443
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.1273195824
Short name T422
Test name
Test status
Simulation time 31476600 ps
CPU time 13.6 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:13:56 PM PDT 24
Peak memory 257928 kb
Host smart-cca4d1cf-29e0-4872-bf77-fcfcf91ad57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273195824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
1273195824
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.654591222
Short name T623
Test name
Test status
Simulation time 24579600 ps
CPU time 15.29 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:59 PM PDT 24
Peak memory 275872 kb
Host smart-9e2b8f4f-f165-43cf-a216-cfd6bd6d4e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654591222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.654591222
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3976779170
Short name T367
Test name
Test status
Simulation time 10050300 ps
CPU time 20.82 seconds
Started May 30 01:13:44 PM PDT 24
Finished May 30 01:14:06 PM PDT 24
Peak memory 272928 kb
Host smart-222b6687-6c61-4ede-afb7-b581d35dd393
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976779170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3976779170
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1511710932
Short name T314
Test name
Test status
Simulation time 14670928700 ps
CPU time 56.59 seconds
Started May 30 01:13:44 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 262408 kb
Host smart-a81c49b6-223d-42c3-baf5-8c80f86f954d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511710932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.1511710932
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2283474828
Short name T565
Test name
Test status
Simulation time 2374111300 ps
CPU time 216.75 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 289492 kb
Host smart-ead0b6fe-ee6d-4cc3-948a-0c06accf0fc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283474828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2283474828
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1199492883
Short name T408
Test name
Test status
Simulation time 15707988900 ps
CPU time 167.4 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 291564 kb
Host smart-8ed751f2-faed-4f4b-9e35-e1ab4d8c31e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199492883 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1199492883
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3468866613
Short name T523
Test name
Test status
Simulation time 43074400 ps
CPU time 110.33 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 259752 kb
Host smart-59de8806-9fad-4f0d-b84c-134cbf116537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468866613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3468866613
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1622953607
Short name T334
Test name
Test status
Simulation time 73354100 ps
CPU time 30.72 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:12 PM PDT 24
Peak memory 275208 kb
Host smart-b5c692bd-9f29-4453-9dc1-5f1d289e24bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622953607 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1622953607
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.3913033617
Short name T392
Test name
Test status
Simulation time 3663475600 ps
CPU time 74.03 seconds
Started May 30 01:13:45 PM PDT 24
Finished May 30 01:15:00 PM PDT 24
Peak memory 262984 kb
Host smart-311a4143-cd91-4d32-b09a-2e7beebfb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913033617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3913033617
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.2602470521
Short name T579
Test name
Test status
Simulation time 28379000 ps
CPU time 97.02 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:15:19 PM PDT 24
Peak memory 275496 kb
Host smart-65aff9b7-e5bc-4283-97cc-6870161e09ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602470521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2602470521
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.4228167982
Short name T504
Test name
Test status
Simulation time 50434600 ps
CPU time 13.57 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:10:29 PM PDT 24
Peak memory 257912 kb
Host smart-032a1cc8-13df-4a14-b191-3d6c8b382e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228167982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.4
228167982
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1200482489
Short name T852
Test name
Test status
Simulation time 16438500 ps
CPU time 15.41 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:10:28 PM PDT 24
Peak memory 275868 kb
Host smart-911055c6-0ea0-4e79-b4f0-852a634bf1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200482489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1200482489
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1291114654
Short name T246
Test name
Test status
Simulation time 174981600 ps
CPU time 103.03 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:11:53 PM PDT 24
Peak memory 281296 kb
Host smart-8d274700-e8d7-4d65-ac69-c476ae3b6331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291114654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1291114654
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.3644991804
Short name T137
Test name
Test status
Simulation time 52671800 ps
CPU time 20.33 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 273156 kb
Host smart-9c6634d8-0ad1-4c70-80e3-9d10528eaa7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644991804 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.3644991804
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.348256069
Short name T971
Test name
Test status
Simulation time 4356479100 ps
CPU time 292.99 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 262828 kb
Host smart-b9af2bbd-4139-4cd2-b723-0685823a09c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348256069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.348256069
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.3211542680
Short name T827
Test name
Test status
Simulation time 27754169400 ps
CPU time 2295.71 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:48:16 PM PDT 24
Peak memory 264404 kb
Host smart-50125cb1-1e56-410a-a27f-1c8f6c0f7310
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211542680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.3211542680
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.3178364255
Short name T163
Test name
Test status
Simulation time 673959900 ps
CPU time 2902.54 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:58:25 PM PDT 24
Peak memory 264772 kb
Host smart-3420c6e6-aa58-4e76-8aab-68139696c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178364255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3178364255
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.4023152084
Short name T950
Test name
Test status
Simulation time 1560602200 ps
CPU time 733.21 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:22:13 PM PDT 24
Peak memory 264832 kb
Host smart-964a1086-8603-49af-bddd-e17de4a67dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023152084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.4023152084
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1058456631
Short name T55
Test name
Test status
Simulation time 330480100 ps
CPU time 21.53 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:28 PM PDT 24
Peak memory 264872 kb
Host smart-83db7158-e34b-4c91-a482-1b5b1cd11f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058456631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1058456631
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.2993264102
Short name T969
Test name
Test status
Simulation time 660889700 ps
CPU time 37.18 seconds
Started May 30 01:10:09 PM PDT 24
Finished May 30 01:10:48 PM PDT 24
Peak memory 261960 kb
Host smart-542866a5-4737-4aeb-8280-268eb88c0006
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993264102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.2993264102
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.2326177516
Short name T993
Test name
Test status
Simulation time 96907559700 ps
CPU time 2644.39 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:54:10 PM PDT 24
Peak memory 262984 kb
Host smart-6ac13b69-b581-4587-a213-c184f5605594
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326177516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.2326177516
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.602285015
Short name T596
Test name
Test status
Simulation time 75800500 ps
CPU time 72.04 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:11:11 PM PDT 24
Peak memory 262300 kb
Host smart-8237f253-8927-43a7-aff9-049f2d61ae03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602285015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.602285015
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.22919530
Short name T1023
Test name
Test status
Simulation time 10011945100 ps
CPU time 155.77 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 397280 kb
Host smart-e15eb0b1-99a5-490a-9a1f-b144ed99dfa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22919530 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.22919530
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3377378997
Short name T275
Test name
Test status
Simulation time 47188400 ps
CPU time 13.69 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:10:30 PM PDT 24
Peak memory 258116 kb
Host smart-b15b6b85-46c6-4f39-b43e-6b2dc7f2c6cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377378997 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3377378997
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.4229717363
Short name T460
Test name
Test status
Simulation time 40127692700 ps
CPU time 827.58 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:23:49 PM PDT 24
Peak memory 263076 kb
Host smart-eb9ba1a0-1f2d-4d03-9f75-9a3283a77dbd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229717363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.4229717363
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.420963913
Short name T630
Test name
Test status
Simulation time 15417377000 ps
CPU time 119.55 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:12:05 PM PDT 24
Peak memory 262448 kb
Host smart-62d20323-6b8b-4604-b277-f50feebc43a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420963913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw
_sec_otp.420963913
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.545860806
Short name T38
Test name
Test status
Simulation time 9265909000 ps
CPU time 164.91 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:12:55 PM PDT 24
Peak memory 289544 kb
Host smart-914820b0-df41-4ac3-8ca9-1d1e5a9ec243
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545860806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_intr_rd.545860806
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1112338749
Short name T897
Test name
Test status
Simulation time 23090112600 ps
CPU time 119.33 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:12:09 PM PDT 24
Peak memory 291764 kb
Host smart-65fa9672-dfb1-46b1-a87d-61a9e6ece144
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112338749 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.1112338749
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.1853409947
Short name T883
Test name
Test status
Simulation time 2389561500 ps
CPU time 65.17 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:11:11 PM PDT 24
Peak memory 259540 kb
Host smart-d4b2bb55-7dd7-49ac-9db5-f864255f585c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853409947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.1853409947
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3760062762
Short name T632
Test name
Test status
Simulation time 21086505500 ps
CPU time 192.2 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:13:21 PM PDT 24
Peak memory 264836 kb
Host smart-e51c5bf2-e9f2-45fc-8e8e-cb0c21fa5444
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376
0062762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3760062762
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2186634125
Short name T182
Test name
Test status
Simulation time 990478600 ps
CPU time 82.74 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:11:22 PM PDT 24
Peak memory 260528 kb
Host smart-36ea0297-ae5e-424b-9eb6-d9894db372b3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186634125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2186634125
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.4206415244
Short name T1083
Test name
Test status
Simulation time 31260400 ps
CPU time 13.13 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:10:23 PM PDT 24
Peak memory 264764 kb
Host smart-7962b6f5-52eb-4b2f-bacb-73b5902b143c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206415244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.4206415244
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.4145611621
Short name T939
Test name
Test status
Simulation time 17924655600 ps
CPU time 165.25 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:12:45 PM PDT 24
Peak memory 261528 kb
Host smart-b715fc38-e35c-42d9-ad4c-52b7d2331dae
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145611621 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.4145611621
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2116559134
Short name T1021
Test name
Test status
Simulation time 204629600 ps
CPU time 130.54 seconds
Started May 30 01:09:56 PM PDT 24
Finished May 30 01:12:08 PM PDT 24
Peak memory 263812 kb
Host smart-3ae0ecf3-b950-4816-9aac-c3e595552b4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116559134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2116559134
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3476471486
Short name T607
Test name
Test status
Simulation time 8925536000 ps
CPU time 176.66 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:13:02 PM PDT 24
Peak memory 281256 kb
Host smart-c472be76-97f7-4189-a3e1-4ae58738ee66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476471486 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3476471486
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1345890553
Short name T66
Test name
Test status
Simulation time 54075100 ps
CPU time 13.56 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:10:23 PM PDT 24
Peak memory 277716 kb
Host smart-e4949fce-886c-48f3-9843-35bb990b112c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1345890553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1345890553
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1521560268
Short name T768
Test name
Test status
Simulation time 171014200 ps
CPU time 152.92 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:12:40 PM PDT 24
Peak memory 262112 kb
Host smart-9b7e02e6-b015-4399-acdc-2a5b120e13db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521560268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1521560268
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2523801969
Short name T183
Test name
Test status
Simulation time 886220200 ps
CPU time 21.07 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:10:31 PM PDT 24
Peak memory 264488 kb
Host smart-dd97be22-560d-4e6f-973e-728c913f5390
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523801969 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2523801969
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.7653498
Short name T151
Test name
Test status
Simulation time 104714000 ps
CPU time 13.65 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 261684 kb
Host smart-33cf9ab1-f71c-42ae-9ef0-ed31dbd13e66
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7653498 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.7653498
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.858171072
Short name T383
Test name
Test status
Simulation time 19481200 ps
CPU time 13.25 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:19 PM PDT 24
Peak memory 258436 kb
Host smart-6c9fce80-5dfb-4330-96b7-dfec5e506fb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858171072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.858171072
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2160142035
Short name T996
Test name
Test status
Simulation time 5705438000 ps
CPU time 980.23 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:26:20 PM PDT 24
Peak memory 283212 kb
Host smart-821ed625-44fa-45b2-b94a-e0a3f30a8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160142035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2160142035
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2927848904
Short name T267
Test name
Test status
Simulation time 1459131700 ps
CPU time 121.13 seconds
Started May 30 01:09:59 PM PDT 24
Finished May 30 01:12:01 PM PDT 24
Peak memory 264828 kb
Host smart-52c1f32a-498f-4160-97d8-34ea8ac67e2d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2927848904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2927848904
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.4078221582
Short name T448
Test name
Test status
Simulation time 332616500 ps
CPU time 34.39 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:10:47 PM PDT 24
Peak memory 274400 kb
Host smart-2cba4357-451c-49c5-9c21-beb02d9cb65e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078221582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.4078221582
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2165437293
Short name T521
Test name
Test status
Simulation time 18239000 ps
CPU time 22.2 seconds
Started May 30 01:10:01 PM PDT 24
Finished May 30 01:10:24 PM PDT 24
Peak memory 264808 kb
Host smart-d4876265-fa20-4ce7-9a60-352060639c18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165437293 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.2165437293
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2553379506
Short name T562
Test name
Test status
Simulation time 25731300 ps
CPU time 22.56 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:10:32 PM PDT 24
Peak memory 264268 kb
Host smart-b6a4c14a-62a8-4467-8720-2dc4a35ce7b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553379506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2553379506
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1000919964
Short name T764
Test name
Test status
Simulation time 4487840400 ps
CPU time 117.65 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:12:03 PM PDT 24
Peak memory 281224 kb
Host smart-4861b441-dc8d-4b9e-abe8-ff635896eab1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000919964 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.1000919964
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.3147989994
Short name T208
Test name
Test status
Simulation time 1023616500 ps
CPU time 134.42 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:12:21 PM PDT 24
Peak memory 281212 kb
Host smart-dc06f0b8-3592-4a40-854b-fa3874e64c51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3147989994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3147989994
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.4184665543
Short name T729
Test name
Test status
Simulation time 2322202700 ps
CPU time 133.78 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:12:24 PM PDT 24
Peak memory 281232 kb
Host smart-e6c563c7-0b80-4479-a3ba-16943998a8c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184665543 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.4184665543
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.1020300359
Short name T192
Test name
Test status
Simulation time 41758803900 ps
CPU time 525.17 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:18:50 PM PDT 24
Peak memory 313056 kb
Host smart-0270b301-8bb3-4e0e-886e-406f65dc49ad
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020300359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.1020300359
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1633142139
Short name T328
Test name
Test status
Simulation time 42573800 ps
CPU time 27.96 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 275964 kb
Host smart-384fa9d7-8282-4080-bffd-2719c4c4a9ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633142139 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1633142139
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3447383292
Short name T64
Test name
Test status
Simulation time 3837656000 ps
CPU time 4704.32 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 02:28:33 PM PDT 24
Peak memory 284860 kb
Host smart-d1cc73f2-5f18-4c01-be5b-ac1996471f85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447383292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3447383292
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.4146332219
Short name T1003
Test name
Test status
Simulation time 1907291400 ps
CPU time 65.87 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:11:15 PM PDT 24
Peak memory 261860 kb
Host smart-1812a318-3cd9-4fd3-b456-0fa405585e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146332219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.4146332219
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1262479125
Short name T603
Test name
Test status
Simulation time 1008810000 ps
CPU time 86.83 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:11:36 PM PDT 24
Peak memory 264768 kb
Host smart-0774a7a8-78c7-47fd-9a24-64dd8efad095
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262479125 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1262479125
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.2607130880
Short name T449
Test name
Test status
Simulation time 827462600 ps
CPU time 84.89 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:11:31 PM PDT 24
Peak memory 273096 kb
Host smart-f322336c-586b-413e-b5ac-dca5fdf3bc84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607130880 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.2607130880
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2531123723
Short name T895
Test name
Test status
Simulation time 23510800 ps
CPU time 52.22 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:10:51 PM PDT 24
Peak memory 270412 kb
Host smart-9de0aa84-866c-47c6-98f8-5c8aa018d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531123723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2531123723
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.272089999
Short name T848
Test name
Test status
Simulation time 28232900 ps
CPU time 25.96 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:10:25 PM PDT 24
Peak memory 258900 kb
Host smart-18001bed-e7c6-4da3-8814-179b7d456f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272089999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.272089999
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.4207683301
Short name T377
Test name
Test status
Simulation time 190060200 ps
CPU time 255.31 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 281264 kb
Host smart-17dab8c8-a1cc-488e-b44d-0df79cbb2186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207683301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.4207683301
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.4151404532
Short name T968
Test name
Test status
Simulation time 25517000 ps
CPU time 26.63 seconds
Started May 30 01:09:57 PM PDT 24
Finished May 30 01:10:24 PM PDT 24
Peak memory 258756 kb
Host smart-f8310e89-0995-4e23-b11e-a4f48ccb8712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151404532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.4151404532
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.3263610938
Short name T578
Test name
Test status
Simulation time 2367809300 ps
CPU time 163.15 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:12:49 PM PDT 24
Peak memory 264792 kb
Host smart-1dbe141a-7db5-4312-9dbf-c364a7d3ad70
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263610938 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.3263610938
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.483785161
Short name T518
Test name
Test status
Simulation time 134357000 ps
CPU time 13.54 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 264776 kb
Host smart-e0718381-538f-4b12-b1e3-bcda9fdd97c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483785161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.483785161
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1191056947
Short name T2
Test name
Test status
Simulation time 24496900 ps
CPU time 15.79 seconds
Started May 30 01:13:40 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 275860 kb
Host smart-24316681-59ef-4c1f-9b13-c1a119ae5d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191056947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1191056947
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3769473461
Short name T856
Test name
Test status
Simulation time 28220500 ps
CPU time 22.07 seconds
Started May 30 01:13:44 PM PDT 24
Finished May 30 01:14:08 PM PDT 24
Peak memory 273116 kb
Host smart-cf6a034e-e245-4b7b-ba8a-1ad8f4fbe984
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769473461 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3769473461
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2542463472
Short name T1060
Test name
Test status
Simulation time 6440615900 ps
CPU time 189.97 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:16:53 PM PDT 24
Peak memory 262404 kb
Host smart-c43b8750-0972-4422-8faf-19773c67fcc3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542463472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.2542463472
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.3216688613
Short name T803
Test name
Test status
Simulation time 189399100 ps
CPU time 131.85 seconds
Started May 30 01:13:44 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 259796 kb
Host smart-6bb5ec65-c861-4000-9d06-fedb87696d38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216688613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.3216688613
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2541035382
Short name T637
Test name
Test status
Simulation time 3914725600 ps
CPU time 72.14 seconds
Started May 30 01:13:43 PM PDT 24
Finished May 30 01:14:56 PM PDT 24
Peak memory 259552 kb
Host smart-01ffb26e-938f-48de-84e1-c15e8a659ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541035382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2541035382
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1439212500
Short name T557
Test name
Test status
Simulation time 23101800 ps
CPU time 74.59 seconds
Started May 30 01:13:44 PM PDT 24
Finished May 30 01:15:00 PM PDT 24
Peak memory 274744 kb
Host smart-faf1856f-6d6f-41a3-a71e-e08f43f978d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439212500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1439212500
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2356743936
Short name T656
Test name
Test status
Simulation time 61276600 ps
CPU time 13.42 seconds
Started May 30 01:13:43 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 264800 kb
Host smart-57a35273-0e24-48ba-ac0d-b88190998522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356743936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2356743936
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2016451808
Short name T173
Test name
Test status
Simulation time 16125100 ps
CPU time 13.63 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 274940 kb
Host smart-0a5af914-96f3-4360-b475-9d1ec7c25a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016451808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2016451808
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.3020812798
Short name T468
Test name
Test status
Simulation time 15069800 ps
CPU time 21.81 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:03 PM PDT 24
Peak memory 273060 kb
Host smart-6f06000c-0285-48ee-a0f2-96e9648ff7c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020812798 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.3020812798
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1381074889
Short name T807
Test name
Test status
Simulation time 13109536500 ps
CPU time 85.8 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:15:09 PM PDT 24
Peak memory 262296 kb
Host smart-f05bb5da-8850-462a-8eb0-7e4816354ef2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381074889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1381074889
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.909700271
Short name T234
Test name
Test status
Simulation time 141601400 ps
CPU time 134.32 seconds
Started May 30 01:13:45 PM PDT 24
Finished May 30 01:16:00 PM PDT 24
Peak memory 260048 kb
Host smart-182b6d60-59fb-4904-9697-1694f658261c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909700271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.909700271
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2381506116
Short name T621
Test name
Test status
Simulation time 2364892900 ps
CPU time 62.07 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 262096 kb
Host smart-bb823f58-4efb-405a-8e33-80c96a6413a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381506116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2381506116
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2622010284
Short name T556
Test name
Test status
Simulation time 38449500 ps
CPU time 166.31 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:16:30 PM PDT 24
Peak memory 276316 kb
Host smart-34b637e6-90fb-4c0e-bb19-a25168dc9811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622010284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2622010284
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.1529709467
Short name T959
Test name
Test status
Simulation time 104384900 ps
CPU time 13.45 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:56 PM PDT 24
Peak memory 257948 kb
Host smart-82f32694-81bf-4411-bb4c-071c8b371042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529709467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
1529709467
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.397637227
Short name T503
Test name
Test status
Simulation time 23075900 ps
CPU time 15.78 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:13:59 PM PDT 24
Peak memory 275904 kb
Host smart-e47307ba-c4ec-4683-8ff3-44a5af03b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397637227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.397637227
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.746148471
Short name T136
Test name
Test status
Simulation time 12422100 ps
CPU time 22.08 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:03 PM PDT 24
Peak memory 280124 kb
Host smart-f26e67ce-d2b7-4f03-b109-30ffc0fa038b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746148471 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.746148471
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3681991496
Short name T635
Test name
Test status
Simulation time 2388710900 ps
CPU time 82.06 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:15:06 PM PDT 24
Peak memory 262232 kb
Host smart-d317c1ec-7e77-4758-847f-3a2ac5285fb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681991496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.3681991496
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2800743217
Short name T650
Test name
Test status
Simulation time 159843900 ps
CPU time 134.46 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:15:58 PM PDT 24
Peak memory 259836 kb
Host smart-e116d8fb-facb-4651-9051-2605b6c44d5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800743217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2800743217
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.648966172
Short name T874
Test name
Test status
Simulation time 1912268100 ps
CPU time 63.12 seconds
Started May 30 01:13:43 PM PDT 24
Finished May 30 01:14:48 PM PDT 24
Peak memory 262748 kb
Host smart-aa51a8e2-12bc-4986-8f7a-63bb1c6308e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648966172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.648966172
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.50746779
Short name T438
Test name
Test status
Simulation time 54428700 ps
CPU time 147.83 seconds
Started May 30 01:13:45 PM PDT 24
Finished May 30 01:16:14 PM PDT 24
Peak memory 276032 kb
Host smart-87db12c9-f4b4-4e9f-8051-926ac976a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50746779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.50746779
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.1745177638
Short name T178
Test name
Test status
Simulation time 123315000 ps
CPU time 13.73 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:09 PM PDT 24
Peak memory 264720 kb
Host smart-4b7ec609-772c-48f2-a2eb-02fed9ea6bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745177638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
1745177638
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1117744869
Short name T833
Test name
Test status
Simulation time 51706300 ps
CPU time 15.65 seconds
Started May 30 01:13:56 PM PDT 24
Finished May 30 01:14:12 PM PDT 24
Peak memory 275796 kb
Host smart-7ee052cc-d46b-422f-aebf-5d20404c2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117744869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1117744869
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2057066287
Short name T900
Test name
Test status
Simulation time 11955600 ps
CPU time 22.54 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:14:06 PM PDT 24
Peak memory 273252 kb
Host smart-4f52a330-9905-4f0b-a2bb-892e895d58a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057066287 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2057066287
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.4023062632
Short name T528
Test name
Test status
Simulation time 2053025500 ps
CPU time 50.37 seconds
Started May 30 01:13:43 PM PDT 24
Finished May 30 01:14:35 PM PDT 24
Peak memory 261796 kb
Host smart-1a8b62c7-e6c9-4075-891b-b0c819dbf194
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023062632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.4023062632
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1086295353
Short name T760
Test name
Test status
Simulation time 137227800 ps
CPU time 128.3 seconds
Started May 30 01:13:43 PM PDT 24
Finished May 30 01:15:53 PM PDT 24
Peak memory 259500 kb
Host smart-1e6852fa-df3f-4c9e-9a6c-3322f0edb686
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086295353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1086295353
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3291797873
Short name T1007
Test name
Test status
Simulation time 1590018200 ps
CPU time 52.05 seconds
Started May 30 01:13:41 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 262392 kb
Host smart-3940c038-79b0-4ea8-b1ac-e643844e81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291797873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3291797873
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2053971838
Short name T510
Test name
Test status
Simulation time 29548400 ps
CPU time 143.56 seconds
Started May 30 01:13:42 PM PDT 24
Finished May 30 01:16:07 PM PDT 24
Peak memory 276172 kb
Host smart-2fba4e16-ef6b-4f63-9f87-57413d5744f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053971838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2053971838
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3277582026
Short name T829
Test name
Test status
Simulation time 69997800 ps
CPU time 13.57 seconds
Started May 30 01:13:54 PM PDT 24
Finished May 30 01:14:08 PM PDT 24
Peak memory 264764 kb
Host smart-9618765e-d18f-4b3c-a615-347230b7aba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277582026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3277582026
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3887239252
Short name T553
Test name
Test status
Simulation time 88737900 ps
CPU time 15.89 seconds
Started May 30 01:13:57 PM PDT 24
Finished May 30 01:14:13 PM PDT 24
Peak memory 275868 kb
Host smart-ac606f91-f7be-4dc1-9079-00e7ac938e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887239252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3887239252
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1521470453
Short name T97
Test name
Test status
Simulation time 10944800 ps
CPU time 21.67 seconds
Started May 30 01:13:54 PM PDT 24
Finished May 30 01:14:16 PM PDT 24
Peak memory 273168 kb
Host smart-e6fbecd5-fd79-4389-854e-0c1581120c79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521470453 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1521470453
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.866073423
Short name T1
Test name
Test status
Simulation time 19303785600 ps
CPU time 124.94 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:16:03 PM PDT 24
Peak memory 262204 kb
Host smart-2538c9cf-0a83-4be3-9add-9b8fb3569475
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866073423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_h
w_sec_otp.866073423
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.771867225
Short name T961
Test name
Test status
Simulation time 77566900 ps
CPU time 108.67 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 259676 kb
Host smart-a1f1b713-e2c8-472a-bc6e-882bfc90ae1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771867225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.771867225
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1355653273
Short name T148
Test name
Test status
Simulation time 2742001500 ps
CPU time 69.81 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:15:09 PM PDT 24
Peak memory 264304 kb
Host smart-4e87f086-71f1-476a-bbbc-94e469abe393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355653273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1355653273
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.4274668216
Short name T1069
Test name
Test status
Simulation time 22140800 ps
CPU time 76.94 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:15:12 PM PDT 24
Peak memory 274800 kb
Host smart-37780b7e-6709-4c60-b688-d6b2924fe3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274668216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.4274668216
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.1033760976
Short name T933
Test name
Test status
Simulation time 54609100 ps
CPU time 13.87 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:14:13 PM PDT 24
Peak memory 264784 kb
Host smart-91400f66-3638-4c3e-91c7-cf3fdf31e661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033760976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
1033760976
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.3169156956
Short name T838
Test name
Test status
Simulation time 14676200 ps
CPU time 13.42 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:09 PM PDT 24
Peak memory 275504 kb
Host smart-7b58bfff-35e3-40ad-ad78-ad2e2b539b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169156956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3169156956
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.3091783243
Short name T371
Test name
Test status
Simulation time 28529400 ps
CPU time 21.78 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:18 PM PDT 24
Peak memory 273180 kb
Host smart-54bd6dee-aa1e-49b9-ae7a-655c90e7b1aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091783243 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.3091783243
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3610681052
Short name T316
Test name
Test status
Simulation time 12331291600 ps
CPU time 269.26 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:18:25 PM PDT 24
Peak memory 262472 kb
Host smart-e4ff624b-f674-4640-923e-878675338a82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610681052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.3610681052
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.2081695270
Short name T424
Test name
Test status
Simulation time 44551800 ps
CPU time 130.29 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 259820 kb
Host smart-788e7985-c148-4322-ac80-dba0d64dccd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081695270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.2081695270
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3986079184
Short name T311
Test name
Test status
Simulation time 8269580800 ps
CPU time 62.44 seconds
Started May 30 01:13:56 PM PDT 24
Finished May 30 01:14:59 PM PDT 24
Peak memory 262928 kb
Host smart-b7111e53-efff-4f80-9fb0-ba5774f7bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986079184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3986079184
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.3281082505
Short name T549
Test name
Test status
Simulation time 308437500 ps
CPU time 168.41 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 276476 kb
Host smart-76c674d6-4f08-4ed5-9f8a-187dca6ce3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281082505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3281082505
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3497789573
Short name T445
Test name
Test status
Simulation time 37229100 ps
CPU time 13.36 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:14:12 PM PDT 24
Peak memory 264796 kb
Host smart-e46d78eb-32d3-433e-8fd5-b1199e485abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497789573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3497789573
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.3904330788
Short name T963
Test name
Test status
Simulation time 26526700 ps
CPU time 13.59 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:10 PM PDT 24
Peak memory 275832 kb
Host smart-e0dc0599-a18a-4bab-8205-3718e68915be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904330788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3904330788
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.735634254
Short name T628
Test name
Test status
Simulation time 15416400 ps
CPU time 22.34 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:18 PM PDT 24
Peak memory 273256 kb
Host smart-479b219c-e02e-4a3e-8230-da138b47b4be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735634254 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.735634254
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3593763395
Short name T543
Test name
Test status
Simulation time 2787594900 ps
CPU time 121.82 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:16:00 PM PDT 24
Peak memory 261768 kb
Host smart-fb7f99c0-97ed-4357-99c8-b4ed4d0b5735
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593763395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3593763395
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1730610418
Short name T930
Test name
Test status
Simulation time 149342700 ps
CPU time 134.12 seconds
Started May 30 01:13:56 PM PDT 24
Finished May 30 01:16:11 PM PDT 24
Peak memory 260544 kb
Host smart-73a493ff-da62-425c-8ab2-531233ef78bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730610418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1730610418
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.227519868
Short name T854
Test name
Test status
Simulation time 27458489800 ps
CPU time 87.64 seconds
Started May 30 01:13:58 PM PDT 24
Finished May 30 01:15:26 PM PDT 24
Peak memory 261868 kb
Host smart-5de2f54e-40b3-4b0f-b63e-64424eae4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227519868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.227519868
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3893686658
Short name T457
Test name
Test status
Simulation time 33659300 ps
CPU time 97.58 seconds
Started May 30 01:13:54 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 276468 kb
Host smart-14075b79-3860-424b-ad53-e61377aba688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893686658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3893686658
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.569733868
Short name T1081
Test name
Test status
Simulation time 35780300 ps
CPU time 13.66 seconds
Started May 30 01:13:56 PM PDT 24
Finished May 30 01:14:11 PM PDT 24
Peak memory 257852 kb
Host smart-e2818485-a159-4d16-81f4-3ac9e11b9e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569733868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.569733868
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.564556106
Short name T625
Test name
Test status
Simulation time 13662600 ps
CPU time 16.06 seconds
Started May 30 01:13:57 PM PDT 24
Finished May 30 01:14:14 PM PDT 24
Peak memory 274744 kb
Host smart-aa3777e0-fdb3-4989-9ea2-be5d98afd6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564556106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.564556106
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1208939472
Short name T139
Test name
Test status
Simulation time 38624400 ps
CPU time 21.75 seconds
Started May 30 01:13:59 PM PDT 24
Finished May 30 01:14:21 PM PDT 24
Peak memory 273108 kb
Host smart-318900fe-ff36-4082-9052-1a5469da4d14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208939472 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1208939472
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.4004517266
Short name T534
Test name
Test status
Simulation time 1472687400 ps
CPU time 50.92 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:14:47 PM PDT 24
Peak memory 261772 kb
Host smart-dca0902b-7224-479e-b60a-120840e35c2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004517266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.4004517266
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.841363990
Short name T906
Test name
Test status
Simulation time 567261800 ps
CPU time 48.48 seconds
Started May 30 01:13:56 PM PDT 24
Finished May 30 01:14:46 PM PDT 24
Peak memory 262892 kb
Host smart-132f80e2-5fdf-43e2-bafe-26c676d8dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841363990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.841363990
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.332500378
Short name T544
Test name
Test status
Simulation time 55722200 ps
CPU time 169.69 seconds
Started May 30 01:13:55 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 280072 kb
Host smart-db5c11f1-3efa-4612-a69a-fd1a526ae414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332500378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.332500378
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.2700509606
Short name T305
Test name
Test status
Simulation time 80858000 ps
CPU time 13.76 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:14:26 PM PDT 24
Peak memory 257764 kb
Host smart-e8af50e1-3ae5-436e-a6fe-79a5f4071f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700509606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
2700509606
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3367187654
Short name T1013
Test name
Test status
Simulation time 45100700 ps
CPU time 15.79 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:14:28 PM PDT 24
Peak memory 275776 kb
Host smart-b545065c-9b13-4efa-9cd4-a1cf805ef992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367187654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3367187654
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1038702463
Short name T368
Test name
Test status
Simulation time 24170900 ps
CPU time 20.45 seconds
Started May 30 01:14:13 PM PDT 24
Finished May 30 01:14:35 PM PDT 24
Peak memory 272964 kb
Host smart-42009146-a2e5-42e3-b5a5-bdd9ad6a2420
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038702463 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1038702463
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1378743963
Short name T749
Test name
Test status
Simulation time 2801460300 ps
CPU time 220.4 seconds
Started May 30 01:13:54 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 262296 kb
Host smart-73cf3553-6cd4-49d7-b98e-0052424860c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378743963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.1378743963
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3192678485
Short name T766
Test name
Test status
Simulation time 34818200 ps
CPU time 110.66 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:16:02 PM PDT 24
Peak memory 263232 kb
Host smart-ddd81954-a8d4-42c6-b15b-739a0a21120a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192678485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3192678485
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3245529540
Short name T397
Test name
Test status
Simulation time 1969851000 ps
CPU time 69.23 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 259460 kb
Host smart-e26bb7b1-fde5-469a-930a-6484b896dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245529540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3245529540
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.1113625475
Short name T376
Test name
Test status
Simulation time 22733000 ps
CPU time 52.46 seconds
Started May 30 01:13:57 PM PDT 24
Finished May 30 01:14:50 PM PDT 24
Peak memory 270356 kb
Host smart-942155c3-91d4-428c-a811-1d5885d0e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113625475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1113625475
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.1101964426
Short name T851
Test name
Test status
Simulation time 90253500 ps
CPU time 13.42 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:14:28 PM PDT 24
Peak memory 257880 kb
Host smart-a4fadfcd-1109-44a6-8b44-7ff3c43f8026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101964426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
1101964426
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.771914930
Short name T552
Test name
Test status
Simulation time 23526200 ps
CPU time 15.93 seconds
Started May 30 01:14:14 PM PDT 24
Finished May 30 01:14:31 PM PDT 24
Peak memory 275516 kb
Host smart-1bd67804-07e2-44a7-9055-b9d5b6308919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771914930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.771914930
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.2088199803
Short name T1076
Test name
Test status
Simulation time 60591600 ps
CPU time 22.04 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 264876 kb
Host smart-f450b930-bc2e-4cc1-9251-cb7df8d0cef4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088199803 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.2088199803
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.500599859
Short name T319
Test name
Test status
Simulation time 9491777300 ps
CPU time 191.7 seconds
Started May 30 01:14:15 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 262416 kb
Host smart-3521859a-ce48-4882-93d8-d5becd85fe80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500599859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h
w_sec_otp.500599859
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.248474684
Short name T1095
Test name
Test status
Simulation time 40541000 ps
CPU time 134.12 seconds
Started May 30 01:14:15 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 260960 kb
Host smart-f1106d1a-ed67-4a1f-9857-a1f72169fdc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248474684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.248474684
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.1401288714
Short name T876
Test name
Test status
Simulation time 2761897400 ps
CPU time 70.15 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:15:23 PM PDT 24
Peak memory 262380 kb
Host smart-290914ba-53c6-4228-a48c-b78b8dcba67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401288714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.1401288714
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2412386549
Short name T524
Test name
Test status
Simulation time 49715900 ps
CPU time 48.9 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:15:03 PM PDT 24
Peak memory 270344 kb
Host smart-08eb0419-ba1d-476e-a400-8507bad5494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412386549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2412386549
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.2236535588
Short name T678
Test name
Test status
Simulation time 58981900 ps
CPU time 13.84 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 264812 kb
Host smart-c1e75d2e-2875-403c-b8d2-a4777deb9c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236535588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2
236535588
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.2469331985
Short name T732
Test name
Test status
Simulation time 16771400 ps
CPU time 15.68 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:22 PM PDT 24
Peak memory 275844 kb
Host smart-0f88d872-55ee-438a-ac3c-f4268496600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469331985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2469331985
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3664743513
Short name T370
Test name
Test status
Simulation time 34923900 ps
CPU time 21.49 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:10:29 PM PDT 24
Peak memory 273220 kb
Host smart-e71d9d56-853f-4ddd-b79f-87365edd9798
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664743513 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3664743513
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2993890674
Short name T219
Test name
Test status
Simulation time 6066092500 ps
CPU time 2247.01 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:47:34 PM PDT 24
Peak memory 264156 kb
Host smart-3d817e3e-b556-4334-8c75-cf01f11cf730
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993890674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2993890674
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1084564829
Short name T535
Test name
Test status
Simulation time 1267912200 ps
CPU time 782.11 seconds
Started May 30 01:10:02 PM PDT 24
Finished May 30 01:23:05 PM PDT 24
Peak memory 272968 kb
Host smart-5e0dc19f-43bc-4816-a6ce-b9e491f8ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084564829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1084564829
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1735091758
Short name T1087
Test name
Test status
Simulation time 369221600 ps
CPU time 21.66 seconds
Started May 30 01:10:11 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 264848 kb
Host smart-8c6e2077-6c44-4398-8cf7-3d728a039149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735091758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1735091758
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1361301785
Short name T218
Test name
Test status
Simulation time 10019473300 ps
CPU time 86.57 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 325752 kb
Host smart-d7824782-fd51-4b55-8f15-ee7eed13182d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361301785 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1361301785
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.794131504
Short name T501
Test name
Test status
Simulation time 47204200 ps
CPU time 13.12 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 258008 kb
Host smart-ce902f4d-4854-46fd-812d-4c5c83532cda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794131504 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.794131504
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3088184400
Short name T935
Test name
Test status
Simulation time 170197747400 ps
CPU time 943.93 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:25:50 PM PDT 24
Peak memory 263636 kb
Host smart-97791a54-d186-42a2-a25a-34b7fc9c31df
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088184400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3088184400
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1592338088
Short name T699
Test name
Test status
Simulation time 3634325500 ps
CPU time 112.9 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:11:52 PM PDT 24
Peak memory 262084 kb
Host smart-1bc70768-2271-4e7e-8aed-61a172e95924
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592338088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1592338088
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.2145173446
Short name T779
Test name
Test status
Simulation time 3937167800 ps
CPU time 134.16 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:12:19 PM PDT 24
Peak memory 292780 kb
Host smart-4c7d3941-2600-43e2-bc37-bb652c2774a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145173446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.2145173446
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.731616159
Short name T706
Test name
Test status
Simulation time 50896774900 ps
CPU time 296.21 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:15:02 PM PDT 24
Peak memory 293000 kb
Host smart-a29bee67-01da-40fb-b79e-02fd3ff5c94b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731616159 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.731616159
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.1271891575
Short name T634
Test name
Test status
Simulation time 2410051100 ps
CPU time 71.05 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 259536 kb
Host smart-77a8a817-dcc7-469e-9ce5-ca95bcf2350c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271891575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.1271891575
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3989732528
Short name T780
Test name
Test status
Simulation time 32022880700 ps
CPU time 211.38 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:13:36 PM PDT 24
Peak memory 264688 kb
Host smart-f1b45937-196d-476f-9955-60d414191312
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398
9732528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3989732528
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3030669029
Short name T867
Test name
Test status
Simulation time 2440264700 ps
CPU time 86.25 seconds
Started May 30 01:10:11 PM PDT 24
Finished May 30 01:11:38 PM PDT 24
Peak memory 259452 kb
Host smart-16c94246-5640-4297-8fa7-08a3ced07fb2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030669029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3030669029
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.4157360651
Short name T279
Test name
Test status
Simulation time 48876300 ps
CPU time 13.09 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:10:22 PM PDT 24
Peak memory 260180 kb
Host smart-1144d408-3f1a-4c13-9d03-87a6c742edfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157360651 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.4157360651
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2333823620
Short name T115
Test name
Test status
Simulation time 47305445000 ps
CPU time 407.9 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 273612 kb
Host smart-2b928129-f915-4f34-90eb-eb452fd93f30
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333823620 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2333823620
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2044190328
Short name T619
Test name
Test status
Simulation time 41579700 ps
CPU time 109.51 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:11:56 PM PDT 24
Peak memory 259776 kb
Host smart-c48ae0ad-35bc-4ae8-9ebd-708dfac19abd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044190328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2044190328
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1959131847
Short name T185
Test name
Test status
Simulation time 73116400 ps
CPU time 156.28 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 261188 kb
Host smart-dbc9ac8a-e39a-46b9-87c8-2af311c7a407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959131847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1959131847
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3481636144
Short name T972
Test name
Test status
Simulation time 72305500 ps
CPU time 13.32 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:10:21 PM PDT 24
Peak memory 258332 kb
Host smart-5041ff50-8ec2-4d22-8099-69209e0723b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481636144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3481636144
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.244251014
Short name T112
Test name
Test status
Simulation time 1511858700 ps
CPU time 1311.58 seconds
Started May 30 01:10:10 PM PDT 24
Finished May 30 01:32:03 PM PDT 24
Peak memory 287032 kb
Host smart-4f21ce81-9502-4cfd-9571-f3309eeea89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244251014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.244251014
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.418375470
Short name T976
Test name
Test status
Simulation time 79683300 ps
CPU time 30.92 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:10:41 PM PDT 24
Peak memory 274128 kb
Host smart-50f80b2b-0f5c-42ac-a5fc-e4e05dd66925
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418375470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_re_evict.418375470
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2755405627
Short name T199
Test name
Test status
Simulation time 5666439400 ps
CPU time 133.9 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:12:24 PM PDT 24
Peak memory 296656 kb
Host smart-43913e9d-4049-4a69-b6e0-09a61b3248e4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755405627 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2755405627
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.2918458041
Short name T194
Test name
Test status
Simulation time 2279762800 ps
CPU time 137.47 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:12:24 PM PDT 24
Peak memory 281288 kb
Host smart-8efd8291-3591-457a-ae3c-8554e2ddaaec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2918458041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2918458041
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2833991478
Short name T698
Test name
Test status
Simulation time 448493700 ps
CPU time 124.24 seconds
Started May 30 01:10:03 PM PDT 24
Finished May 30 01:12:09 PM PDT 24
Peak memory 281276 kb
Host smart-e3cff7e2-bc86-48d9-9a78-c2a36e4d6eaf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833991478 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2833991478
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.2195738098
Short name T1045
Test name
Test status
Simulation time 6543267800 ps
CPU time 463.64 seconds
Started May 30 01:10:10 PM PDT 24
Finished May 30 01:17:55 PM PDT 24
Peak memory 309196 kb
Host smart-d722a8db-42e5-47f0-91e5-6aae99a0960e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195738098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.2195738098
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.808928124
Short name T857
Test name
Test status
Simulation time 8340167100 ps
CPU time 614.34 seconds
Started May 30 01:09:58 PM PDT 24
Finished May 30 01:20:14 PM PDT 24
Peak memory 311364 kb
Host smart-0210771c-7504-4c12-a8e7-1e19ba3b72ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808928124 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.808928124
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.3284251293
Short name T465
Test name
Test status
Simulation time 51230100 ps
CPU time 30.96 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:37 PM PDT 24
Peak memory 274112 kb
Host smart-ef69f3ca-1b68-40d5-9ae9-a8e0e9f16f0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284251293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.3284251293
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3467942927
Short name T1080
Test name
Test status
Simulation time 38323200 ps
CPU time 30.41 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:37 PM PDT 24
Peak memory 274476 kb
Host smart-0ad4e7c9-98e9-4277-abb1-07bfdfc68610
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467942927 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3467942927
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.3553790492
Short name T191
Test name
Test status
Simulation time 48016942900 ps
CPU time 680.65 seconds
Started May 30 01:10:09 PM PDT 24
Finished May 30 01:21:31 PM PDT 24
Peak memory 319796 kb
Host smart-a165365e-0957-4317-9968-36db20a9eae7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553790492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.3553790492
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2526346923
Short name T1044
Test name
Test status
Simulation time 913727200 ps
CPU time 59.79 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:11:09 PM PDT 24
Peak memory 262788 kb
Host smart-73baad1d-7e25-49f7-9444-897d6f792096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526346923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2526346923
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.1710112201
Short name T235
Test name
Test status
Simulation time 19026200 ps
CPU time 51.79 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:11:05 PM PDT 24
Peak memory 270448 kb
Host smart-0dba4205-574e-4381-8c96-7f2b241e2eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710112201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1710112201
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.2311593634
Short name T992
Test name
Test status
Simulation time 6912982100 ps
CPU time 177.32 seconds
Started May 30 01:10:11 PM PDT 24
Finished May 30 01:13:09 PM PDT 24
Peak memory 259044 kb
Host smart-85e9c06a-0285-4f2e-bf53-f7fdd1f4569a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311593634 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.2311593634
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1924650106
Short name T320
Test name
Test status
Simulation time 50560800 ps
CPU time 15.84 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:14:29 PM PDT 24
Peak memory 275804 kb
Host smart-3b0bc241-dad2-40f6-8631-5a2afd2a53fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924650106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1924650106
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3311580510
Short name T179
Test name
Test status
Simulation time 20187300 ps
CPU time 15.81 seconds
Started May 30 01:14:13 PM PDT 24
Finished May 30 01:14:31 PM PDT 24
Peak memory 275488 kb
Host smart-610867d1-74e6-43d8-b9d1-946dcac21fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311580510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3311580510
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.829091935
Short name T669
Test name
Test status
Simulation time 65391900 ps
CPU time 131.87 seconds
Started May 30 01:14:13 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 259560 kb
Host smart-0f4b1f34-26e5-4924-a7cb-122f659d6cf8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829091935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_ot
p_reset.829091935
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1193372314
Short name T893
Test name
Test status
Simulation time 16055400 ps
CPU time 15.19 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:14:29 PM PDT 24
Peak memory 274688 kb
Host smart-6030f64f-d64f-438c-8a83-ab43b16a64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193372314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1193372314
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2990348772
Short name T757
Test name
Test status
Simulation time 40025300 ps
CPU time 130.68 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 264332 kb
Host smart-62d88f01-64dc-43fb-827c-74cebbaa993e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990348772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2990348772
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1055369987
Short name T667
Test name
Test status
Simulation time 15160100 ps
CPU time 15.59 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:14:30 PM PDT 24
Peak memory 275764 kb
Host smart-6f83e55a-2b0f-4658-979c-461d4b653375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055369987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1055369987
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.3407262816
Short name T119
Test name
Test status
Simulation time 37819200 ps
CPU time 131.9 seconds
Started May 30 01:14:14 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 264444 kb
Host smart-d094811b-80ce-4dbd-abf2-4f5dd4b5f11f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407262816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.3407262816
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.3886542988
Short name T956
Test name
Test status
Simulation time 46777300 ps
CPU time 15.93 seconds
Started May 30 01:14:13 PM PDT 24
Finished May 30 01:14:31 PM PDT 24
Peak memory 275456 kb
Host smart-eb98ea46-faa4-47fd-bf47-a5311a4b242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886542988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3886542988
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.2404529735
Short name T910
Test name
Test status
Simulation time 41849200 ps
CPU time 128.81 seconds
Started May 30 01:14:13 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 260792 kb
Host smart-04a0b074-ca01-43ea-8e70-b288e066411e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404529735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.2404529735
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.4153294446
Short name T436
Test name
Test status
Simulation time 16369700 ps
CPU time 15.79 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:14:30 PM PDT 24
Peak memory 275724 kb
Host smart-9cecdd5f-ea01-4612-b8aa-23d20c0aee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153294446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4153294446
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.3186928711
Short name T1067
Test name
Test status
Simulation time 40632900 ps
CPU time 130.57 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 259608 kb
Host smart-386d2ff5-e426-4ab9-800a-4e8131b9d1e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186928711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.3186928711
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.3592078567
Short name T837
Test name
Test status
Simulation time 26007000 ps
CPU time 13.38 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 275896 kb
Host smart-209edf44-e8fe-40e6-a77e-6f3f448658e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592078567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3592078567
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.366088385
Short name T93
Test name
Test status
Simulation time 170885200 ps
CPU time 131.49 seconds
Started May 30 01:14:09 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 259732 kb
Host smart-e54d4f80-69a0-4dae-a851-08e29092d534
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366088385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.366088385
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3260206429
Short name T974
Test name
Test status
Simulation time 61685000 ps
CPU time 15.86 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:14:28 PM PDT 24
Peak memory 275632 kb
Host smart-5c863b79-6cef-4ca3-bd0b-1534cd705a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260206429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3260206429
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3366171484
Short name T662
Test name
Test status
Simulation time 44879900 ps
CPU time 129.19 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:16:21 PM PDT 24
Peak memory 259676 kb
Host smart-a0741a9c-9742-48b0-9596-d870803d73fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366171484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3366171484
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2436045070
Short name T700
Test name
Test status
Simulation time 89196300 ps
CPU time 15.61 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:14:30 PM PDT 24
Peak memory 275892 kb
Host smart-6dfb0155-c84c-4c7d-86ba-ab11c12de781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436045070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2436045070
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.4173370682
Short name T846
Test name
Test status
Simulation time 75263700 ps
CPU time 129.59 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 260964 kb
Host smart-2a34abe1-5439-4d30-8a7a-f347933c793a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173370682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.4173370682
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.2186531598
Short name T176
Test name
Test status
Simulation time 25467600 ps
CPU time 15.79 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:14:29 PM PDT 24
Peak memory 275936 kb
Host smart-878fe1ea-f9f4-455e-8004-ba23a17aa8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186531598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2186531598
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.4272709749
Short name T979
Test name
Test status
Simulation time 46306400 ps
CPU time 130.8 seconds
Started May 30 01:14:10 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 260832 kb
Host smart-1f3d682f-72df-40fa-bd77-9a3baf5fb77d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272709749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.4272709749
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.1830763523
Short name T564
Test name
Test status
Simulation time 60846200 ps
CPU time 13.41 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 264780 kb
Host smart-f0405b68-e87b-47a9-9f09-2a3f369bc5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830763523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1
830763523
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1245821499
Short name T892
Test name
Test status
Simulation time 16627700 ps
CPU time 15.57 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:10:43 PM PDT 24
Peak memory 275548 kb
Host smart-09a5efa1-751b-45eb-b806-9d44afcc8546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245821499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1245821499
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.1373216471
Short name T389
Test name
Test status
Simulation time 20249400 ps
CPU time 20.42 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 273212 kb
Host smart-179274a2-de6a-467f-af57-f8efb1e7daf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373216471 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.1373216471
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3729460299
Short name T1006
Test name
Test status
Simulation time 19075867100 ps
CPU time 2338.23 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:49:07 PM PDT 24
Peak memory 264496 kb
Host smart-da25b9ff-dcc2-4b4b-8d3d-6b6da5f309d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729460299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3729460299
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.1097032870
Short name T735
Test name
Test status
Simulation time 707052000 ps
CPU time 965.32 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:26:14 PM PDT 24
Peak memory 272996 kb
Host smart-335dc177-dd94-4113-9fe2-c513996dbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097032870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1097032870
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3283153430
Short name T53
Test name
Test status
Simulation time 1036615600 ps
CPU time 23.5 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:10:31 PM PDT 24
Peak memory 264784 kb
Host smart-1776b002-6dd1-412a-8c33-6a93c7e04352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283153430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3283153430
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2912442729
Short name T995
Test name
Test status
Simulation time 10018669600 ps
CPU time 81.2 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:11:48 PM PDT 24
Peak memory 321528 kb
Host smart-c53c0511-d87e-40ac-af55-607601e2e43d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912442729 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2912442729
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.154692492
Short name T855
Test name
Test status
Simulation time 15512600 ps
CPU time 13.37 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 258012 kb
Host smart-98dbb72a-e969-4172-9630-21d08c33d5ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154692492 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.154692492
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.1268524351
Short name T121
Test name
Test status
Simulation time 50133256100 ps
CPU time 819.16 seconds
Started May 30 01:10:09 PM PDT 24
Finished May 30 01:23:50 PM PDT 24
Peak memory 264096 kb
Host smart-ed8f9115-913e-472d-9371-5e94f121b4b9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268524351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.1268524351
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3739675788
Short name T313
Test name
Test status
Simulation time 7532614900 ps
CPU time 118.99 seconds
Started May 30 01:10:07 PM PDT 24
Finished May 30 01:12:08 PM PDT 24
Peak memory 262304 kb
Host smart-90a97cd8-3968-4157-9407-9191ad76621b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739675788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3739675788
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.3446187906
Short name T618
Test name
Test status
Simulation time 1949023000 ps
CPU time 204.73 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:13:33 PM PDT 24
Peak memory 289404 kb
Host smart-a8a7ef4a-4976-4616-8728-f1b9774bc1e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446187906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.3446187906
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2544940352
Short name T165
Test name
Test status
Simulation time 21416352300 ps
CPU time 248.59 seconds
Started May 30 01:10:15 PM PDT 24
Finished May 30 01:14:25 PM PDT 24
Peak memory 292912 kb
Host smart-8993743c-b62c-480e-bba5-74b11eb5e1b0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544940352 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2544940352
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.2603082169
Short name T753
Test name
Test status
Simulation time 4813448400 ps
CPU time 73.91 seconds
Started May 30 01:10:08 PM PDT 24
Finished May 30 01:11:24 PM PDT 24
Peak memory 264844 kb
Host smart-38ce2d7a-40d4-4b28-8417-c69888d91bff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603082169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.2603082169
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1215507030
Short name T1094
Test name
Test status
Simulation time 18713695700 ps
CPU time 160.48 seconds
Started May 30 01:10:22 PM PDT 24
Finished May 30 01:13:03 PM PDT 24
Peak memory 259904 kb
Host smart-367670ac-c2da-4067-8401-e778602321cb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121
5507030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1215507030
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.3747068312
Short name T825
Test name
Test status
Simulation time 6429148100 ps
CPU time 76.37 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:11:25 PM PDT 24
Peak memory 260480 kb
Host smart-02861763-42d2-4506-9cef-8a60c1cbeaf6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747068312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3747068312
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.501480262
Short name T245
Test name
Test status
Simulation time 26311500 ps
CPU time 13.28 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:10:37 PM PDT 24
Peak memory 264776 kb
Host smart-791c61ed-f8d8-4042-91be-dc97400e5ece
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501480262 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.501480262
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.572259576
Short name T78
Test name
Test status
Simulation time 10140001900 ps
CPU time 244.05 seconds
Started May 30 01:10:11 PM PDT 24
Finished May 30 01:14:16 PM PDT 24
Peak memory 273452 kb
Host smart-cc315b1d-f5a6-4873-a11b-61e21b792d82
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572259576 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_mp_regions.572259576
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2820231027
Short name T879
Test name
Test status
Simulation time 77761300 ps
CPU time 130.72 seconds
Started May 30 01:10:10 PM PDT 24
Finished May 30 01:12:22 PM PDT 24
Peak memory 263680 kb
Host smart-5910ac2c-52c2-4aac-b4b7-3046e86a3339
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820231027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2820231027
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.34981934
Short name T515
Test name
Test status
Simulation time 17014125200 ps
CPU time 601.31 seconds
Started May 30 01:10:05 PM PDT 24
Finished May 30 01:20:08 PM PDT 24
Peak memory 262164 kb
Host smart-eb0966ac-0855-446f-8683-e84185424bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34981934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.34981934
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1621994891
Short name T781
Test name
Test status
Simulation time 18302500 ps
CPU time 13.43 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:10:34 PM PDT 24
Peak memory 258388 kb
Host smart-a826fa9c-f2b4-45d4-93a0-5f4978e6ec08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621994891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1621994891
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.716194905
Short name T105
Test name
Test status
Simulation time 4694671300 ps
CPU time 992.89 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:26:41 PM PDT 24
Peak memory 287588 kb
Host smart-e2b990f4-da08-4b47-ba17-f54090239573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716194905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.716194905
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.315296625
Short name T884
Test name
Test status
Simulation time 1391330100 ps
CPU time 109.74 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:11:58 PM PDT 24
Peak memory 296656 kb
Host smart-afa8cd94-e204-4d03-919c-d1d2847a2eee
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315296625 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.315296625
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.2527324890
Short name T778
Test name
Test status
Simulation time 6040172500 ps
CPU time 155.97 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:12:50 PM PDT 24
Peak memory 281244 kb
Host smart-f4b14b75-cb94-44e0-8d64-d93a37ab503b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2527324890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2527324890
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3274287959
Short name T1017
Test name
Test status
Simulation time 1325174800 ps
CPU time 159.46 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:12:55 PM PDT 24
Peak memory 293936 kb
Host smart-bca7ca96-ffe0-48c7-b370-34151eda3cb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274287959 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3274287959
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1553727086
Short name T1072
Test name
Test status
Simulation time 28919548100 ps
CPU time 585.4 seconds
Started May 30 01:10:04 PM PDT 24
Finished May 30 01:19:51 PM PDT 24
Peak memory 313284 kb
Host smart-8abc43c5-0aac-4e8c-b24c-a7b610f5251f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553727086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.1553727086
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.301649523
Short name T1027
Test name
Test status
Simulation time 4902847300 ps
CPU time 808.61 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:23:43 PM PDT 24
Peak memory 327616 kb
Host smart-02626fa7-56c1-40b0-81af-ac903c014a07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301649523 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.301649523
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3973535905
Short name T940
Test name
Test status
Simulation time 32760900 ps
CPU time 27.88 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:10:50 PM PDT 24
Peak memory 273060 kb
Host smart-7081e8c2-b466-48bb-84c7-f1d811f6a49f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973535905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3973535905
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.2774001382
Short name T485
Test name
Test status
Simulation time 14704390600 ps
CPU time 686.94 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:21:40 PM PDT 24
Peak memory 319764 kb
Host smart-1021b671-e411-4c69-8768-0123af901720
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774001382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.2774001382
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.2427692464
Short name T583
Test name
Test status
Simulation time 6196280400 ps
CPU time 72.63 seconds
Started May 30 01:10:16 PM PDT 24
Finished May 30 01:11:29 PM PDT 24
Peak memory 262888 kb
Host smart-d46e659a-28e0-4283-8bf5-6668c9d3548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427692464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2427692464
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.4276259456
Short name T642
Test name
Test status
Simulation time 69415000 ps
CPU time 122.68 seconds
Started May 30 01:10:09 PM PDT 24
Finished May 30 01:12:13 PM PDT 24
Peak memory 275508 kb
Host smart-d2263bf0-5129-4eb4-aea4-7929ca3216cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276259456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.4276259456
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1506511576
Short name T555
Test name
Test status
Simulation time 3782246100 ps
CPU time 158.63 seconds
Started May 30 01:10:06 PM PDT 24
Finished May 30 01:12:46 PM PDT 24
Peak memory 258780 kb
Host smart-63b6a23e-44ed-4757-bb6b-826e3ecac15b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506511576 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.1506511576
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3579366919
Short name T433
Test name
Test status
Simulation time 17062200 ps
CPU time 15.88 seconds
Started May 30 01:14:11 PM PDT 24
Finished May 30 01:14:29 PM PDT 24
Peak memory 275592 kb
Host smart-5d3a076e-ae8c-4a3f-8444-bc4a69dd399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579366919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3579366919
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3362579214
Short name T756
Test name
Test status
Simulation time 277635000 ps
CPU time 133.05 seconds
Started May 30 01:14:12 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 260620 kb
Host smart-80bbde15-1403-41ab-af24-b04b955fd6cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362579214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3362579214
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3401439250
Short name T951
Test name
Test status
Simulation time 13472200 ps
CPU time 16.06 seconds
Started May 30 01:14:09 PM PDT 24
Finished May 30 01:14:27 PM PDT 24
Peak memory 275504 kb
Host smart-17d598e3-7dda-48a8-8465-ba5ccb3ce4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401439250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3401439250
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.1801610946
Short name T703
Test name
Test status
Simulation time 14345500 ps
CPU time 15.7 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 275376 kb
Host smart-b4774d5f-c947-4b21-8c65-c9b551b6c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801610946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1801610946
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.2039639030
Short name T716
Test name
Test status
Simulation time 46455700 ps
CPU time 132.18 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:39 PM PDT 24
Peak memory 261080 kb
Host smart-2334b614-241f-4833-987a-7aa3f65af8ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039639030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.2039639030
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1916577210
Short name T835
Test name
Test status
Simulation time 44597500 ps
CPU time 15.51 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 275776 kb
Host smart-435bf105-e235-4be0-b23c-a504beb64493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916577210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1916577210
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1621922388
Short name T126
Test name
Test status
Simulation time 36211300 ps
CPU time 130.65 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:37 PM PDT 24
Peak memory 260972 kb
Host smart-50401d36-6513-44a1-a972-06e750f092e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621922388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1621922388
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.535592856
Short name T823
Test name
Test status
Simulation time 149516100 ps
CPU time 13.55 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:39 PM PDT 24
Peak memory 275532 kb
Host smart-96785494-61fc-47a1-9bf9-5e067d233869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535592856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.535592856
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.4226376504
Short name T427
Test name
Test status
Simulation time 149849500 ps
CPU time 128.98 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:16:33 PM PDT 24
Peak memory 259828 kb
Host smart-79d6cd44-b12e-4fb1-ae47-0d5e6f8e0408
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226376504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.4226376504
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2016451900
Short name T474
Test name
Test status
Simulation time 13753500 ps
CPU time 15.8 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 275564 kb
Host smart-82cde545-abfd-473f-895d-796280bc8071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016451900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2016451900
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3626993016
Short name T537
Test name
Test status
Simulation time 74011000 ps
CPU time 129.92 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:16:35 PM PDT 24
Peak memory 259692 kb
Host smart-2032e707-5d3c-4bb6-b9b0-c49caa9fe534
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626993016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3626993016
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2933985147
Short name T772
Test name
Test status
Simulation time 25692600 ps
CPU time 15.62 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:14:40 PM PDT 24
Peak memory 274784 kb
Host smart-87c8fe11-f01f-451b-8a30-218a29df7af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933985147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2933985147
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.2241372097
Short name T94
Test name
Test status
Simulation time 46770800 ps
CPU time 129.53 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:16:36 PM PDT 24
Peak memory 261032 kb
Host smart-b8ed31a1-ae74-4157-839e-12266a565d92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241372097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.2241372097
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.835890442
Short name T832
Test name
Test status
Simulation time 27400700 ps
CPU time 15.44 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:14:40 PM PDT 24
Peak memory 275528 kb
Host smart-c878d6c6-72cb-40ae-8cdb-8a1fab4ddbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835890442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.835890442
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.304795273
Short name T793
Test name
Test status
Simulation time 161609100 ps
CPU time 111.2 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:16:16 PM PDT 24
Peak memory 259732 kb
Host smart-d7535a2a-34bc-406e-abd3-2430f6b71fdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304795273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_ot
p_reset.304795273
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.4057825201
Short name T374
Test name
Test status
Simulation time 14144300 ps
CPU time 15.41 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 275616 kb
Host smart-bf1525d8-b984-4197-8cdb-9677b04a91d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057825201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.4057825201
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2328404361
Short name T1048
Test name
Test status
Simulation time 38996300 ps
CPU time 131.05 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:38 PM PDT 24
Peak memory 259640 kb
Host smart-f95cc05c-36f7-41ee-a08a-ea322cfb69bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328404361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2328404361
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.605547668
Short name T949
Test name
Test status
Simulation time 22077500 ps
CPU time 15.88 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 275496 kb
Host smart-9fef6375-5a49-4b2f-906d-e44782b28185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605547668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.605547668
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2245740285
Short name T953
Test name
Test status
Simulation time 125717200 ps
CPU time 132.3 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:16:42 PM PDT 24
Peak memory 259724 kb
Host smart-cd1f59b9-f84b-464a-9b07-176f6c9cd9ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245740285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2245740285
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1629860637
Short name T818
Test name
Test status
Simulation time 97782300 ps
CPU time 13.84 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:10:33 PM PDT 24
Peak memory 264784 kb
Host smart-6643b7c5-d526-41c4-ae76-7aa06cf82f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629860637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
629860637
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2563223670
Short name T839
Test name
Test status
Simulation time 44053200 ps
CPU time 15.57 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 274940 kb
Host smart-bc8469ea-93df-4408-9b0b-38d0c572ffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563223670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2563223670
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.596453761
Short name T102
Test name
Test status
Simulation time 12729700 ps
CPU time 20.46 seconds
Started May 30 01:10:15 PM PDT 24
Finished May 30 01:10:37 PM PDT 24
Peak memory 272996 kb
Host smart-70abcd20-c817-441f-b7dc-61de59d5aa23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596453761 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.596453761
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2312066132
Short name T691
Test name
Test status
Simulation time 5723629700 ps
CPU time 2069.51 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:44:52 PM PDT 24
Peak memory 264820 kb
Host smart-25af79c8-86c3-42c9-b3c2-8768fc8ee48e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312066132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.2312066132
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3341976514
Short name T875
Test name
Test status
Simulation time 644556400 ps
CPU time 862.75 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:24:51 PM PDT 24
Peak memory 273036 kb
Host smart-ca7d5ef1-ac4c-4027-8d8a-c820913c7d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341976514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3341976514
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.3297691878
Short name T885
Test name
Test status
Simulation time 940409700 ps
CPU time 23.5 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:10:49 PM PDT 24
Peak memory 264856 kb
Host smart-caf25e1c-e890-4fd2-8054-031766452afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297691878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3297691878
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1317932180
Short name T1041
Test name
Test status
Simulation time 10012853100 ps
CPU time 129.04 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:12:32 PM PDT 24
Peak memory 361584 kb
Host smart-babd6edb-882a-43f9-8148-f9f56cc39425
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317932180 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1317932180
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1356262328
Short name T882
Test name
Test status
Simulation time 15074800 ps
CPU time 13.38 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 264764 kb
Host smart-e009abb2-a40a-461e-bcd9-884d627fcfb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356262328 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1356262328
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.50912224
Short name T863
Test name
Test status
Simulation time 160190114900 ps
CPU time 919.42 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:25:39 PM PDT 24
Peak memory 259724 kb
Host smart-ec3147fe-fd45-4f08-80fa-d8efb9ea92b8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50912224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.flash_ctrl_hw_rma_reset.50912224
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3198596091
Short name T451
Test name
Test status
Simulation time 1973844300 ps
CPU time 86.68 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:11:52 PM PDT 24
Peak memory 262224 kb
Host smart-298e7a21-3898-4a3c-a630-5eda74c6c58c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198596091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3198596091
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.975859062
Short name T323
Test name
Test status
Simulation time 1882999800 ps
CPU time 200.84 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 290484 kb
Host smart-92940c57-ffff-47a6-b092-eb6966ca8749
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975859062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.975859062
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3414450210
Short name T676
Test name
Test status
Simulation time 9168119900 ps
CPU time 137.39 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:12:41 PM PDT 24
Peak memory 292968 kb
Host smart-155d81d3-7bdc-42a3-896c-91664229de47
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414450210 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3414450210
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3080602258
Short name T35
Test name
Test status
Simulation time 1973320800 ps
CPU time 59.92 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:11:28 PM PDT 24
Peak memory 259520 kb
Host smart-ad5988e8-aacf-43e7-b9ed-8c36f73424fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080602258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3080602258
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.4031100509
Short name T1077
Test name
Test status
Simulation time 100961958100 ps
CPU time 209.25 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:13:49 PM PDT 24
Peak memory 259360 kb
Host smart-423ba7e2-3974-44db-a6f3-f5aff4ae699e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403
1100509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.4031100509
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3706079918
Short name T487
Test name
Test status
Simulation time 1680545900 ps
CPU time 67.49 seconds
Started May 30 01:10:25 PM PDT 24
Finished May 30 01:11:33 PM PDT 24
Peak memory 259760 kb
Host smart-dc575098-13a8-4ca4-91b8-fffc35fd26d4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706079918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3706079918
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1132931959
Short name T638
Test name
Test status
Simulation time 26091200 ps
CPU time 13.44 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:10:32 PM PDT 24
Peak memory 260064 kb
Host smart-8475a5a1-20d1-4a43-93fb-f2abab078515
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132931959 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1132931959
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.668766546
Short name T908
Test name
Test status
Simulation time 272576400 ps
CPU time 129.28 seconds
Started May 30 01:10:12 PM PDT 24
Finished May 30 01:12:22 PM PDT 24
Peak memory 261048 kb
Host smart-c8f01235-2901-4dbe-b00f-04b8447f9f42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668766546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.668766546
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.3581836502
Short name T932
Test name
Test status
Simulation time 1539357200 ps
CPU time 455.14 seconds
Started May 30 01:10:10 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 261232 kb
Host smart-f55a6425-4aa7-48c2-8f5f-ef945dace303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581836502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3581836502
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3403607247
Short name T244
Test name
Test status
Simulation time 8266030900 ps
CPU time 170.95 seconds
Started May 30 01:10:22 PM PDT 24
Finished May 30 01:13:14 PM PDT 24
Peak memory 258860 kb
Host smart-c3ed854f-d610-4c0f-9264-34cc0b96236d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403607247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3403607247
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.1545305014
Short name T985
Test name
Test status
Simulation time 109949300 ps
CPU time 171.77 seconds
Started May 30 01:10:14 PM PDT 24
Finished May 30 01:13:09 PM PDT 24
Peak memory 280460 kb
Host smart-59daf88e-04cb-4ff1-9f3c-ab4f0dc8acb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545305014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1545305014
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2690479369
Short name T584
Test name
Test status
Simulation time 127502400 ps
CPU time 33.99 seconds
Started May 30 01:10:22 PM PDT 24
Finished May 30 01:10:57 PM PDT 24
Peak memory 273104 kb
Host smart-5d039847-e1e1-42d9-85cf-00f76a88e290
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690479369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2690479369
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3838187535
Short name T919
Test name
Test status
Simulation time 509486800 ps
CPU time 102.11 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:12:08 PM PDT 24
Peak memory 281216 kb
Host smart-2571f6af-35d2-49bf-a97d-47e3a227490d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838187535 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.3838187535
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3679986644
Short name T905
Test name
Test status
Simulation time 549496000 ps
CPU time 124.69 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:12:32 PM PDT 24
Peak memory 281244 kb
Host smart-f4c99a97-b421-4df3-ad67-26575631128b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3679986644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3679986644
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.4115412584
Short name T924
Test name
Test status
Simulation time 1025586100 ps
CPU time 126.1 seconds
Started May 30 01:10:14 PM PDT 24
Finished May 30 01:12:22 PM PDT 24
Peak memory 293068 kb
Host smart-7f03947d-1dd4-41b0-a79e-633cb5545b47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115412584 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.4115412584
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.4144188289
Short name T592
Test name
Test status
Simulation time 3899399900 ps
CPU time 447.94 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 309016 kb
Host smart-e6efab14-ab28-46ad-b682-6af5bd2b5f1f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144188289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.4144188289
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2056715205
Short name T904
Test name
Test status
Simulation time 74622100 ps
CPU time 30.97 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:10:59 PM PDT 24
Peak memory 273112 kb
Host smart-340232ed-81ca-4964-8e62-34e92cf6116e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056715205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2056715205
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.4080679684
Short name T899
Test name
Test status
Simulation time 82179400 ps
CPU time 31.47 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:10:56 PM PDT 24
Peak memory 275104 kb
Host smart-e85b1447-3f04-4e83-80d3-d9a07399fc66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080679684 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.4080679684
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3315297024
Short name T1028
Test name
Test status
Simulation time 1650285000 ps
CPU time 68.14 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:11:36 PM PDT 24
Peak memory 262212 kb
Host smart-64500080-dc36-44cb-8df3-61f8fc80bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315297024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3315297024
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3865792853
Short name T464
Test name
Test status
Simulation time 95022400 ps
CPU time 168.25 seconds
Started May 30 01:10:13 PM PDT 24
Finished May 30 01:13:02 PM PDT 24
Peak memory 280168 kb
Host smart-44f67e74-2e3a-4331-bac3-cad679d93a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865792853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3865792853
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3056879060
Short name T975
Test name
Test status
Simulation time 2118734500 ps
CPU time 152.63 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:12:56 PM PDT 24
Peak memory 258528 kb
Host smart-0ea21fe4-fe51-46af-8b04-4fc7ff8e1021
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056879060 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3056879060
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1974679312
Short name T446
Test name
Test status
Simulation time 20779200 ps
CPU time 15.77 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 275864 kb
Host smart-f335b813-6cbb-4dea-9177-ebfab944a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974679312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1974679312
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1815812893
Short name T569
Test name
Test status
Simulation time 70965900 ps
CPU time 130.5 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:37 PM PDT 24
Peak memory 260860 kb
Host smart-f0ed2eb8-b901-4f1c-abce-344f8417fe90
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815812893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1815812893
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2970675674
Short name T767
Test name
Test status
Simulation time 72875400 ps
CPU time 15.97 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 275000 kb
Host smart-c6411acf-c809-4eee-bfe8-b4da39531cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970675674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2970675674
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.4286317708
Short name T1010
Test name
Test status
Simulation time 40837400 ps
CPU time 130.66 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:38 PM PDT 24
Peak memory 259636 kb
Host smart-bd13fae8-cfc7-4ea9-93d7-d1dcafa513bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286317708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.4286317708
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.993234739
Short name T480
Test name
Test status
Simulation time 23130200 ps
CPU time 15.91 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 275768 kb
Host smart-6d730ad0-faee-46a6-9bfa-e5c8f59299b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993234739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.993234739
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2676504912
Short name T730
Test name
Test status
Simulation time 38963900 ps
CPU time 134.31 seconds
Started May 30 01:14:39 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 259748 kb
Host smart-c198329c-3914-4d91-93b5-fd3477db17fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676504912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2676504912
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.760509575
Short name T788
Test name
Test status
Simulation time 13735700 ps
CPU time 15.77 seconds
Started May 30 01:14:28 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 275856 kb
Host smart-2e4445ad-021b-4dc8-bd02-f99e16ef4bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760509575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.760509575
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3381999967
Short name T1011
Test name
Test status
Simulation time 60125400 ps
CPU time 111.9 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:16:19 PM PDT 24
Peak memory 259716 kb
Host smart-3c73528d-9edd-430a-8955-08dbabf696b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381999967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3381999967
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.558279998
Short name T715
Test name
Test status
Simulation time 41080400 ps
CPU time 15.88 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 274776 kb
Host smart-ef40bd44-018a-48b9-999c-42fe7671b353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558279998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.558279998
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3789139911
Short name T127
Test name
Test status
Simulation time 38782400 ps
CPU time 130.26 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:16:36 PM PDT 24
Peak memory 259548 kb
Host smart-b7ddf904-0f3e-4895-8e62-bdcdb4272529
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789139911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3789139911
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.314489166
Short name T773
Test name
Test status
Simulation time 14036800 ps
CPU time 13.61 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:14:40 PM PDT 24
Peak memory 275368 kb
Host smart-e0281d33-dd4a-4313-9fac-a77a0d7f51f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314489166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.314489166
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.963393192
Short name T476
Test name
Test status
Simulation time 39773400 ps
CPU time 129.73 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:16:35 PM PDT 24
Peak memory 260844 kb
Host smart-0a268a81-107c-4dc2-a5a4-35ad7c9ccdfd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963393192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.963393192
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1084943468
Short name T1061
Test name
Test status
Simulation time 38758000 ps
CPU time 110.33 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:16:16 PM PDT 24
Peak memory 259836 kb
Host smart-bbce3516-a043-4c09-934a-41ad46802e35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084943468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1084943468
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3517771464
Short name T909
Test name
Test status
Simulation time 77713600 ps
CPU time 13.9 seconds
Started May 30 01:14:24 PM PDT 24
Finished May 30 01:14:39 PM PDT 24
Peak memory 274652 kb
Host smart-5a5aa683-910b-4202-90af-a0247aedb402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517771464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3517771464
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.2472210614
Short name T430
Test name
Test status
Simulation time 147730400 ps
CPU time 111.41 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:16:19 PM PDT 24
Peak memory 260776 kb
Host smart-d3dc17cf-ea87-4279-8e0b-b98cd13d856c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472210614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.2472210614
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3840623072
Short name T988
Test name
Test status
Simulation time 16133700 ps
CPU time 15.37 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 275788 kb
Host smart-dc69a91c-edef-41a0-bb5b-5246947be547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840623072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3840623072
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.3292734739
Short name T421
Test name
Test status
Simulation time 77981600 ps
CPU time 132.57 seconds
Started May 30 01:14:25 PM PDT 24
Finished May 30 01:16:39 PM PDT 24
Peak memory 264516 kb
Host smart-e111967c-a8f5-4b37-bb0d-6a0e5992014e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292734739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.3292734739
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.3696562513
Short name T1015
Test name
Test status
Simulation time 13368500 ps
CPU time 16.38 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 275028 kb
Host smart-e279181a-72e0-49d0-926a-cf6da78f2eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696562513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3696562513
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.3473240154
Short name T130
Test name
Test status
Simulation time 70685000 ps
CPU time 110.55 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:16:17 PM PDT 24
Peak memory 259520 kb
Host smart-d09f1064-1b39-4cfe-b130-4ec0766fc39b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473240154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.3473240154
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.857042364
Short name T633
Test name
Test status
Simulation time 98750000 ps
CPU time 13.12 seconds
Started May 30 01:10:17 PM PDT 24
Finished May 30 01:10:31 PM PDT 24
Peak memory 264804 kb
Host smart-6003698b-53c6-4c51-b8f2-0b00bb131981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857042364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.857042364
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1354192848
Short name T172
Test name
Test status
Simulation time 40820600 ps
CPU time 15.53 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:10:35 PM PDT 24
Peak memory 275556 kb
Host smart-03823f85-b986-481d-b5e1-2fa746fe7ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354192848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1354192848
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3049420734
Short name T611
Test name
Test status
Simulation time 12096400 ps
CPU time 22.14 seconds
Started May 30 01:10:17 PM PDT 24
Finished May 30 01:10:40 PM PDT 24
Peak memory 273160 kb
Host smart-d41b586c-c166-462a-b8aa-f40b5cea4262
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049420734 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3049420734
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3817664533
Short name T283
Test name
Test status
Simulation time 26594386400 ps
CPU time 2283.85 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:48:36 PM PDT 24
Peak memory 264068 kb
Host smart-93d0128a-e98d-427e-9e0c-e6c3a3703996
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817664533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.3817664533
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2009699680
Short name T646
Test name
Test status
Simulation time 607191100 ps
CPU time 818.13 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:24:03 PM PDT 24
Peak memory 272996 kb
Host smart-2aee8123-7ad1-483b-9969-643f505b66cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009699680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2009699680
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.213088692
Short name T577
Test name
Test status
Simulation time 10034658000 ps
CPU time 64.23 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:11:23 PM PDT 24
Peak memory 292564 kb
Host smart-b665294b-3d2f-42c0-af3a-385995020227
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213088692 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.213088692
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3533023379
Short name T921
Test name
Test status
Simulation time 15397100 ps
CPU time 13.01 seconds
Started May 30 01:10:17 PM PDT 24
Finished May 30 01:10:31 PM PDT 24
Peak memory 258920 kb
Host smart-c27a862c-598e-4454-9e6f-ee74c4e9aecc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533023379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3533023379
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.370905196
Short name T145
Test name
Test status
Simulation time 40126061800 ps
CPU time 822.53 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:24:04 PM PDT 24
Peak memory 263620 kb
Host smart-f2890b73-e64e-4835-909b-b9758a059442
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370905196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.370905196
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.3606805729
Short name T315
Test name
Test status
Simulation time 4614956400 ps
CPU time 130.65 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:12:32 PM PDT 24
Peak memory 259792 kb
Host smart-cfd7a45b-501d-433e-8e64-503cd5abfbe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606805729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.3606805729
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.911414126
Short name T1068
Test name
Test status
Simulation time 9662427700 ps
CPU time 204.39 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:13:57 PM PDT 24
Peak memory 283556 kb
Host smart-200f8ad9-bf2e-44fd-b643-5b13ab3870ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911414126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.911414126
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2336763390
Short name T888
Test name
Test status
Simulation time 8150792100 ps
CPU time 146.96 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:12:59 PM PDT 24
Peak memory 291632 kb
Host smart-901f41c2-a547-46b4-a43d-09c1236c8589
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336763390 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2336763390
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.990373656
Short name T654
Test name
Test status
Simulation time 4173330000 ps
CPU time 66.69 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:11:39 PM PDT 24
Peak memory 264732 kb
Host smart-e7836819-7563-4eb3-bb44-8b92bde195cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990373656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.990373656
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.359880993
Short name T978
Test name
Test status
Simulation time 100314651500 ps
CPU time 206.35 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:13:48 PM PDT 24
Peak memory 260008 kb
Host smart-6a03f430-ae7d-4320-8043-08e9d6044ba3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359
880993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.359880993
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.491710647
Short name T479
Test name
Test status
Simulation time 6477508800 ps
CPU time 67.78 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:11:40 PM PDT 24
Peak memory 260408 kb
Host smart-0c9f2a73-b879-43c3-a1bc-b4b4cf5f33f7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491710647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.491710647
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.657749596
Short name T929
Test name
Test status
Simulation time 73302800 ps
CPU time 13.12 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:10:32 PM PDT 24
Peak memory 259268 kb
Host smart-ab50d1ca-82e0-4223-91a8-4ada4a276c2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657749596 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.657749596
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2083798440
Short name T744
Test name
Test status
Simulation time 1569779600 ps
CPU time 142.89 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:12:47 PM PDT 24
Peak memory 262512 kb
Host smart-f4af69b8-fd1f-4a89-a97c-6df7d6d11797
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083798440 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2083798440
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3260191172
Short name T610
Test name
Test status
Simulation time 88826400 ps
CPU time 110.7 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:12:09 PM PDT 24
Peak memory 264224 kb
Host smart-5f3752de-33b0-4425-9f84-df422be26157
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260191172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3260191172
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.386367146
Short name T1070
Test name
Test status
Simulation time 1438283400 ps
CPU time 484.67 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:18:29 PM PDT 24
Peak memory 262100 kb
Host smart-4c88108f-f996-491c-987f-a327dc25cda2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386367146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.386367146
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3548426259
Short name T973
Test name
Test status
Simulation time 36980600 ps
CPU time 13.33 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:10:34 PM PDT 24
Peak memory 258360 kb
Host smart-407353fd-f625-4ea5-bf64-d0227ff75d03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548426259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.3548426259
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2915245929
Short name T790
Test name
Test status
Simulation time 248479600 ps
CPU time 546.59 seconds
Started May 30 01:10:23 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 282240 kb
Host smart-f0af2997-18d5-45cc-975d-4c6d523fc092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915245929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2915245929
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.3506122165
Short name T327
Test name
Test status
Simulation time 96907500 ps
CPU time 35.03 seconds
Started May 30 01:10:20 PM PDT 24
Finished May 30 01:10:56 PM PDT 24
Peak memory 274152 kb
Host smart-f5bb6daf-e91a-4a90-85ed-f9ab7c764685
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506122165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.3506122165
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1256869010
Short name T211
Test name
Test status
Simulation time 1189846000 ps
CPU time 120.9 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:12:23 PM PDT 24
Peak memory 296724 kb
Host smart-298980c3-e55f-4944-b293-ed4b6ef788f8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256869010 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.1256869010
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.593783323
Short name T785
Test name
Test status
Simulation time 951249100 ps
CPU time 148.32 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:13:01 PM PDT 24
Peak memory 281280 kb
Host smart-f57f03e2-e3f6-4ad2-aabb-7d4a4a4a2fb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
593783323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.593783323
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.768665973
Short name T432
Test name
Test status
Simulation time 651638900 ps
CPU time 140.2 seconds
Started May 30 01:10:29 PM PDT 24
Finished May 30 01:12:51 PM PDT 24
Peak memory 281228 kb
Host smart-76c70713-1514-44db-a4f2-17c86a932a89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768665973 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.768665973
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.2405873867
Short name T581
Test name
Test status
Simulation time 12095537400 ps
CPU time 460.65 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:18:13 PM PDT 24
Peak memory 310920 kb
Host smart-6cf4f0d5-17ee-4cbb-93ed-4c40687ab02f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405873867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.2405873867
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.864206474
Short name T967
Test name
Test status
Simulation time 184148300 ps
CPU time 30.05 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:10:49 PM PDT 24
Peak memory 275128 kb
Host smart-4784eb3f-ee7a-4122-aab9-9cb3fd603dc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864206474 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.864206474
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3970080759
Short name T877
Test name
Test status
Simulation time 14232822100 ps
CPU time 489.35 seconds
Started May 30 01:10:31 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 319800 kb
Host smart-0ccd08e3-031b-4e6e-b9f8-84803c31adc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970080759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3970080759
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3625419899
Short name T395
Test name
Test status
Simulation time 1444040700 ps
CPU time 68.31 seconds
Started May 30 01:10:17 PM PDT 24
Finished May 30 01:11:26 PM PDT 24
Peak memory 262860 kb
Host smart-f9e84c84-0fdd-431a-aa1b-32f4b4994394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625419899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3625419899
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3810517233
Short name T303
Test name
Test status
Simulation time 33593700 ps
CPU time 122.09 seconds
Started May 30 01:10:18 PM PDT 24
Finished May 30 01:12:21 PM PDT 24
Peak memory 275464 kb
Host smart-2a1c92a6-0c6c-48f8-9ab8-72010eef75bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810517233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3810517233
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3514550455
Short name T748
Test name
Test status
Simulation time 2498442500 ps
CPU time 171.75 seconds
Started May 30 01:10:21 PM PDT 24
Finished May 30 01:13:13 PM PDT 24
Peak memory 258884 kb
Host smart-a81d21f3-ec3d-49af-af2e-9555d92da525
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514550455 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.3514550455
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2631403582
Short name T643
Test name
Test status
Simulation time 106227200 ps
CPU time 14.27 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:11:02 PM PDT 24
Peak memory 264696 kb
Host smart-816e4fdc-a5a3-4149-82d8-e536b10939af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631403582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
631403582
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.2953552077
Short name T804
Test name
Test status
Simulation time 27586600 ps
CPU time 13.47 seconds
Started May 30 01:10:46 PM PDT 24
Finished May 30 01:11:00 PM PDT 24
Peak memory 275776 kb
Host smart-54666392-e875-45ab-81be-5c536acd9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953552077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2953552077
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.1645660848
Short name T168
Test name
Test status
Simulation time 28531100 ps
CPU time 21.92 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:11:10 PM PDT 24
Peak memory 264844 kb
Host smart-e6a267d5-eeef-4a36-84c8-71f263787afa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645660848 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.1645660848
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.2205554513
Short name T697
Test name
Test status
Simulation time 22262242000 ps
CPU time 2253.72 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:48:01 PM PDT 24
Peak memory 263836 kb
Host smart-4e325a7b-5eda-4f81-b218-74eb54f00310
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205554513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.2205554513
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.1044502640
Short name T160
Test name
Test status
Simulation time 369740300 ps
CPU time 760.68 seconds
Started May 30 01:10:25 PM PDT 24
Finished May 30 01:23:06 PM PDT 24
Peak memory 270916 kb
Host smart-9e39fdd9-1de1-4ac9-ac79-60f4f830f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044502640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1044502640
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1407871856
Short name T942
Test name
Test status
Simulation time 604325000 ps
CPU time 27.3 seconds
Started May 30 01:10:24 PM PDT 24
Finished May 30 01:10:53 PM PDT 24
Peak memory 264784 kb
Host smart-5f98bfe7-5f0c-42e9-ada0-ecfe2c4d3709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407871856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1407871856
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4236907770
Short name T122
Test name
Test status
Simulation time 10034198900 ps
CPU time 102.85 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:12:28 PM PDT 24
Peak memory 274772 kb
Host smart-4dcb7e24-73db-49a6-84d0-90d589715436
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236907770 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.4236907770
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.4154682475
Short name T990
Test name
Test status
Simulation time 15479400 ps
CPU time 13.28 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:10:59 PM PDT 24
Peak memory 258000 kb
Host smart-c8719906-3c5a-489b-b438-b232dbf94835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154682475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.4154682475
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.1392395040
Short name T481
Test name
Test status
Simulation time 80136365300 ps
CPU time 855.58 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:24:42 PM PDT 24
Peak memory 263632 kb
Host smart-2f98b29a-1dc4-4373-ae04-1cc0de776f76
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392395040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.1392395040
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.3166672019
Short name T317
Test name
Test status
Simulation time 8396692000 ps
CPU time 50.59 seconds
Started May 30 01:10:25 PM PDT 24
Finished May 30 01:11:16 PM PDT 24
Peak memory 262288 kb
Host smart-57705163-ffc6-4ec6-b718-3ec71aeb7951
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166672019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.3166672019
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3034897440
Short name T751
Test name
Test status
Simulation time 6211367000 ps
CPU time 219.91 seconds
Started May 30 01:10:46 PM PDT 24
Finished May 30 01:14:27 PM PDT 24
Peak memory 290488 kb
Host smart-fc694964-626a-4ef5-b31c-0d206e655558
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034897440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3034897440
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.517406555
Short name T649
Test name
Test status
Simulation time 24333823100 ps
CPU time 276.34 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 291340 kb
Host smart-a2d65e9f-05d7-4f57-9df3-f00b40c1c21a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517406555 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.517406555
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2799853291
Short name T944
Test name
Test status
Simulation time 4743493100 ps
CPU time 77.34 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:12:03 PM PDT 24
Peak memory 264832 kb
Host smart-7ba7974e-c1a7-4296-b3d5-a0c76e46ca3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799853291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2799853291
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3087558493
Short name T680
Test name
Test status
Simulation time 343713078700 ps
CPU time 268.24 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:15:14 PM PDT 24
Peak memory 264916 kb
Host smart-4f18765a-ec3a-436d-b230-aebc91f13754
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308
7558493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3087558493
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.964631524
Short name T463
Test name
Test status
Simulation time 1708721200 ps
CPU time 69.72 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:11:36 PM PDT 24
Peak memory 260272 kb
Host smart-1dfd249e-6226-488b-8469-7a003f3c80e1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964631524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.964631524
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1261870781
Short name T280
Test name
Test status
Simulation time 29571300 ps
CPU time 13.3 seconds
Started May 30 01:10:46 PM PDT 24
Finished May 30 01:11:00 PM PDT 24
Peak memory 259280 kb
Host smart-cca2623c-2dfa-4034-adea-f6232a04a895
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261870781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1261870781
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.1069472059
Short name T99
Test name
Test status
Simulation time 31840148400 ps
CPU time 272.77 seconds
Started May 30 01:10:25 PM PDT 24
Finished May 30 01:14:59 PM PDT 24
Peak memory 273440 kb
Host smart-c417a1b6-e55f-4610-87db-b962a1d66287
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069472059 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.1069472059
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.4016517315
Short name T387
Test name
Test status
Simulation time 78845800 ps
CPU time 112.84 seconds
Started May 30 01:10:26 PM PDT 24
Finished May 30 01:12:20 PM PDT 24
Peak memory 260940 kb
Host smart-d67315b7-2d8b-4bf8-8687-69774e05cbe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016517315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.4016517315
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2283682186
Short name T330
Test name
Test status
Simulation time 64591400 ps
CPU time 109.54 seconds
Started May 30 01:10:27 PM PDT 24
Finished May 30 01:12:18 PM PDT 24
Peak memory 261444 kb
Host smart-c94eb0b7-a4c4-4cd6-bae7-69c13f3873f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283682186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2283682186
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.2279826873
Short name T798
Test name
Test status
Simulation time 21908900 ps
CPU time 13.42 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:10:59 PM PDT 24
Peak memory 258132 kb
Host smart-0b065700-d569-4958-a222-e0032e169ac5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279826873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.2279826873
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.764166930
Short name T497
Test name
Test status
Simulation time 2075717600 ps
CPU time 976.04 seconds
Started May 30 01:10:19 PM PDT 24
Finished May 30 01:26:36 PM PDT 24
Peak memory 285424 kb
Host smart-4d75861d-7c3f-4905-86ad-a3061f6b319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764166930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.764166930
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3818441887
Short name T87
Test name
Test status
Simulation time 623851100 ps
CPU time 34.11 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:11:19 PM PDT 24
Peak memory 273108 kb
Host smart-6aa23eba-bf8a-4297-9b2a-218fdd7336c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818441887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3818441887
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.2030889845
Short name T1057
Test name
Test status
Simulation time 2066182300 ps
CPU time 102.67 seconds
Started May 30 01:10:29 PM PDT 24
Finished May 30 01:12:13 PM PDT 24
Peak memory 296752 kb
Host smart-69a9285b-a35e-48d0-8751-3012a9337052
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030889845 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.2030889845
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3107743665
Short name T212
Test name
Test status
Simulation time 450702300 ps
CPU time 109.07 seconds
Started May 30 01:10:45 PM PDT 24
Finished May 30 01:12:35 PM PDT 24
Peak memory 281284 kb
Host smart-0a851d99-780e-4705-bc15-d3a270ddee35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3107743665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3107743665
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.4237807180
Short name T1004
Test name
Test status
Simulation time 447419000 ps
CPU time 109.32 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:12:34 PM PDT 24
Peak memory 294052 kb
Host smart-3d7bacb3-d2a3-473e-a35c-ea64ae8218c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237807180 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.4237807180
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3217035950
Short name T843
Test name
Test status
Simulation time 18148282300 ps
CPU time 492.09 seconds
Started May 30 01:10:46 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 313280 kb
Host smart-db756d1b-8215-4f4a-ad1e-50e47b696b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217035950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.3217035950
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.1498888820
Short name T685
Test name
Test status
Simulation time 50435400 ps
CPU time 30.68 seconds
Started May 30 01:10:47 PM PDT 24
Finished May 30 01:11:18 PM PDT 24
Peak memory 273008 kb
Host smart-20495d24-22bd-4c91-8449-3fab6e07e52a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498888820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.1498888820
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3909780103
Short name T1071
Test name
Test status
Simulation time 260907000 ps
CPU time 31.03 seconds
Started May 30 01:10:44 PM PDT 24
Finished May 30 01:11:16 PM PDT 24
Peak memory 274340 kb
Host smart-6a3eeeb9-57c4-4184-934b-c5bae39e8f19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909780103 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3909780103
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2934469129
Short name T1034
Test name
Test status
Simulation time 2204922000 ps
CPU time 79.66 seconds
Started May 30 01:10:46 PM PDT 24
Finished May 30 01:12:07 PM PDT 24
Peak memory 263872 kb
Host smart-b951d937-50fc-49de-b352-62d205e4ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934469129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2934469129
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.1567483666
Short name T955
Test name
Test status
Simulation time 111944500 ps
CPU time 121.77 seconds
Started May 30 01:10:16 PM PDT 24
Finished May 30 01:12:19 PM PDT 24
Peak memory 275784 kb
Host smart-3d23505b-9069-435b-a3d6-ceb6af87fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567483666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1567483666
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2384394819
Short name T722
Test name
Test status
Simulation time 9228283500 ps
CPU time 125.78 seconds
Started May 30 01:10:28 PM PDT 24
Finished May 30 01:12:34 PM PDT 24
Peak memory 258828 kb
Host smart-bba4e859-cbda-4d7f-ae27-e9010a118060
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384394819 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2384394819
Directory /workspace/9.flash_ctrl_wo/latest
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