Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	322298	1		T1	1		T2	1		T3	1
all_values[1]	322298	1		T1	1		T2	1		T3	1
all_values[2]	322298	1		T1	1		T2	1		T3	1
all_values[3]	322298	1		T1	1		T2	1		T3	1
all_values[4]	322298	1		T1	1		T2	1		T3	1
all_values[5]	322298	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	650865	1		T1	6		T2	6		T3	6
auto[1]	1282923	1		T26	30472		T34	166292		T28	6428

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	941392	1		T1	4		T2	4		T3	4
auto[1]	992396	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	322159	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	139	1		T265	4		T266	6		T267	3
all_values[1]	auto[0]	auto[1]	322131	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	167	1		T265	4		T266	2		T267	4
all_values[2]	auto[0]	auto[0]	1570	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	60	1		T265	1		T266	3		T267	1
all_values[2]	auto[1]	auto[0]	320606	1		T26	7618		T34	41573		T28	1607
all_values[2]	auto[1]	auto[1]	62	1		T265	1		T266	2		T267	3
all_values[3]	auto[0]	auto[0]	1585	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	70	1		T362	2		T266	3		T267	2
all_values[3]	auto[1]	auto[0]	71526	1		T26	241		T28	1607		T31	309
all_values[3]	auto[1]	auto[1]	249117	1		T26	7377		T34	41573		T31	370
all_values[4]	auto[0]	auto[0]	1100	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	552	1		T4	1		T5	1		T6	1
all_values[4]	auto[1]	auto[0]	222904	1		T26	6151		T34	39860		T28	1
all_values[4]	auto[1]	auto[1]	97742	1		T26	1467		T34	1713		T28	1606
all_values[5]	auto[0]	auto[0]	1508	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	130	1		T21	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	320593	1		T26	7618		T34	41573		T28	1607
all_values[5]	auto[1]	auto[1]	67	1		T265	2		T266	3		T344	2