Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	237483	1		T4	216		T5	700		T6	1639
auto[FlashEraseBank]	261606	1		T5	360		T6	1716		T9	484

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	248179	1		T4	16		T5	1060		T6	1275
auto[FlashOpProgram]	229931	1		T4	192		T6	2080		T18	128
auto[FlashOpErase]	16979	1		T4	8		T18	14		T8	8
auto[FlashOpInvalid]	4000	1		T86	200		T87	200		T298	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	248179	1		T4	16		T5	1060		T6	1275
op[FlashOpProgram]	229931	1		T4	192		T6	2080		T18	128
op[FlashOpErase]	16979	1		T4	8		T18	14		T8	8
read_erase_read	674	1		T4	3		T18	2		T8	1
read_prog_read	792	1		T6	7		T9	4		T7	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	355098	1		T5	809		T6	2788		T9	830
auto[FlashPartInfo]	140559	1		T4	216		T5	248		T6	562
auto[FlashPartInfo1]	886	1		T5	1		T6	2		T9	2
auto[FlashPartInfo2]	2546	1		T5	2		T6	3		T9	5

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	175730	1		T5	809		T6	971		T9	270
auto[FlashPartData]	auto[FlashOpProgram]	171651	1		T6	1817		T9	560		T7	5
auto[FlashPartData]	auto[FlashOpErase]	3775	1		T53	41		T66	41		T67	33
auto[FlashPartData]	auto[FlashOpInvalid]	3942	1		T86	196		T87	194		T298	198
auto[FlashPartInfo]	auto[FlashOpRead]	70107	1		T4	16		T5	248		T6	300
auto[FlashPartInfo]	auto[FlashOpProgram]	57217	1		T4	192		T6	262		T18	128
auto[FlashPartInfo]	auto[FlashOpErase]	13183	1		T4	8		T18	14		T8	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	52	1		T86	4		T87	4		T298	2
auto[FlashPartInfo1]	auto[FlashOpRead]	715	1		T5	1		T6	2		T9	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T20	32		T87	1		T63	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T87	1		T116	1		T93	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T87	2		T93	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1627	1		T5	2		T6	2		T9	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	899	1		T6	1		T9	1		T39	3
auto[FlashPartInfo2]	auto[FlashOpErase]	18	1		T67	1		T104	1		T106	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T410	2		-	-		-	-